CN205562695U - Hierarchical test system of relay protection time delay - Google Patents

Hierarchical test system of relay protection time delay Download PDF

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CN205562695U
CN205562695U CN201620036088.7U CN201620036088U CN205562695U CN 205562695 U CN205562695 U CN 205562695U CN 201620036088 U CN201620036088 U CN 201620036088U CN 205562695 U CN205562695 U CN 205562695U
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module
data
relay protection
test
signal
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卜强生
袁宇波
宋亮亮
宋爽
杨毅
高磊
刘玙
嵇建飞
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Jiangsu Electric Power Co Ltd
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State Grid Corp of China SGCC
Electric Power Research Institute of State Grid Jiangsu Electric Power Co Ltd
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Abstract

The utility model discloses a based on the hierarchical test system of relay protection time delay of luo shi coil transient state emulation, it includes host computer and test host computer, the test host computer includes main control unit, data generation module, data acquisition module, DA module, AD module and gathers interface module. The utility model discloses can at first generate based on the transient state simulation model of luo shi coil under the power system fault circumstances through the host computer, then send transient state simulated data to the test host computer in real time, the number of pass sends differential little analog signal to the collector according to generation module and DA module, sets up whole spaced developments analog data. Regard as the standard source with the little analog signal of the aforesaid simultaneously, gather serial data signal, merging cells's 9 again 2 data, digital relay protection's GOOSE data and intelligent terminal's switching value to a whole set of test system is establish, time delay and the whole time delay of these signals for the transient state standard source can be tested respectively.

Description

A kind of relay protection action delay hierarchical test system
Technical field
This utility model relates to relay protection detection technique field, a kind of relay protection action delay hierarchical test system based on Luo-coil transient emulation.
Background technology
Intelligent substation, as the important component part of intelligent grid, is the Main way of current power grid construction.In intelligent substation process of construction, Luo-coil electricity electronic mutual inductor has obtained certain application.It is Faraday law of electromagnetic induction and Ampere circuit law that Luo-coil measures the ultimate principle of electric current, Luo-coil is to be the air core coil that skeleton is constituted by nonmagnetic substance, in air core coil, secondary is wound on non magnetic skeleton, the linearity making this sensor without ferromagnetic material is good, unsaturation is also without hysteresis, and therefore, air core coil has excellent frequency response ability.But voltage e (t) of Luo-coil secondary output becomes differential relationship with primary current Ip (t), the electronic mutual inductor of Luo-coil principle is the signal after differential due to its output, have to be reduced by integral element, the impact that the change of the brought transient characterisitics of link of this differential to integration ultimately causes also lacks enough test data at present.Two kinds of technical schemes that the electronic mutual inductor integral element of the most domestic Luo-coil principle is taked substantially, one is Software Integration, and another kind is hardware integration.Both modes diversity in transient characterisitics is also a unknown number.This impact by the process of differential to integration for the impact of current temporary state signal and for digital relay protection device of based on electronic mutual inductor movement time is also a lack of enough test foundations.
Digital relay protection device is all to add digital signal based on IEC61950-9-2 communication standard in relay protection front end at present; then test the movement time of digital relay protection device, the impact that this test mode has cast aside the transient characterisitics of electronic mutual inductor own and transient state time delay is brought.At present the transient test of electronic mutual inductor be substantially use the mode of heavy current impact produce test required for the big electric current of transient process, the most again test product is tested together with combining unit.The hardware test condition high investment that this mode is relied on is big, needs to build primary system physics Dynamic Model Test room, and this is essentially such that digital relay protection device characteristic test movement time based on electronic mutual inductor Temporal Data becomes impossible.And the time-delay characteristics of electronic mutual inductor are substantially and record under stable situation, this can not directly reflect the molar behavior time of digital relay protection device based on electronic mutual inductor.
So from the point of view of current present situation; in the urgent need to a kind of device by electronic mutual inductor being carried out transient emulation and outputing signal to electronic mutual inductor; then test classification time delay and the molar behavior time delay of digital relay protection device of the too many levels such as electronic transformer collector, combining unit, digital relay protection device, intelligent terminal, thus record the molar behavior time delay of digital relay protection device in transient process and the relation of links.
Utility model content
The technical problems to be solved in the utility model is: provide a kind of relay protection action delay hierarchical test system; Luo-coil electronic mutual inductor transient process can be emulated by it, and then realizes the global test of relation between whole group of digital relay protection device characteristic movement time and links action delay.
Technical scheme that this utility model is taked is particularly as follows: a kind of relay protection action delay hierarchical test system, including host computer, test main frame, and electronic transformer collector, combining unit, digital relay protection device and the intelligent terminal being sequentially connected with;
Test main frame includes master controller, data generation module, data acquisition module, D/A module, A/D module and acquisition interface module;
Described acquisition interface module includes FT3 signal optical fibre serial line interface, 9-2 signal optical fibre Ethernet interface, GOOSE signal optical fibre Ethernet interface and switch acquisition interface, and the outfan of above-mentioned each interface connects data acquisition module respectively;The input of described FT3 signal optical fibre serial line interface connects the outfan of electronic transformer collector; the input of 9-2 signal optical fibre Ethernet interface connects the outfan of combining unit; the input of GOOSE signal optical fibre Ethernet interface connects the outfan of digital relay protection device, and the input of switch acquisition interface connects the outfan of intelligent terminal;
Host computer sends Luo-coil Temporal Data to the master controller of test main frame and generates order, data generation module receives data genaration order from master controller, and then generate transient test data, and the transient test data of generation are exported to electronic transformer collector after D/A module is changed, simultaneously as in standard source output to A/D module;The outfan of A/D module connects data acquisition module;
Data acquisition module gathers FT3 signal, 9-2 signal, GOOSE signal and on-off model by acquisition interface module, then by the data in above-mentioned signal, by master controller output to host computer.
In this utility model, host computer uses computer to realize, and master controller, data generation module and data acquisition module in test main frame can use existing control chip respectively.Master controller in test main frame is responsible for being connected with host computer, and the Luo-coil Temporal Data received being generated order by master controller transmission to data generation module, the digital quantity of generation is sent to the generation test of D/A module and uses little analog signals by data generation module.Data acquisition module gathers standard source little analog quantity voltage signal, the fiber optic serial signal of harvester, Ethernet 9-2 signal, GOOSE signal and the hard contact point signal of switching value respectively, and stamps accurate markers respectively.The above-mentioned standard source of data collecting module collected, harvester, combining unit, digital relay protection device and the source signal of intelligent terminal, and complete to synchronize to calculate, deliver in host computer after the data that will have synchronized and then realize test.Described Luo-coil Temporal Data generates order i.e. Luo-coil Transient simulation data source, and it is prior art, can determine the characteristic point of follow-up generated transient test data signal.Computer realizes Luo-coil Temporal Data by software and generates the generation of order, and to carry out relevant delay test according to the data collected be prior art;Utilize existing control chip to generate order according to Luo-coil Temporal Data and generate transient test data signal also for prior art
Further, also including crystal oscillator in test main frame of the present utility model, the clock signal output terminal of crystal oscillator connects master controller, data acquisition module and data generation module respectively.Crystal oscillator can be selected for OCXO50 constant-temperature crystal oscillator, the operating temperature of-40 to 85 degree, and less than the temperature drift characteristic of 1ppb, the low phase noise of-160dBc/1KHz, maximum 10ppb/year's is low aging.This High Precision Crystal Oscillator is master controller, data generation module and data acquisition module provide timeticks, it is ensured that the accuracy of sequencing contro, and long-term stability.
The master controller of described test main frame uses model to be the embedded microprocessor of MPC8247.Master controller is with PowerPC as core, and MPC8247 embedded microprocessor is that Freescale company produces, and belongs to PowerQUICC II series, comprises a kernel based on PowerPC MPC603e, and a communication process kernel CPM.The design of its double-core has powerful disposal ability and higher integrated level, reduces the composition expense of system, simplifies the design of circuit board, reduce power consumption.The generation of high-frequency data, and test data collection completed by master controller.
Described data generation module and data acquisition module are respectively adopted fpga chip.FPGA uses the Spartan3 series of products XC3S1500 of Xilinx, includes 1,500,000 system doors, 32 special multiplier, and 4 digital dock management modules, logical resource enriches, and the speed of service is fast.Utilize the accurate capability of sequential control of FPGA, can complete media access control sublayer design, media access control sublayer and the Interface design of ethernet controller of Ethernet, Ethernet data receives, the control of DAC, A/D data acquisition, completes high-speed serial data simultaneously and receives and switching value reception.
Described D/A module uses model to be the digital to analog converter of AD5683R, its 16 single channel transducers produced for ADI company, and relative accuracy is ± 2 LSB INL, built-in 2 ppm/ ° of C 2.5V reference voltage sources;Use joint space-efficient 2mm × 2mm 8 pin LFCSP and 10 pin MSOP encapsulation, more function can be realized in less circuit board space;The total non-alignment error of 2mV, it is not necessary to initial calibration or adjustment;4kV HBM ESD rated value, it is achieved that system robustness.
A/D module uses 18 AD7690 chips of AD company, and this chip is 1.5 LSB INL, 400 kSPS difference ADC, and its differential input characteristic has higher interference free performance.
Beneficial effect
This utility model sets up Luo-coil Transient simulation model in the case of electric power system fault by host computer, then Luo-coil transient state simulation data source signal is sent in real time the data generation module to test main frame, and then by D/A module, the little analog signals of differential is sent the harvester to electronic mutual inductor, set up the dynamic analog data at whole interval.Simultaneously using the small voltage signal of D/A output as standard source; gather the serial data signal output of harvester, the 9-2 data output of combining unit, the GOOSE data output of digital relay protection device and the output switch parameter of intelligent terminal again thus set up a whole set of test system, these signals can be tested respectively relative to the time delay of transient state standard source and molar behavior time delay.
This utility model for digital relay protection device molar behavior time delay based on electronic mutual inductor in intelligent substation and and point link time delay between relation propose the test system of a kind of high efficient and reliable; the transient performance power of test of electronic mutual inductor can be improved; improving transformer station's digital relay protection device adaptation ability for electronic mutual inductor, the safe and stable operation for electrical network provides safeguard.Specifically can bring following effect:
1. precise time is measured, and uses constant temperature essence to bestir oneself the clock standard for whole system so that the metering system of too many levels has a relatively accurate markers;
2. adaptability improves, because electronic mutual inductor producer harvester output protocol is essentially privatization agreement, and this utility model system can support the adaptive analytic of many producers agreement;
3. standard source back production, it is ensured that the measuring accuracy of whole test system, carries out back production to standard source, has avoided data source precision that may be present itself and latency issue;
4. transient state time precision is high, and multi-signal can carry out time test simultaneously, is suitable for transient process capturing technology, accurately to measure the initial time of fault;
5. multisource synchronization, whole system test process uses analog quantity as benchmark, tests respectively high-speed serial data, 9-2 data, GOOSE data and the time of switching value analogue signal, uses FPGA as data acquisition module, it is possible to achieve multidata precise synchronization.
Accompanying drawing explanation
Fig. 1 show this utility model system structure schematic block diagram.
Detailed description of the invention
Further illustrate below in conjunction with the drawings and specific embodiments.
As shown in Figure 1; this utility model relay protection based on Luo-coil transient emulation action delay hierarchical test system includes host computer, test main frame, and electronic transformer collector, combining unit, digital relay protection device and the intelligent terminal being sequentially connected with;
Test main frame includes master controller, data generation module, data acquisition module, D/A module, A/D module and acquisition interface module;
Described acquisition interface module includes that outfan connects the FT3 signal optical fibre serial line interface of data acquisition module, 9-2 signal optical fibre Ethernet interface, GOOSE signal optical fibre Ethernet interface and switch acquisition interface respectively;The input of described FT3 signal optical fibre serial line interface connects the outfan of electronic transformer collector; the input of 9-2 signal optical fibre Ethernet interface connects the outfan of combining unit; the input of GOOSE signal optical fibre Ethernet interface connects the outfan of digital relay protection device, and the input of switch acquisition interface connects the outfan of intelligent terminal;
In host computer, available existing software engineering realizes data source generation module and delay test module;Data source generation module is used for building Luo-coil Transient simulation model, and generates simulation data source;Delay test module can include electronic mutual inductor delay test unit, relay protection delay test unit and intelligent terminal's test cell movement time respectively, for the test of corresponding data;Above-mentioned it is all prior art.
Data source generation module in host computer generates Luo-coil Temporal Data and generates order, and export to the master controller of test main frame, data generation module in test main frame receives Luo-coil Temporal Data from master controller and generates order, and then generate transient test data, and the transient test data of generation are exported to electronic transformer collector after D/A module is changed, simultaneously as in standard source output to A/D module;The outfan of A/D module connects data acquisition module;
Data acquisition module gathers FT3 signal, 9-2 signal, GOOSE signal and on-off model by acquisition interface module, then extracts the data in above-mentioned signal, by the delay test module of master controller output to host computer;
According to the data received; the time-delay characteristics of the electronic mutual inductor delay test unit testing electronic transformer collector in delay test module; relay protection delay test unit testing combining unit time delay, digital relay protection device movement time, intelligent terminal movement time, and relay protection molar behavior time delay.
Master controller in test main frame is responsible for being connected with host computer, and sends the Temporal Data source received to data generation module, and digital quantity is sent to the generation test of D/A module and uses little analog signals by data generation module.Data acquisition module gathers standard source little analog quantity voltage signal, the fiber optic serial signal of harvester, Ethernet 9-2 signal, GOOSE signal and the hard contact point signal of switching value respectively, and stamps accurate markers respectively.The above-mentioned standard source of data collecting module collected, harvester, combining unit, digital relay protection device and the source signal of intelligent terminal; and complete to synchronize to calculate; deliver to electronic mutual inductor and the digital relay protection device delay test module of host computer after the data that will have synchronized, and then realize test.
Embodiment
In embodiment shown in Fig. 1, upper computer software uses VC++ visual programming, builds Luo-coil transient process data source generation module and electronic mutual inductor and digital relay protection device delay test module respectively, and two modules are completely independent.Data source generation module is output as the differential signal of Luo-coil.
Also including crystal oscillator in test main frame, the clock signal output terminal of crystal oscillator connects master controller, data acquisition module and data generation module respectively.Crystal oscillator selects OCXO50 constant-temperature crystal oscillator, the operating temperature of-40 to 85 degree, and less than the temperature drift characteristic of 1ppb, the low phase noise of-160dBc/1KHz, maximum 10ppb/year's is low aging.This High Precision Crystal Oscillator provides timeticks for PowerPC and FPGA, it is ensured that the accuracy of sequencing contro, and long-term stability.
The master controller of test main frame uses model to be the embedded microprocessor of MPC8247.Master controller is with PowerPC as core, and MPC8247 embedded microprocessor is that Freescale company produces, and belongs to PowerQUICC II series, comprises a kernel based on PowerPC MPC603e, and a communication process kernel CPM.The design of its double-core has powerful disposal ability and higher integrated level, reduces the composition expense of system, simplifies the design of circuit board, reduce power consumption.The generation of high-frequency data, and test data collection completed by master controller.
Data generation module and data acquisition module are respectively adopted fpga chip.FPGA uses the Spartan3 series of products XC3S1500 of Xilinx, includes 1,500,000 system doors, 32 special multiplier, and 4 digital dock management modules, logical resource enriches, and the speed of service is fast.Utilize the accurate capability of sequential control of FPGA, can complete media access control sublayer design, media access control sublayer and the Interface design of ethernet controller of Ethernet, Ethernet data receives, the control of DAC, A/D data acquisition, completes high-speed serial data simultaneously and receives and switching value reception.
D/A module uses model to be the digital to analog converter of AD5683R, its 16 single channel transducers produced for ADI company, and relative accuracy is ± 2 LSB INL, built-in 2 ppm/ ° of C 2.5V reference voltage sources;Use joint space-efficient 2mm × 2mm 8 pin LFCSP and 10 pin MSOP encapsulation, more function can be realized in less circuit board space;The total non-alignment error of 2mV, it is not necessary to initial calibration or adjustment;4kV HBM ESD rated value, it is achieved that system robustness.
A/D module uses 18 AD7690 chips of AD company, and this chip is 1.5 LSB INL, 400 kSPS difference ADC, and its differential input characteristic has higher interference free performance.
Fiber optic Ethernet interface uses the LXT971 fiber optic Ethernet controller of Intel Company.LXT971 is single port 10/100M double speed quick ether controller, its compatible IEEE802.3;Support 10Base5,10Base2,10BaseT, 100BASE-X, 100BASE-TX, 100BASE-FX, and can automatically detect connected medium, select Agilent AFBR5803 as fiber optic network transceiver.High speed serialization receives and uses Agilent AFBR2416 as fiber optic network transceiver, has the reliability of high-speed transfer.
This utility model is by setting up Luo-coil Transient simulation model in the case of electric power system fault, then Luo-coil transient emulation signal is sent in real time the data generation module to test main frame, and then by D/A module, the little analog signals of differential is sent the harvester to electronic mutual inductor, set up the dynamic analog data at whole interval.Simultaneously using the small voltage signal of D/A output as standard source; gather the serial data signal output of harvester, the 9-2 data output of combining unit, the GOOSE data output of digital relay protection device and the output switch parameter of intelligent terminal again thus set up a whole set of test system, these signals can be tested respectively relative to the time delay of transient state standard source and molar behavior time delay.

Claims (7)

1. a relay protection action delay hierarchical test system, is characterized in that,
Including host computer, test main frame, and electronic transformer collector, combining unit, digital relay protection device and the intelligent terminal being sequentially connected with;
Test main frame includes master controller, data generation module, data acquisition module, D/A module, A/D module and acquisition interface module;
Described acquisition interface module includes FT3 signal optical fibre serial line interface, 9-2 signal optical fibre Ethernet interface, GOOSE signal optical fibre Ethernet interface and switch acquisition interface, and the outfan of above-mentioned each interface connects data acquisition module respectively;The input of described FT3 signal optical fibre serial line interface connects the outfan of electronic transformer collector; the input of 9-2 signal optical fibre Ethernet interface connects the outfan of combining unit; the input of GOOSE signal optical fibre Ethernet interface connects the outfan of digital relay protection device, and the input of switch acquisition interface connects the outfan of intelligent terminal;
Host computer sends Luo-coil Temporal Data to the master controller of test main frame and generates order, data generation module receives data genaration order from master controller, and then generate transient test data, and the transient test data of generation are exported to electronic transformer collector after D/A module is changed, simultaneously as in standard source output to A/D module;The outfan of A/D module connects data acquisition module;
Data acquisition module gathers FT3 signal, 9-2 signal, GOOSE signal and on-off model by acquisition interface module, then by the data in above-mentioned signal, by master controller output to host computer.
Relay protection action delay hierarchical test system the most according to claim 1, is characterized in that, also includes crystal oscillator in test main frame, and the clock signal output terminal of crystal oscillator connects master controller, data acquisition module and data generation module respectively.
Relay protection action delay hierarchical test system the most according to claim 2, is characterized in that, described crystal oscillator uses OCXO50 constant-temperature crystal oscillator.
Relay protection action delay hierarchical test system the most according to claim 1 and 2, is characterized in that, the master controller of described test main frame uses model to be the embedded microprocessor of MPC8247.
Relay protection action delay hierarchical test system the most according to claim 1 and 2, is characterized in that, described data generation module and data acquisition module are respectively adopted fpga chip.
Relay protection action delay hierarchical test system the most according to claim 1 and 2, is characterized in that, the digital to analog converter chip that described D/A module uses model to be AD5683R.
Relay protection action delay hierarchical test system the most according to claim 1 and 2, is characterized in that, the analog-digital converter chip that described A/D module uses model to be AD7690.
CN201620036088.7U 2016-01-13 2016-01-13 Hierarchical test system of relay protection time delay Active CN205562695U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109085441A (en) * 2018-09-26 2018-12-25 云南电网有限责任公司电力科学研究院 A kind of fault waveform playback system and method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109085441A (en) * 2018-09-26 2018-12-25 云南电网有限责任公司电力科学研究院 A kind of fault waveform playback system and method
CN109085441B (en) * 2018-09-26 2021-02-02 云南电网有限责任公司电力科学研究院 Fault waveform playback system and method

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