CN205541959U - Word line drive circuit - Google Patents
Word line drive circuit Download PDFInfo
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- CN205541959U CN205541959U CN201620330306.8U CN201620330306U CN205541959U CN 205541959 U CN205541959 U CN 205541959U CN 201620330306 U CN201620330306 U CN 201620330306U CN 205541959 U CN205541959 U CN 205541959U
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- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Abstract
The utility model discloses a word line drive circuit, including voltage regulator, address decoding circuit and terminal drive circuit, the signal input part and the address bus of address decoding circuit are connected, the signal battery input and the outside power of address decoding circuit are connected, and the signal output part of address decoding circuit and terminal drive circuit's signal input part are connected for when applying outside power input fixed voltage, decode address signal, and output control signal is with the drive terminal drive circuit, voltage regulator's input and outside power are connected, voltage regulator's output with terminal drive circuit's signal battery input is connected for adjust the fixed voltage of input, apply with the change terminal drive circuit's voltage, terminal drive circuit's signal output part is connected with memory cell, is used for the drive memory cell's word line. The utility model discloses can reduce the consumption, and the time of reducing the charge -discharge.
Description
Technical field
This utility model relates to memory circuitry, particularly relates to a kind of word line driving circuit.
Background technology
Flash storage needs to choose a wordline when wiping or write operation, and is input in the memory element in this wordline by program voltage (VPP).Because the operation read or write needs the voltage being applied to memory element to be different, so in the operating process wiped or write, needing to be varied multiple times the magnitude of voltage of VPP.Change vpp voltage value every time and typically require value relatively low for VPP bleed off to, such as supply voltage VDD, then with booster circuits such as electric charge pumps, VPP is re-established target voltage.
During the continuous recharge-discharge of program voltage VPP, owing to program voltage VPP is applied separately in address decoding circuitry and end drive circuit, address decoding circuitry includes most capacitive load, easily causes the waste of electric charge when VPP is charged-discharges simultaneously need to longer discharge and recharge time.
Utility model content
In view of this, this utility model embodiment provides a kind of word line driving circuit, it is possible to reduces power consumption, and reduces the time of discharge and recharge.
This utility model embodiment provides a kind of word line driving circuit, including voltage regulator, address decoding circuitry and end drive circuit；
The signal input part of described address decoding circuitry is connected with address bus；The power supply signal input of described address decoding circuitry is connected with outside power supply, the signal output part of address decoding circuitry is connected with the signal input part of end drive circuit, for when the power supply outside applying inputs fixed voltage, address signal is decoded, and exports control signal to drive described end drive circuit；
The input of described voltage regulator is connected with outside power supply, the outfan of described voltage regulator is connected with the power supply signal input of described end drive circuit, for the fixed voltage of input is adjusted, to change the voltage being applied to described end drive circuit；
The signal output part of described end drive circuit is connected with memory element, for driving the wordline of described memory element.
Further, described end drive circuit includes the first PMOS transistor, the second PMOS transistor, the first nmos pass transistor and the second nmos pass transistor；
The grid of described first PMOS transistor is connected with the first signal output part of address decoding circuitry；The source electrode of described first PMOS transistor is connected with the outfan of described voltage regulator, and is connected with the substrate of described first PMOS transistor；The drain electrode of described first PMOS transistor is connected with the source electrode of the second PMOS transistor, and the substrate of described first PMOS transistor and the substrate of the second PMOS transistor connect；
The grid of described second PMOS transistor is connected with the secondary signal outfan of described address decoding circuitry；The drain electrode of described second PMOS transistor is connected with the drain electrode of described first nmos pass transistor, and is connected with wordline；
The grid of described first nmos pass transistor is connected with the secondary signal outfan of described address decoding circuitry；The source electrode of described first nmos pass transistor is connected with the substrate of described first nmos pass transistor, and ground connection；
The grid of described second nmos pass transistor is connected with the first signal output part of described address decoding circuitry；The drain electrode of described second nmos pass transistor is connected with wordline, and the source electrode of described second nmos pass transistor is connected with the substrate of described second nmos pass transistor, and ground connection.
Further, the fixed voltage of voltage regulator input is more than the voltage of output.
Further, the magnitude of voltage of voltage regulator output is respectively 0V, 5V and 7V.
Further, described voltage regulator includes the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the first resistance and the second resistance；
The source electrode of the 3rd PMOS transistor is connected with outside power supply；The drain electrode of the 3rd PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor；The grid of described 3rd PMOS transistor is connected with the grid of described 4th PMOS transistor and the drain electrode of described 3rd PMOS crystal respectively；
The grid of described 3rd nmos pass transistor is connected with the input of described second resistance；The source electrode of described 3rd nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor；
The source ground of described 5th nmos pass transistor, the grid of described 5th nmos pass transistor is connected with outside bias supply；
The source electrode of described 4th PMOS transistor is connected with outside power supply, and the drain electrode of described 4th PMOS transistor is connected with the described drain electrode of the 4th nmos pass transistor and the grid of the 5th PMOS transistor respectively；
The source electrode of described 4th nmos pass transistor and the drain electrode of the 5th nmos pass transistor connect, and the grid of described 4th nmos pass transistor is connected with outside electric charge pump；
The source electrode of described 5th PMOS transistor is connected with outside power supply；The drain electrode of described 5th PMOS transistor power supply signal input with the input of described first resistance and described end drive circuit respectively is connected；
The outfan of described first resistance is connected with the input of described second resistance；The output head grounding of described second resistance.
Further, described bias supply, for controlling the conducting of the 5th nmos pass transistor, and make the electric current flowing through the 5th nmos pass transistor keep stable.
Further, described electric charge pump, for controlling the conducting of the 4th nmos pass transistor, and control to flow through the electric current of the 4th nmos pass transistor, to control the voltage difference between grid and the source electrode of the 5th PMOS transistor.
A kind of word line driving circuit that this utility model embodiment provides, by being applied to fixed voltage in address decoding circuitry and being adjusted changing the voltage being input to end drive circuit to the fixed voltage of input by voltage regulator, the wordline of memory element can be driven, and reduce power consumption, save the time of discharge and recharge.
Accompanying drawing explanation
The detailed description that non-limiting example is made made with reference to the following drawings by reading, other features, objects and advantages of the present utility model will become more apparent upon:
Fig. 1 a is the structure chart of a kind of word line driving circuit that this utility model embodiment one provides；
Fig. 1 b be this utility model embodiment one provide outside power supply input fixed voltage and voltage regulator regulation after voltage graph；
Fig. 2 a is the structure chart of a kind of word line driving circuit that this utility model embodiment two provides；
Fig. 2 b is the structure chart of the voltage regulator that this utility model embodiment two provides.
Detailed description of the invention
The utility model is described in further detail with embodiment below in conjunction with the accompanying drawings.It is understood that specific embodiment described herein is used only for explaining this utility model, rather than to restriction of the present utility model.It also should be noted that, for the ease of describing, accompanying drawing illustrate only the part relevant to this utility model rather than full content.
Embodiment one
Fig. 1 a is the structure chart of a kind of word line driving circuit that this utility model embodiment one provides, and as shown in Figure 1a, described word line driving circuit, including voltage regulator 10, address decoding circuitry 20 and end drive circuit 30.
The signal input part of address decoding circuitry 20 is connected with address bus 40；The power supply signal input of address decoding circuitry 20 is connected with outside power supply 50, the signal output part of address decoding circuitry 20 is connected with the signal input part of end drive circuit 30, for when the power supply 50 outside applying inputs fixed voltage, address signal is decoded, and exports control signal to drive end drive circuit 30.Wherein, it is high level signal and low level signal respectively that address bus 40 is input to the address signal of address decoding circuitry 20, magnitude of voltage device internal voltage value VDD of high level signal, and the magnitude of voltage of low level signal is 0.After address signal is decoded by address decoding circuitry 20, exporting control signal, the control signal of output is the address signal after decoding.The magnitude of voltage of control signal is respectively the magnitude of voltage VPP and 0 of outside power supply input.
The input of voltage regulator 10 is connected with outside power supply 50, and the outfan of voltage regulator 10 is connected with the power supply signal input of end drive circuit 30, for being adjusted by the fixed voltage of input, to change the voltage being applied to end drive circuit 30.The signal output part of end drive circuit 30 is connected with memory element 60, for driving the wordline 70 of memory element 60.Wherein, the fixed voltage of voltage regulator 10 input is more than the voltage of output.The magnitude of voltage of voltage regulator 10 output is respectively 0V, 5V and 7V.Wherein, when memory element 60 is carried out read operation, the magnitude of voltage of voltage regulator 10 output is 5V, when memory element 60 is carried out write operation, the magnitude of voltage of voltage regulator 10 output is 7V, and when to memory element 60 without operation, the magnitude of voltage of voltage regulator 10 output is 0V.
In the present embodiment, as shown in Figure 1a, when memory element 60 being carried out read or write by above-mentioned circuit, the fixed voltage of outside power supply 50 is input to address decoding circuitry 20 and voltage regulator 10, the fixed voltage of input is adjusted by voltage regulator 10, voltage after regulation is inputed to end drive circuit 30, magnitude of voltage required during to reach memory element 60 is carried out read or write.When end drive circuit 30 selects wordline 70 that memory element 60 is carried out read or write, need the control of the control signal that address decoding circuitry 20 exports.As the voltage VPP that address decoding circuitry 20 is fixed by outside power supply 50 input, the address signal of input is decoded, and export control signal, the magnitude of voltage of control signal is respectively VPP and 0, when end drive circuit 30 inputs different control signals, the state of the driving of wordline 70 is also different.Wherein, as shown in Figure 1 b, the fixed voltage 1 of outside power supply input is more than the voltage 2 after voltage regulator regulates to the voltage after the fixed voltage of the power supply input of outside and voltage regulator regulation, and the voltage after voltage regulator regulation is changed in time.
By above-mentioned method, address decoding circuitry 20 have input the fixed voltage of the power supply 50 of outside, save the time of discharge and recharge, reduce power consumption, and by voltage regulator 10, the fixed voltage of outside power supply input is adjusted, and the voltage after regulation is inputed to end drive circuit 30, make above-mentioned circuit when wordline 70 drives, it is possible to the operation that memory element 60 is read or write.
Present embodiments provide a kind of word line driving circuit, by being applied to fixed voltage in address decoding circuitry and being adjusted changing the voltage being input to end drive circuit to the fixed voltage of input by voltage regulator, the operation that memory element is read or write by the wordline of memory element with realization can be driven, and reduce power consumption, save the time of discharge and recharge.
Embodiment two
Fig. 2 a is the structure chart of a kind of word line driving circuit that the present embodiment two provides, and as shown in Figure 2 a, word line driving circuit, including voltage regulator 10, address decoding circuitry 20 and end drive circuit 30.The fixed voltage of outside power supply 50 output inputs to address decoding circuitry 20 and voltage regulator 10 respectively；When the fixed voltage of outside power supply 50 is input to address decoding circuitry 20, the address signal come from address bus 40 is decoded by address decoding circuitry 20, and exports control signal (address signal after decoding) to end drive circuit 30.When the voltage of end drive circuit 30 input voltage regulation device 10 output, control signal controls the end drive circuit 30 driving to wordline, to complete the read or write to memory element 60, wherein, address decoding circuitry 20 one end ground connection.
On the basis of above-described embodiment, as shown in Figure 2 a, described end drive circuit 30 includes the first PMOS transistor the 301, second PMOS transistor the 302, first nmos pass transistor 303 and the second nmos pass transistor 304.
Wherein, the grid of the first PMOS transistor 301 is connected with the first signal output part 201 of address decoding circuitry 20；The source electrode of the first PMOS transistor 301 is connected with the outfan of voltage regulator 10, and is connected with the substrate of the first PMOS transistor 301；The drain electrode of the first PMOS transistor 301 is connected with the source electrode of the second PMOS transistor 302, and the substrate of the first PMOS transistor 301 and the substrate of the second PMOS transistor 302 connect.The grid of the second PMOS transistor 302 is connected with the secondary signal outfan 202 of address decoding circuitry 20；The drain electrode of the second PMOS transistor 302 is connected with the drain electrode of the first nmos pass transistor 303, and is connected with wordline 70.First signal output part 201 of address decoding circuitry 20 exports control signal, and the magnitude of voltage of control signal is respectively VPP and 0, and the magnitude of voltage of the control signal of secondary signal outfan 202 output of address decoding circuitry is respectively VPP and 0.
The grid of the first nmos pass transistor 303 is connected with the secondary signal outfan 202 of address decoding circuitry 20；The source electrode of the first nmos pass transistor 303 and the substrate of the first nmos pass transistor 303 connect, and ground connection；The grid of the second nmos pass transistor 304 is connected with the first signal output part 201 of address decoding circuitry 20；The drain electrode of the second nmos pass transistor 304 is connected with wordline 70, and the source electrode of the second nmos pass transistor 304 and the substrate of the second nmos pass transistor 304 connect, and ground connection.
As shown in Figure 2 a, when end drive circuit 30 drives wordline 70 that memory element 60 is carried out read or write, outside power supply 50 all inputs fixing voltage to address decoding circuitry 20 and voltage regulator 10, after the address signal of address bus 40 is decoded by address decoding circuitry 20, export control signal by the first signal output part 201 and secondary signal outfan 202.When the magnitude of voltage of the control signal that the first signal output part 201 and the secondary signal outfan 202 of address decoding circuitry export is 0, the voltage of the grid of the first PMOS transistor 301 and the grid of the second PMOS transistor 302 is 0；First PMOS transistor 301 turns on, and the second PMOS transistor 302 turns on, and the first nmos pass transistor 303 ends, and the second nmos pass transistor 304 ends.The fixed voltage that outside power supply 50 inputs is adjusted by voltage regulator 10, and the voltage after modulation is input to the first PMOS transistor 301, voltage signal is through the second PMOS transistor 302, drive the operation that memory element 60 is read or write by wordline 70, when the voltage of voltage signal is 5V, memory element 60 is carried out read operation, when the voltage of power supply signal is 7V, the operation that memory element 60 is write.
When memory element is carried out read or write, need the voltage being input to memory element is constantly adjusted.In the present embodiment, the fixed voltage of outside power supply input is adjusted by voltage regulator, and different voltage is input to end drive circuit, so that end drive circuit drives wordline, it is achieved the operation different to memory element.Owing to outside power supply is fixed voltage to address decoding circuitry input, therefore when memory element is carried out read or write, the voltage being input to address decoding circuitry immobilizes, and makes the discharge and recharge time of address decoding circuitry reduce, and reduces power consumption.
As shown in Figure 2 a, when being 0 when the first signal output part 201 of address decoding circuitry is different from the magnitude of voltage of the control signal that secondary signal outfan 202 exports, it is impossible to wordline 70 is driven, and then the operation that memory element 60 can not be read or write.Such as, when the first signal output part 201 of address decoding circuitry 20 is respectively 0 and VPP with the magnitude of voltage of the control signal of secondary signal outfan 202 output, first PMOS transistor 301 turns on, second PMOS transistor 302 is ended, therefore, the voltage signal of voltage regulator 10 input is after the first PMOS transistor 301, it is impossible to by the second PMOS transistor 302, and then wordline 70 can not be driven the operation read or write memory element 60 with realization.
And for example, when the first signal output part 201 of address decoding circuitry 20 is VPP with the magnitude of voltage of the control signal of secondary signal outfan 202 output, first PMOS transistor 301 and the second PMOS transistor 302 are turned off, therefore, the voltage signal of voltage regulator 10 input all can not pass through the first PMOS transistor 301 and the second PMOS transistor 302, and therefore wordline 70 can not be driven the operation read or write memory element 60 with realization.
In the present embodiment, as shown in Figure 2 b, voltage regulator includes the 3rd PMOS transistor the 101, the 4th PMOS transistor the 102, the 5th PMOS transistor the 103, the 3rd nmos pass transistor the 104, the 4th nmos pass transistor the 105, the 5th nmos pass transistor the 106, first resistance 107 and the second resistance 108.
Wherein, the source electrode of the 3rd PMOS transistor 101 is connected with outside power supply 50；The drain electrode of the 3rd PMOS transistor 101 is connected with the drain electrode of the 3rd nmos pass transistor 104；The grid of the 3rd PMOS transistor 101 is connected with the grid of the 4th PMOS transistor 102 and the drain electrode of the 3rd PMOS transistor 101 respectively；The grid of the 3rd nmos pass transistor 104 and the input of the second resistance 108 connect；The source electrode of the 3rd nmos pass transistor 104 and the drain electrode of the 5th nmos pass transistor 106 connect；The source ground of the 5th nmos pass transistor 106, the grid of the 5th nmos pass transistor 106 is connected with outside bias supply 109；Wherein, bias supply 109, for controlling the conducting of the 5th nmos pass transistor 106, and make the electric current flowing through the 5th nmos pass transistor 106 keep stable.
In the present embodiment, the source electrode of the 4th PMOS transistor 102 is connected with outside power supply 50, and the drain electrode of the 4th PMOS transistor 102 is connected with the drain electrode of the 4th nmos pass transistor 105 and the grid of the 5th PMOS transistor 103 respectively；The source electrode of the 4th nmos pass transistor 105 and the drain electrode of the 5th nmos pass transistor 106 connect, and the grid of the 4th nmos pass transistor 105 is connected with outside electric charge pump 110.The source electrode of the 5th PMOS transistor 103 is connected with outside power supply 50；The drain electrode of the 5th PMOS transistor 103 is connected with the input of the first resistance 107 and the power supply signal input of end drive circuit 30 respectively；The outfan of the first resistance 107 and the input of the second resistance 108 connect；The output head grounding of the second resistance 108.Wherein, electric charge pump, for controlling the conducting of the 4th nmos pass transistor 105, and control the electric current flowing through the 4th nmos pass transistor 105 with the voltage difference between grid and the source electrode of control the 5th PMOS transistor 103.
As shown in Figure 2 b, when the fixed voltage of outside power supply 50 input is adjusted by voltage regulator, the resistance ratio being input to the voltage of the 4th nmos pass transistor 105 grid or regulation the first resistance 107 and the second resistance 108 by regulation electric charge pump 110 is realized.Wherein, the voltage VREF of the grid that electric charge pump 110 is input to the 4th nmos pass transistor 105 represents, voltage regulator is input to the voltage VPP0 of end drive circuit 30 and represents, the voltage VF of the grid of the 3rd nmos pass transistor 104 represents, the voltage VG of the grid of the 5th PMOS transistor 103 represents, resistance R1 of the first resistance 107 represents, resistance R2 of the second resistance 108 represents.
As shown in Figure 2 b, when current stabilization in voltage regulator, VREF with VF is identical, i.e. VREF=VPP0 × R2/ (R1+R2), after deformation, and VPP0=VREF × (R1+R2)/R2.Therefore, when the fixed voltage of outside power supply 50 input is adjusted by voltage regulator, voltage VREF and/or first resistance 107 and the resistance ratio of the second resistance 108 of the grid of the 4th nmos pass transistor 105 it is input to, it is possible to realize the voltage VPP0 being input to end drive circuit is changed by regulation electric charge pump 110.
nullWherein，Realize principle identical for VREF with VF as follows: when electric charge pump 110 is input to the grid voltage VREF of the 4th nmos pass transistor 105 more than the grid voltage VF of the 3rd nmos pass transistor 104，The electric current flowing through the 4th nmos pass transistor 105 increases，Constant (flowing through the electric current of the 3rd nmos pass transistor 104 with the electric current sum flowing through the 4th nmos pass transistor 105 is to flow through the electric current of the 5th nmos pass transistor 106) is kept owing to flowing through the electric current of the 5th nmos pass transistor 106，Therefore flow through the 3rd PMOS transistor 101 and flow through the electric current reduction of the 3rd nmos pass transistor 104，Because the 3rd PMOS transistor 101 and the 4th PMOS transistor 102 are symmetrical，Therefore the electric current flowing through the 4th PMOS transistor 102 also reduces.Therefore, the electric charge of the 5th PMOS transistor 103 grid can be pumped, so the voltage VG of the 5th PMOS transistor 103 grid reduces, and then the 5th PMOS transistor 103 grid and source voltage difference increase, so the electric current flowing through the 5th PMOS transistor 103 increases, the electric current wherein flowing through the second resistance 108 is identical with the electric current flowing through the 5th PMOS transistor 103.Increase owing to flowing through the electric current of the 5th PMOS transistor 103, so resistance R2 of the second resistance 108 and the product VF flowing through the second resistance 108 electric current also increase, during until VF with VREF is identical, VG no longer changes, and the electric current flowing through the 5th PMOS transistor 103 and the second resistance 108 no longer changes.
In like manner, when electric charge pump 110 is input to the grid voltage VREF of the 4th nmos pass transistor 105 less than the grid voltage VF of third transistor, VG raises, and flows through the electric current of the second resistance 108 and the electric current reduction of the 5th PMOS transistor 103, VF reduces, until VF with VREF is identical.
Thus, by the method for above-mentioned change VREF, thus it is possible to vary voltage regulator is input to the voltage VPPO of end drive circuit.Certainly the resistance ratio of the first resistance and the second resistance be can also change, or VREF and the resistance ratio of the first resistance and the second resistance changed, for how system of selection selects as required simultaneously.
What deserves to be explained is this utility model embodiment exemplary the structure representation of voltage regulator is become the structure shown in Fig. 2 b, but a kind of example of the structure of the voltage regulator shown in Fig. 2 b, the structure of voltage regulator is not limited to the structure one form shown in Fig. 2 b, can also is that other form, it is possible to realize the purpose of the different voltage of regulation fixed voltage output.
A kind of word line driving circuit that this utility model embodiment provides, on the basis of above-described embodiment, end drive circuit and voltage regulator are optimized, when using above-mentioned circuit that memory element is carried out read or write, reduce power consumption, save the time of address decoding circuitry discharge and recharge.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.It will be appreciated by those skilled in the art that this utility model is not limited to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute without departing from protection domain of the present utility model.Therefore, although this utility model being described in further detail by above example, but this utility model is not limited only to above example, in the case of conceiving without departing from this utility model, other Equivalent embodiments more can also be included, and scope of the present utility model is determined by scope of the appended claims.
Claims (7)
1. a word line driving circuit, it is characterised in that include voltage regulator, address decoding circuitry and end drive circuit；
The signal input part of described address decoding circuitry is connected with address bus；The power supply signal input of described address decoding circuitry is connected with outside power supply, the signal output part of address decoding circuitry is connected with the signal input part of end drive circuit, for when the power supply outside applying inputs fixed voltage, address signal is decoded, and exports control signal to drive described end drive circuit；
The input of described voltage regulator is connected with outside power supply, the outfan of described voltage regulator is connected with the power supply signal input of described end drive circuit, for the fixed voltage of input is adjusted, to change the voltage being applied to described end drive circuit；
The signal output part of described end drive circuit is connected with memory element, for driving the wordline of described memory element.
Word line driving circuit the most according to claim 1, it is characterised in that described end drive circuit includes the first PMOS transistor, the second PMOS transistor, the first nmos pass transistor and the second nmos pass transistor；
The grid of described first PMOS transistor is connected with the first signal output part of address decoding circuitry；The source electrode of described first PMOS transistor is connected with the outfan of described voltage regulator, and is connected with the substrate of described first PMOS transistor；The drain electrode of described first PMOS transistor is connected with the source electrode of the second PMOS transistor, and the substrate of described first PMOS transistor and the substrate of the second PMOS transistor connect；
The grid of described second PMOS transistor is connected with the secondary signal outfan of described address decoding circuitry；The drain electrode of described second PMOS transistor is connected with the drain electrode of described first nmos pass transistor, and is connected with wordline；
The grid of described first nmos pass transistor is connected with the secondary signal outfan of described address decoding circuitry；The source electrode of described first nmos pass transistor is connected with the substrate of described first nmos pass transistor, and ground connection；
The grid of described second nmos pass transistor is connected with the first signal output part of described address decoding circuitry；The drain electrode of described second nmos pass transistor is connected with wordline, and the source electrode of described second nmos pass transistor is connected with the substrate of described second nmos pass transistor, and ground connection.
Word line driving circuit the most according to claim 1, it is characterised in that the fixed voltage of voltage regulator input is more than the voltage of output.
Word line driving circuit the most according to claim 3, it is characterised in that the magnitude of voltage of voltage regulator output is respectively 0V, 5V and 7V.
Word line driving circuit the most according to claim 1, it is characterized in that, described voltage regulator includes the 3rd PMOS transistor, the 4th PMOS transistor, the 5th PMOS transistor, the 3rd nmos pass transistor, the 4th nmos pass transistor, the 5th nmos pass transistor, the first resistance and the second resistance；
The source electrode of the 3rd PMOS transistor is connected with outside power supply；The drain electrode of the 3rd PMOS transistor is connected with the drain electrode of described 3rd nmos pass transistor；The grid of described 3rd PMOS transistor is connected with the grid of described 4th PMOS transistor and the drain electrode of described 3rd PMOS crystal respectively；
The grid of described 3rd nmos pass transistor is connected with the input of described second resistance；The source electrode of described 3rd nmos pass transistor is connected with the drain electrode of described 5th nmos pass transistor；
The source ground of described 5th nmos pass transistor, the grid of described 5th nmos pass transistor is connected with outside bias supply；
The source electrode of described 4th PMOS transistor is connected with outside power supply, and the drain electrode of described 4th PMOS transistor is connected with the described drain electrode of the 4th nmos pass transistor and the grid of the 5th PMOS transistor respectively；
The source electrode of described 4th nmos pass transistor and the drain electrode of the 5th nmos pass transistor connect, and the grid of described 4th nmos pass transistor is connected with outside electric charge pump；
The source electrode of described 5th PMOS transistor is connected with outside power supply；The drain electrode of described 5th PMOS transistor power supply signal input with the input of described first resistance and described end drive circuit respectively is connected；
The outfan of described first resistance is connected with the input of described second resistance；The output head grounding of described second resistance.
Word line driving circuit the most according to claim 5, it is characterised in that described bias supply, for controlling the conducting of the 5th nmos pass transistor, and makes the electric current flowing through the 5th nmos pass transistor keep stable.
Word line driving circuit the most according to claim 5, it is characterized in that, described electric charge pump, for controlling the conducting of the 4th nmos pass transistor, and controls the electric current flowing through the 4th nmos pass transistor with the voltage difference between grid and the source electrode of control the 5th PMOS transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620330306.8U CN205541959U (en) | 2016-04-19 | 2016-04-19 | Word line drive circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620330306.8U CN205541959U (en) | 2016-04-19 | 2016-04-19 | Word line drive circuit |
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|---|---|
| CN205541959U true CN205541959U (en) | 2016-08-31 |
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|---|---|---|---|
| CN201620330306.8U Withdrawn - After Issue CN205541959U (en) | 2016-04-19 | 2016-04-19 | Word line drive circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945831A (en) * | 2016-10-12 | 2018-04-20 | 北京京存技术有限公司 | Reduce the circuit and nand flash memory of nand flash memory programming settling time |
-
2016
- 2016-04-19 CN CN201620330306.8U patent/CN205541959U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107945831A (en) * | 2016-10-12 | 2018-04-20 | 北京京存技术有限公司 | Reduce the circuit and nand flash memory of nand flash memory programming settling time |
| CN107945831B (en) * | 2016-10-12 | 2020-09-18 | 北京兆易创新科技股份有限公司 | Circuit for reducing programming setup time of NAND flash memory and NAND flash memory |
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