CN205486082U - Be applied to ware that sends in USB -PD communication - Google Patents
Be applied to ware that sends in USB -PD communication Download PDFInfo
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- CN205486082U CN205486082U CN201620133037.6U CN201620133037U CN205486082U CN 205486082 U CN205486082 U CN 205486082U CN 201620133037 U CN201620133037 U CN 201620133037U CN 205486082 U CN205486082 U CN 205486082U
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Abstract
The utility model relates to a do you be applied to USB send the ware in the PD communication, should send the ware and include: OTA circuit, amplifier, prime amplifier and control logic unit, wherein, the positive input terminal of OTA circuit and negative input end link to each other with the control logic unit, its output and the negative input end of control logic unit, the positive input terminal of amplifier to and electric capacity C1's one end links to each other, electric capacity C1's other end ground connection, amplifier positive input terminal connects the output of OTA circuit to and electric capacity C1's one end is continuous, and its negative input end and self output connection are together, prime amplifier positive input terminal ground connection, and the output of OTA circuit, its output connection control logic unit's one end is connected to the negative input end, the output of prime amplifier is connected to the first end of control logic unit, and the input of OTA circuit is connected to the second end, and the output of OTA circuit is connected to the third end, and reference voltage is connected to the fourth end, the OTA circuit passes through the control logic unit for the work of OTA circuit is at amplifier and comparator state.
Description
Technical Field
The utility model belongs to the technical field of the USB circuit design and specifically relates to a be applied to sending ware in USB-PD communication.
Background
Currently, various adapters have different standards and are very complicated to apply. The USB-PD is a communication protocol for carrying out power capability negotiation for the rapid charging of the electronic equipment with the USB Type-C interface, and BMC coding is adopted through a CC line in communication. The USB-PD, redesigns for power transmission, brings the power output option that provides more bold for the user, and its general communication process is as follows:
1. after the adapter and the electrical appliance are connected and established, the adapter broadcasts through the CC line to tell the other party of the connection what kinds of voltage and corresponding current the adapter can provide.
2. After the power supply capability of the adapter is known, the electric appliance selects a power supply mode which is most suitable for the electric appliance, and sends a request data packet to the adapter.
3. The adapter sends an 'accept' command after evaluating the capability of the adapter according to the selection of the electrical appliance.
4. The adapter performs internal voltage conversion and sends a "power ready" packet to the appliance.
5. The adapter applies the negotiated new supply voltage to the VBUS.
During the communication, according to the USB-PD protocol, the transmitted signal quality has clear requirements, a high level voltage range (1.04-1.2) V is output, a low level voltage range (0-75) mv is output, the rising edge and falling edge time is at least 300ns, and the maximum rising edge and falling edge time cannot violate the eye diagram rule.
SUMMERY OF THE UTILITY MODEL
The utility model provides a purpose of this application, the USB Type-C interface is different for solving current various adapter standards, uses very loaded down with trivial details problem, and the utility model provides a be applied to the circuit architecture of sending in the USB Type-C PD communication.
In order to achieve the above object, the present application provides a transmitter applied in USB-PD communication, the transmitter including: a transconductance Operational amplifier (OTA) circuit, an amplifier, a preamplifier and a control logic unit; the positive input end and the negative input end of the OTA circuit are connected with the control logic unit, the output of the OTA circuit is connected with the negative input end of the control logic unit, the positive input end of the amplifier and one end of a capacitor C1, and the other end of the capacitor C1 is grounded; the positive input end of the amplifier is connected with the output end of the OTA circuit and one end of a capacitor C1, and the negative input end of the amplifier is connected with the output end of the amplifier; the positive input end of the preamplifier is grounded, the negative input end of the preamplifier is connected with the output end of the OTA circuit, and the output of the preamplifier is connected with one end of the control logic unit; the first end of the control logic unit is connected with the output end of the preamplifier, the second end of the control logic unit is connected with the input end of the OTA circuit, the third end of the control logic unit is connected with the output end of the OTA circuit, and the fourth end of the control logic unit is connected with the reference voltage; the OTA circuit enables the OTA circuit to work in the states of the amplifier and the comparator through the control logic unit, so that the output waveform of the OTA circuit can meet the time requirements of high level and low level, rising edge and falling edge in the USB-PD communication protocol.
As an improvement of the embodiment of the present application, the control logic unit includes: controlling switches S1, S2, S3, S4, wherein one end of S1 is connected to the positive output terminal of the preamplifier, the other end of S1 is connected to the positive input terminal of the OTA circuit, and one end of S4; one end of the S2 is connected with the negative output of the preamplifier, and the other end of the S2 is connected with the negative input end of the OTA circuit; one end of the S3 is connected with the negative input end of the OTA circuit, and the other end of the S3 is connected with the output end of the OTA circuit; one end of S4 is connected with the reference voltage, the other end of S4 is connected with the positive input end of the OTA circuit, and the other end of S1; when the control logic unit transmits BMC code system signals '1' and '0', the OTA circuit is used as an operational amplifier or a comparator by opening different control switches.
As an improvement of the embodiment of the application, the OTA circuit adopts an amplifier with a folded cascode structure.
As an improvement of the embodiment of the application, the amplifier adopts an AB class amplifier.
As an improvement of the embodiment of the application, the amplifier is connected into a unit gain negative feedback form, so that the signal of the positive input end of the amplifier can be tracked, and the operational amplifier of the amplifier can ensure smaller quiescent current and larger driving capability.
As an improvement of the embodiment of the present application, the preamplifier is in a fully differential output form to ensure that the OTA circuit has enough voltage difference to input when outputting "0".
As an improvement of the embodiment of the present application, the preamplifier is in a fully differential output form, and includes a current source I1, a first PMOS transistor P1, a second PMOS transistor P2, a resistor R1, and a resistor R2; one end of the current source I1 is connected with a power supply VDD, and the other end is connected with the sources of P1 and P2; the drain terminals of the P1 and the P2 are respectively connected with one ends of the resistor R1 and the resistor R2, and the grid terminals of the P1 and the P2 are respectively connected with two input terminals; the other ends of the resistor R1 and the resistor R2 are connected with a reference ground; the output end of the S-shaped switch is connected with one ends of S1 and S2.
Drawings
The present invention will be further explained with reference to the drawings and examples.
Fig. 1 is a schematic diagram of a transmitter circuit according to an embodiment of the present invention;
FIG. 2 is an OTA circuit schematic of the transmitter of FIG. 1;
FIG. 3 is a schematic diagram of a preamplifier circuit of the transmitter of FIG. 1;
fig. 4 is a signal control schematic of the transmitter of fig. 1.
Detailed Description
The technical solution of the present invention is further described in detail by the accompanying drawings and examples.
Fig. 1 is a schematic diagram of a transmitter circuit according to an embodiment of the present invention. As shown in fig. 1, the transmitter includes: OTA circuit 001, amplifier 002, preamplifier 003 and control logic 004.
The positive input end and the negative input end of the OTA circuit 001 are connected with the control logic unit 004, the output of the OTA circuit is connected with the negative input end of the control logic unit 004, the positive input end of the amplifier 002 and one end of the capacitor C1, and the other end of the capacitor C1 is grounded; the positive input end of the amplifier 002 is connected with the output end of the OTA circuit 001, and one end of the capacitor C1, and the negative input end thereof is connected with the output of the amplifier itself; the preamplifier 003 positive input is connected to ground and the negative input is connected to the output of the OTA circuit 001, the output of which is connected to one end of the control logic 004. The first end of the control logic unit 004 is connected with the output end of the preamplifier 003, the second end is connected with the input end of the OTA circuit 001, the third end is connected with the output end of the OTA circuit 001, and the fourth end is connected with the reference voltage VREF. The OTA circuit 001 operates with the amplifier and comparator states through the control logic 004 so that its output waveform can meet the high and low levels, and the timing requirements for the rising and falling edges in the USB-PD communication protocol.
The OTA circuit 001 adopts an amplifier (as shown in fig. 2) with a folded cascode structure, and the amplifier 002 is connected to a unity gain negative feedback form, so that the signal at the positive input terminal of the amplifier 002 can be tracked, and the amplifier 002 operational amplifier can ensure a small quiescent current and a large driving capability.
The amplifier 002 is a class AB amplifier, the positive input terminal of which is connected to the output of the OTA circuit 001, the negative input terminal of which is connected to its own output, and the whole class AB amplifier is connected to a unity gain negative feedback form.
The preamplifier 003 is in a fully differential output form (as shown in fig. 3), and includes a current source I1, a first PMOS transistor P1, a second PMOS transistor P2, a resistor R1, and a resistor R2; one end of the current source I1 is connected with a power supply VDD, and the other end is connected with the sources of P1 and P2; the drain terminals of the P1 and the P2 are respectively connected with one ends of the resistor R1 and the resistor R2, and the grid terminals of the P1 and the P2 are respectively connected with two input terminals; the other ends of the resistor R1 and the resistor R2 are connected with a reference ground; the output end of the S-shaped switch is connected with one ends of S1 and S2. The preamplifier 003 is a fully differential output to ensure that the OTA circuit 001 has sufficient voltage differential to the input when outputting a "0".
The control logic unit 004 includes: controlling switches S1, S2, S3, S4, wherein one end of S1 is connected to the positive output terminal of the preamplifier 003, the other end of S1 is connected to the positive input terminal of the OTA circuit 001, and one end of S4; one end of the S2 is connected with the negative output of the preamplifier 003, and the other end of the S2 is connected with the negative input end of the OTA circuit 001; one end of the S3 is connected with the negative input end of the OTA circuit 001, and the other end of the S3 is connected with the output end of the OTA circuit 001; one end of the S4 is connected with the reference voltage VREF, and the other end of the S4 is connected with the positive input end of the OTA circuit 001 and the other end of the S1; when the control logic unit 004 transmits the BMC code system signals "1" and "0", the OTA circuit 001 is used as an operational amplifier or a comparator by turning on different control switches.
Fig. 4 is a signal control schematic of the transmitter of fig. 1. As shown in fig. 4, in conjunction with signal control, the transmitter operates as follows:
when the BMC code is '1', the control signals of the switches S3 and S4 are '1', the switches S3 and S4 are turned on, the control signals of the switches S1 and S2 are '0', and the switches S1 and S2 are turned off. At this time, the positive input terminal of the OTA circuit 001 is the reference voltage (VREF is the intermediate value between VHMAX and VHMIN required in the protocol), and the negative input terminal is connected with the output terminal, which is equivalent to that the OTA circuit 001 is connected to form a unity gain negative feedback amplifier. Because the output of the OTA circuit 001 in the previous state is "0", the OTA circuit 001 is in the large signal state, as shown in fig. 2, at this time, the tail current I1 flows through the P3 completely, according to the mirror image principle, the P4/P5 tube current increases I1, which is equivalent to the current with the size of I1 to charge the capacitor C1, when the capacitor is charged to be closer to VREF (reference voltage), the OTA circuit 001 enters the amplifier state, and in the small signal state, the proper phase margin condition is satisfied, the output of the OTA circuit 001 does not overshoot, and then the VREF voltage is finally reached. By properly sizing the I1 current, the C1 capacitance, and the input pair transistors P2 and P3, the rise time, and ultimately the voltage, can be made to meet the protocol requirements.
When the BMC code is "0", the control signals of the switches S3 and S4 are "0", the switches S3 and S4 are off, the control signals of the switches S1 and S2 are "1", the switches S1 and S2 are on, and the preamplifier 003 is connected to the control loop. As shown in fig. 4, when VINP input is ground and VINN is OTA circuit 001 output, and the former state is VREF (reference voltage), the gain of the preamplifier 003 can be set properly so that the output positive terminal of the preamplifier 003 is higher voltage and the output negative terminal is lower voltage, which are respectively applied to the negative input terminal and the positive input terminal of the OTA circuit 001 through the control switches S2 and S1. For the OTA circuit 001, such a large voltage difference input causes the OTA circuit 001 to be in a large signal operation state, where the I1 current flows completely through the P2, which causes the current in the P4/P5 mirror tube to disappear, and the current corresponding to I1 draws current from the C1. In the whole process that the BMC code is '0', the OTA circuit 001 is always in the working state of the comparator due to the action of the preamplifier 003, the input of the positive end of the OTA circuit 001 is always larger than the input of the negative end, finally, the output of the OTA circuit 001 meets the requirement of outputting (0-75) mv voltage in a protocol, the falling edge time is also determined by the size sum of I1 and C1, and the falling edge time can meet the requirement through reasonable configuration.
To this end, the core of the entire transmitter is described, and the communication between the consumer and the adapter is carried out by a CABLE, which is required by the industry according to the protocol, and whose CABLE MODEL (CABLE mode) is shown in fig. 1, whose capacitance is still large, for which purpose a BUFFER stage is added after the OTA circuit 001, and the amplifier 002 is connected in the form of a unity gain negative feedback, which follows the output of the OTA circuit 001, so that the signal meeting the protocol requirements is transmitted.
The above-mentioned embodiments, further detailed description of the objects, technical solutions and advantages of the present invention, it should be understood that the above description is only the embodiments of the present invention, and is not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (7)
1. A transmitter for use in USB-PD communication, comprising: an OTA circuit (001), an amplifier (002), a preamplifier (003) and a control logic unit (004); wherein,
the positive input end and the negative input end of the OTA circuit (001) are connected with the control logic unit (004), the output of the OTA circuit is connected with the second end of the control logic unit (004), the positive input end of the amplifier (002) and one end of a capacitor C1, and the other end of the capacitor C1 is grounded;
the positive input end of the amplifier (002) is connected with the output end of the OTA circuit (001) and one end of a capacitor C1, and the negative input end of the amplifier is connected with the output end of the amplifier;
the positive input end of the preamplifier (003) is grounded, the negative input end of the preamplifier is connected with the output end of the OTA circuit (001), and the output of the preamplifier is connected with the first end of the control logic unit (004);
the first end of the control logic unit (004) is connected with the output end of the preamplifier (003), the second end of the control logic unit is connected with the input end of the OTA circuit (001), the third end of the control logic unit is connected with the output end of the OTA circuit (001), and the fourth end of the control logic unit is connected with a reference voltage VREF;
the OTA circuit (001) is enabled by the control logic unit (004) to operate the OTA circuit (001) in amplifier and comparator states, enabling its output waveform to meet the high and low levels, and the timing requirements of rising and falling edges in the USB-PD communication protocol.
2. Transmitter according to claim 1, characterized in that said control logic unit (004) comprises: a control switch S1, a control switch S2, a control switch S3 and a control switch S4, wherein one end of the control switch S1 is connected with the positive output end of the preamplifier (003), the other end of the control switch S1 is connected with the positive input end of the OTA circuit (001), and one end of the control switch S4; one end of a control switch S2 is connected with the negative output end of the preamplifier (003), and the other end of S2 is connected with the negative input end of the OTA circuit (001); one end of the control switch S3 is connected with the negative input end of the OTA circuit (001), and the other end of the control switch S3 is connected with the output end of the OTA circuit (001); one end of a control switch S4 is connected with a reference voltage VREF, and the other end of the control switch S4 is connected with the positive input end of the OTA circuit (001) and the other end of the control switch S1; and when the control logic unit (004) transmits the BMC code system signals '1' and '0', the OTA circuit (001) is used as an operational amplifier or a comparator by opening different control switches.
3. Transmitter according to claim 1, characterized in that the OTA circuit (001) employs an amplifier of folded cascode structure.
4. Transmitter according to claim 1, characterized in that the amplifier (002) is a class AB amplifier.
5. A transmitter as claimed in claim 1 or 2, characterised in that the amplifier (002) is connected in the form of unity gain negative feedback, so that the signal at the positive input of the amplifier (002) can be tracked, while the operational amplifier (002) can guarantee a small quiescent current, a large driving capability.
6. The transmitter of claim 1, wherein the preamplifier (003) is in the form of a fully differential output to ensure that the OTA circuit (001) has sufficient voltage differential to the input when outputting a "0".
7. The transmitter of claim 2, wherein the preamplifier (003) is in the form of a fully differential output comprising a current source I1, a first PMOS transistor P1, a second PMOS transistor P2, a resistor R1, and a resistor R2; one end of the current source I1 is connected with a power supply VDD, and the other end is connected with the sources of P1 and P2; the drain terminals of the P1 and the P2 are respectively connected with one ends of the resistor R1 and the resistor R2, and the grid terminals of the P1 and the P2 are respectively connected with two input terminals; the other ends of the resistor R1 and the resistor R2 are connected with a reference ground; the output end of the S-shaped switch is connected with one ends of S1 and S2.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620133037.6U CN205486082U (en) | 2016-02-22 | 2016-02-22 | Be applied to ware that sends in USB -PD communication |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620133037.6U CN205486082U (en) | 2016-02-22 | 2016-02-22 | Be applied to ware that sends in USB -PD communication |
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| CN205486082U true CN205486082U (en) | 2016-08-17 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI663819B (en) * | 2017-04-21 | 2019-06-21 | 通嘉科技股份有限公司 | Power delivery controller applied to a power converter and operation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI663819B (en) * | 2017-04-21 | 2019-06-21 | 通嘉科技股份有限公司 | Power delivery controller applied to a power converter and operation method thereof |
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Effective date of registration: 20210428 Address after: No.1, floor 4, building 10, No.303, group 3, liangfengding village, Zhengxing Town, Tianfu New District, Chengdu, Sichuan 610000 Patentee after: Sichuan Yichong Technology Co.,Ltd. Address before: 300457, Tianjin Binhai New Area, Tianjin Development Zone, No. 19 West Ring Road, TEDA service outsourcing Garden No. 2701-1 building, room 2 Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |