CN205485900U - USB line power supply system - Google Patents
USB line power supply system Download PDFInfo
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- CN205485900U CN205485900U CN201620029795.3U CN201620029795U CN205485900U CN 205485900 U CN205485900 U CN 205485900U CN 201620029795 U CN201620029795 U CN 201620029795U CN 205485900 U CN205485900 U CN 205485900U
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Abstract
The utility model provides a USB line power supply system, this electrical power generating system includes the USB interface, piece external resistance array and chip, the chip includes the interior gating switch array of piece, low dropout regulator in voltage detector and the first piece in the piece, low dropout regulator in the second piece, the USB interface is connected to gating switch array in the piece through piece external resistance array, switch in the piece in the gating switch array is connected to the interior voltage detector's of piece input, voltage detector's output is connected to the logic circuit of the interior gating switch array of piece in the piece, switch in the piece in the gating switch array is connected to the interior low dropout regulator's of first piece input. The utility model discloses need not extra LDO chip or power inductance, also do not need complicated inside circuit design simultaneously, only can realize reducing chip calorific capacity through a plurality of resistance to the cost is reduced.
Description
Technical field
This utility model relates to field of power systems, especially relates to a kind of power-supply system reducing USB line power supply chip caloric value.
Background technology
Along with the development of integrated circuit technique, raising of the expansion of chip-scale, the lifting of speed and functional complexity etc. is all more and more higher to the power consumption requirements of chip self.In addition the chip after encapsulation has thermal resistance, the power increase that i.e. chip consumes, and further increases the dissipated power of chip.If case chip internal medium is the biggest to the thermal potential difference of case chip external environment condition, and under conditions of ambient temperature is identical, illustrate that the temperature of chip itself is the highest.Owing to the maximum operating temperature of chip is fixing, so reducing power consumption to be accomplished by reducing the dissipated power of chip internal.So in chip power system designs, needing the maximum considering to reduce chip internal dissipation power consumption as far as possible.
See Fig. 1, Fig. 1 is the circuit structure schematic diagram of generic USB line power supply plan, on the pcb board being provided with USB chip, usb 10 electrically connects with chip 13, chip 13 electrically connects with peripheral hardware 14, and the USB interface of the outside that the usb 10 on pcb board is matched with it by USB line 12 electrically connects with external power source, in USB power source system, the running voltage of general chip I/O port (input/output port) and peripheral hardware 14 is 3.3 volts, and chip 13 inherent logic running voltage is 1.2 volts or 1.8 volts.
Traditional solution reducing chip power-consumption mainly has and following has three kinds:
Assuming that chip I/O port and peripheral hardware maximum operating currenbt are I33, logic maximum operating currenbt is I12, then total maximum operating currenbt of chip is I33 and I12 sum.USB line supply input voltage max is 5.25 volts, and the running voltage of chip I/O port and peripheral hardware is 3.3 volts, and logic working voltage is 1.2 volts.
See Fig. 2, Fig. 2 is existing one by internal LDO(low pressure difference linear voltage regulator) the circuit structure schematic diagram of power supply plan, wherein USB interface 20 electrically connects with the public input of low pressure difference linear voltage regulator in two sheets being connected in parallel on chip 23, wherein in first, the outfan of low pressure difference linear voltage regulator 25 electrically connects with peripheral hardware 24, ground connection after the output termination capacitor of second interior low pressure difference linear voltage regulator 26.In this scheme, chip 23 dissipated power is P=5.25V × (I33+I12) with the relation of current power dissipation.
See Fig. 3, Fig. 3 is the circuit structure schematic diagram of existing DC-DC BUCK step-down conversion circuit power supply plan, wherein USB interface 30 electrically connects with the public input of two step-down conversion circuits being connected in parallel on chip 33, first step-down conversion circuit 39 is electrically connected with peripheral hardware 34 by inductance L1, in this scheme, chip 33 dissipated power and current power dissipation relation are P=K × (3.3V × I33+1.2V × I12), and wherein K is the efficiency of internal DC-DC Buck step-down conversion circuit.Utilize high pressure to arrive the extracurrent conversion efficiency of low pressure, effectively reduce input current power consumption, thus reduce chip own power and dissipate, but Electro Magnetic Compatibility and internal circuit design difficulty is big and cost is high.
See Fig. 4, Fig. 4 is the circuit structure schematic diagram of existing outside LDO power supply plan, the public input of the off-chip low pressure difference linear voltage regulator that two outside wherein USB interface 40 is with chip 43 are connected in parallel electrically connects, the outfan of the outer low pressure difference linear voltage regulator 47 of first electrically connects with chip 43 and peripheral hardware 44 respectively, and the outfan of the second off-chip low pressure difference linear voltage regulator 48 electrically connects with chip 43.In this scheme, chip 43 dissipated power and current power dissipation relation are P=3.3V × I33+1.2V × I12.The method uses at chip 43 external low-voltage difference linear constant voltage regulator, low pressure difference linear voltage regulator outside Li Yonging undertakes 5 volts to 3.3 volts and the power consumption of 5 volts to 1.2 volts and heating, thus reduce chip own power and dissipate, but the low pressure difference linear voltage regulator outside Shi Yonging is powered needs extra outer low pressure difference linear constant voltage regulator, cause circuit cost high.
Utility model content
Main purpose of the present utility model is to provide that a kind of production cost is low and the USB line powersupply system of working stability.
nullIn order to realize above-mentioned main purpose，The power-supply system that this utility model provides includes USB interface、Off chip resistor array and chip，Its chips includes sheet internal gating switch arrays、Low pressure difference linear voltage regulator in voltage detector and first in sheet、Second interior low pressure difference linear voltage regulator，USB interface is connected to sheet internal gating switch arrays by off chip resistor array，Sheet internal gating switch arrays include that at least one switchs，Switch is connected to the input of voltage detector in sheet，In sheet, the outfan of voltage detector is connected to the logic circuit of sheet internal gating switch arrays，Switch in sheet internal gating switch arrays is connected to the input of low pressure difference linear voltage regulator in first，Connect between outfan and the input of second interior low pressure difference linear voltage regulator of low pressure difference linear voltage regulator in first and have the resistance being positioned at outside chip.
nullFrom such scheme，External power source inputs USB standard voltage by USB interface，Power-supply system monitors the voltage of the node being connected between off chip resistor array and sheet internal gating switch arrays by voltage detector in sheet，Switch in dynamic gating sheet internal gating switch arrays，Thus gate the different resistance branch in off chip resistor array，Realize above-mentioned node to float near a fixing relatively low voltage range，Then in first low pressure difference linear voltage regulator again by the voltage needed for the fixing relatively low voltage voltage stabilizing of node to chip I/O port and peripheral hardware，Simultaneously，The voltage difference falling therebetween by the resistance consumption being positioned at outside chip connected between outfan and the input of second interior low pressure difference linear voltage regulator of low pressure difference linear voltage regulator in first，So that originally being dissipated by non-essential resistance by the power of internal dissipation，Low pressure difference linear voltage regulator that this power-supply system need not be extra or relatively costly power inductance，Reduce the cost of integral product.
Further scheme is to comprise at least one branch road in off chip resistor array.
Further scheme is, comprises at least one resistance in every branch road of off chip resistor array.
Further scheme is, the switch that every branch road of off chip resistor array is respectively connecting in sheet internal gating switch arrays.
As can be seen here, the mode of choosing of the different resistance branch in off chip resistor array is determined by chip I/O and peripheral hardware maximum operating currenbt, logic maximum operating currenbt, external power source maximum supply voltage and minimum internal resistance thereof, external power source minimum supply voltage, the expection voltage of node being connected between off chip resistor array and sheet internal gating switch arrays and required voltage stabilizing resolution, and switchs, by the different of gating sheet internal gating switch arrays, the different resistance branch realizing choosing in off chip resistor array.
Further scheme is, in sheet, voltage detector includes comparator, phase inverter, level translator and the first adjustable resistance, the second adjustable resistance, comparator output terminal electrically connects with inverter input, inverter output electrically connects with level translator input, being connected in series between first adjustable resistance and the second adjustable resistance, the outfan of level translator is connected with the logic circuit of sheet internal gating switch arrays.
Further scheme is, comparator output terminal is connected between the first adjustable resistance and the second adjustable resistance by a NMOS tube.
Further scheme is, at least two of connecting between the first adjustable resistance and power end resistance.
As can be seen here, the logic circuit of sheet internal gating switch carrys out the switch during dynamic tab internal gating switchs by the output of the detection level translator in voltage detector in sheet.If switch in sheet internal gating switch arrays from top to bottom is SW1a, SW1b and SW1c, assume that its control signal is S0, S1, S2, S0 when powering on, S1, S2 default value is 000, chip acquiescence low-power consumption mode, first it is adjusted to 001, the most progressively each module of opening chip, if logic LS of level translator is output as 1, i.e. high level, then continue on, if logic LS of level translator is output as 0, i.e. low level, then the control signal controlling sheet internal gating switch is increased to 010, recirculation above-mentioned steps, until required module all has turned on, hereafter dynamic shaping modes is entered back into.
Accompanying drawing explanation
Fig. 1 is existing generic USB power supply plan circuit structure schematic diagram.
Fig. 2 is existing internal LDO power supply plan circuit structure schematic diagram.
Fig. 3 is existing DC-DC BUCK step-down conversion circuit power supply plan circuit structure schematic diagram.
Fig. 4 is existing chip external LDO power supply plan circuit structure schematic diagram.
Fig. 5 is the circuit structure schematic diagram of this utility model USB line powersupply system embodiment.
Fig. 6 be this utility model USB line powersupply system embodiment sheet in voltage detector circuit structure principle chart.
Below in conjunction with drawings and Examples, the utility model is described in further detail.
Detailed description of the invention
See the circuit structure schematic diagram that Fig. 5, Fig. 5 are this utility model embodiment.Power-supply system of the present utility model includes in off chip resistor array 100, sheet internal gating switch arrays 200, sheet 400, second interior low pressure difference linear voltage regulator 500 of low pressure difference linear voltage regulator, sheet internal resistance R3 and off chip resistor R2 in voltage detector 300, first.Wherein, usb 1 electrically connects with off chip resistor array 100, off chip resistor array 100 includes resistance R1a, resistance R1b, resistance R1c and resistance R1d, sheet internal gating switch arrays 200 include switching SW1a, switch SW1b and switch SW1c from top to bottom, resistance R1d is connected to switch first end of SW1a, resistance R1a is connected in parallel on resistance R1d two ends and is connected to switch first end of SW1b after connecting with resistance R1c, resistance R1b is connected to switch first end of SW1c after being connected in parallel on resistance R1c, sheet internal resistance R3 is connected in parallel between switch SW1c two ends.As shown in Figure 5, between resistance R1a, resistance R1b and sheet internal resistance R3 it is the relation connected.Second end of switch SW1a in sheet internal gating switch arrays 200, switch SW1b and switch SW1c is connected to the input of low pressure difference linear voltage regulator 400 in the input of voltage detector 300 in sheet and first respectively, wherein, the logic circuit of the outfan contact pin internal gating switch arrays 200 of voltage detector 300 in sheet, in first, the outfan of low pressure difference linear voltage regulator 400 is connected to the input of second interior low pressure difference linear voltage regulator 500 by off chip resistor R2, and in first, the outfan of low pressure difference linear voltage regulator 400 is connected to peripheral hardware 600.
Assume that external power source input voltage VUSB is in the range of 4.75 volts to 5.25 volts of USB standard voltage range.There is certain excursion due to the relation of wire rod and length in USB line, here it is assumed that between being 0 to 3 ohm.In first, the output voltage V1 of low pressure difference linear voltage regulator 400 is 3.3 volts, the output voltage V2 of second interior low pressure difference linear voltage regulator 500 is 1.2 volts, assume that chip I/O port maximum operating currenbt I33A is 50 milliamperes, peripheral hardware 600 maximum operating currenbt I33B is 100 milliamperes, then chip I/O port is 150 milliamperes plus the maximum operating currenbt I33 of peripheral hardware 600；Assume that logic maximum operating currenbt I12 is 100 milliamperes.
It is assumed above that on the premise of, use 3 chip I/O ports and four resistance, the voltage stabilizing resolution of 0.125 volt can be realized, the resistance value making resistance R1a, resistance R1b, resistance R1c and resistance R1d is respectively 1.55 ohm, 5.45 ohm, 4.45 ohm and 5 ohm, and sheet internal resistance R3 is 100 ohm.Switch from top to bottom is switch SW1a, switch SW1a and switch SW1c, assume that multiple switch SW1a, SW1a and SW1c control signal is respectively S0, S1, S2, the signal then switching SW1a, switch SW1b and switch SW1c can be as follows with permutation and combination: 000,001,010,011,100,101,110,111, and the equivalent resistance that thus can be calculated multiple electricity is respectively as follows: 100 ohm, 7 ohm, 6 ohm, 5 ohm, 4 ohm, 2.92 ohm, 2.73 ohm and 2.22 ohm.
The voltage of the node N1 being connected between off chip resistor array 100 with sheet internal gating switch arrays 200 is monitored by voltage detector in sheet 300, dynamically gating sheet internal gating switch arrays 200, thus gate the different resistance branch of off chip resistor array 100, realize node N1 and fix relatively low voltage at one, fluctuate near about 3.5 volts.Voltage stabilizing resolution is utilized to do the sluggishness judged, assume that voltage stabilizing resolution is 0.1 volt, if voltage detector 300 detects that the voltage of node N1 is more than 3.6 volts in sheet, by controlling the logic circuit of sheet internal gating switch arrays 200, strengthen the equivalent resistance of off chip resistor array 100, in like manner, if voltage detector 300 detects the voltage of node N1 less than 3.4 volts in sheet, by controlling the logic circuit of sheet internal gating switch arrays 200, reduce the equivalent resistance of off chip resistor array 100, thus the voltage of node N1 is decreased or increased.
In first, low pressure difference linear voltage regulator 400 is again by 3.3 volts of voltages needed for the voltage voltage stabilizing of about 3.5 volts to chip I/O port and peripheral hardware 600, the mode of choosing of off chip resistor array 100 by chip I/O port and peripheral hardware 600 maximum operating currenbt I33, logic maximum operating currenbt I12, external power source maximum supply voltage and minimum internal resistance thereof, external power source minimum supply voltage, is connected between off chip resistor array 100 and sheet internal gating switch arrays 200 node N1 expect that voltage and required voltage stabilizing resolution determine.
In the case of, USB line impedance minimum the highest at outside power input voltage VUSB, during peak point current, the output voltage of node N1 is 3.5 volts.In the case of, USB line impedance maximum minimum at outside power input voltage VUSB, during peak point current, node N1 output voltage is 3.445 volts.
The circuit of output voltage V2 for output voltage V1 to second interior low pressure difference linear voltage regulator 500 of low pressure difference linear voltage regulator in first 400, off chip resistor R2 is the major part of the pressure reduction of the output voltage V2 of output voltage V1 to second interior low pressure difference linear voltage regulator 500 of low pressure difference linear voltage regulator 400 in consuming first, makes this part originally will be dissipated by non-essential resistance by the power of internal dissipation.The value of off chip resistor R2 is (V1-V2-Vod2)/I12, and wherein Vod2 is the seamless remaining keeping for second interior low pressure difference linear voltage regulator 500.According to aforementioned setting, and assume that Vod2 is 0.2 volt, then the value of resistance R2 is 19 ohm.
In conventional power source scheme, chip 3 maximum dissipation power consumption is 5.25V × 0.25A-3.3V × 0.1A=0.9825W.Wherein in this scheme, chip 3 maximum dissipation power consumption 3.625V × 0.25V-3.3V × 0.1A-19 × 0.1A × 0.1A=0.906W-0.33W-0.19W=0.386W.Compared to conventional power source scheme, scheme of the present utility model chip maximum dissipation lower power consumption to the 39% of original value.
In like manner, the resistance value if chip current power consumption profile is different, in corresponding tab external resistance array 100.If needing thinner voltage stabilizing resolution, then increase the number of chip I/O port thus build thinner regulation stepping.
See Fig. 6, Fig. 6 is voltage detector circuit structure principle chart in this utility model embodiment sheet, and in sheet, the circuit of voltage detector includes resistance R7, resistance R4, adjustable resistance R5, adjustable resistance R6, electric capacity C1, NMOS tube M1, comparator 301, phase inverter 302 and level translator 303.Wherein resistance R7, resistance R4, it is sequentially connected in series between first adjustable resistance R5 and the second adjustable resistance R6, one end of resistance R7 is connected with power supply, one end ground connection of the second adjustable resistance R6, the electrode input end of comparator 301 meets voltage reference Vref, the outfan of comparator 301 is connected to the input of phase inverter 302, the grid of NMOS tube M1 is connected between the outfan of comparator 301 and the input of phase inverter 302, the drain electrode of NMOS tube M1 is connected between the first adjustable resistance R5 and the second adjustable resistance R6, the source ground of NMOS tube M1, the input of the output termination level translator 303 of phase inverter 302, the outfan of level translator 303 connects the logic circuit of sheet internal gating switch arrays 200.
If switch in sheet internal gating switch arrays 200 from top to bottom is SW1a, SW1b and SW1c, assume that its control signal is S0, S1, S2, S0 when powering on, S1, S2 default value is 000, chip 3 gives tacit consent to low-power consumption mode, first control signal is adjusted such that S0, S1, S2 is 001, the most progressively each module of opening chip 3, if the logic circuit LS of level translator 303 is output as 1, i.e. high level, then continue on, if the logic circuit LS of level translator 303 is output as 0, i.e. low level, then the control signal controlling gating switch is increased to 010, recirculation above-mentioned steps, until required module all has turned on, hereafter dynamic shaping modes is entered back into.
In foregoing circuit, the effect of electric capacity C1 is to provide filtering, prevents in first the ripple on the connection node N2 between low pressure difference linear voltage regulator 400 outfan and off chip resistor R2 to cause and switchs switching action the most frequently.The effect of the first adjustable resistance R5 is to cooperate with the adjustable retarding window that NMOS tube M1 provides the most controlled.The effect of resistance R4 is to provide adjustable mid-point voltage.Voltage reference Vref is from Bandgap accurately (band-gap reference) circuit of chip internal.Logic circuit carrys out the switch in dynamic tab internal gating switch arrays 200 by the output of detection level translator 303.Power on control signal S0 of time control film-making internal gating switch arrays 200 breaker in middle, S1, S2 default value is 000, and chip 3 gives tacit consent to low-power consumption mode.First it is adjusted to 001, the more progressively each module of opening chip 3, if LS is output as 1, continues on, if LS is output as 0, increase to 010.It is further continued for this step, until required module all has turned on, hereafter enters back into dynamic shaping modes.
Certainly, above-described embodiment is only preferred scheme of the present utility model, can also have more change, such as, the setting of the different resistance branch of off chip resistor array during actual application；Or, other circuit that can realize voltage detector function in sheet or instrument；Or, the change of voltage stabilizing resolution, such change also can realize the purpose of this utility model.
Finally it is emphasized that this utility model is not limited to above-mentioned embodiment, as off chip resistor array, sheet internal gating switch to change with the in-built change of voltage detector in sheet etc. and also should be included in this utility model scope of the claims.
Claims (7)
1.USB line powersupply system, including USB interface, off chip resistor array and chip；
It is characterized in that:
Described chip includes in sheet internal gating switch arrays, sheet low pressure difference linear voltage regulator, second interior low pressure difference linear voltage regulator in voltage detector and first；
Described USB interface is connected to described internal gating switch arrays by described off chip resistor array, described internal gating switch arrays include that at least one switchs, described switch is connected to the input of described interior voltage detector, the outfan of described interior voltage detector is connected to the logic circuit of described internal gating switch arrays, and the described switch in described internal gating switch arrays is connected to the input of low pressure difference linear voltage regulator in described first；
It is connected between the outfan of low pressure difference linear voltage regulator and the input of described second interior low pressure difference linear voltage regulator in described first and has the resistance being positioned at outside described chip.
USB line powersupply system the most according to claim 1, it is characterised in that:
Described off chip resistor array comprises at least one branch road.
USB line powersupply system the most according to claim 2, it is characterised in that:
Every described branch road of described off chip resistor array comprises at least one resistance.
USB line powersupply system the most according to claim 2, it is characterised in that:
Every described branch road of described off chip resistor array is respectively connecting to a described switch in described internal gating switch arrays.
5. according to the USB line powersupply system described in any one of Claims 1-4, it is characterised in that:
Described interior voltage detector includes comparator, phase inverter, level translator and the first adjustable resistance, the second adjustable resistance, the outfan of described comparator electrically connects with the input of described phase inverter, the outfan of described phase inverter electrically connects with the input of described level translator, being connected in series between described first adjustable resistance and described second adjustable resistance, the outfan of described level translator is connected with the described logic circuit of described internal gating switch arrays.
USB line powersupply system the most according to claim 5, it is characterised in that:
Described comparator output terminal is connected between described first adjustable resistance and described second adjustable resistance by a NMOS tube.
USB line powersupply system the most according to claim 5, it is characterised in that:
Connect between described first adjustable resistance and power end at least two resistance.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620029795.3U CN205485900U (en) | 2016-01-12 | 2016-01-12 | USB line power supply system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620029795.3U CN205485900U (en) | 2016-01-12 | 2016-01-12 | USB line power supply system |
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| CN205485900U true CN205485900U (en) | 2016-08-17 |
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| CN201620029795.3U Active CN205485900U (en) | 2016-01-12 | 2016-01-12 | USB line power supply system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105487628A (en) * | 2016-01-12 | 2016-04-13 | 建荣集成电路科技(珠海)有限公司 | USB power supply system and method |
| US11049830B2 (en) | 2019-08-14 | 2021-06-29 | International Business Machines Corporation | Level shifting between interconnected chips having different voltage potentials |
-
2016
- 2016-01-12 CN CN201620029795.3U patent/CN205485900U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105487628A (en) * | 2016-01-12 | 2016-04-13 | 建荣集成电路科技(珠海)有限公司 | USB power supply system and method |
| US11049830B2 (en) | 2019-08-14 | 2021-06-29 | International Business Machines Corporation | Level shifting between interconnected chips having different voltage potentials |
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| C14 | Grant of patent or utility model | ||
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Effective date of registration: 20220315 Address after: Rooms 1306-1309, 13 / F, 19 science Avenue West, Hong Kong Science Park, Shatin, New Territories, China Patentee after: BUILDWIN INTERNATIONAL (ZHUHAI) LTD. Address before: 519015 3rd Floor, Stereo Science and Technology Building, 184 Bailian Road, Jida, Zhuhai City, Guangdong Province Patentee before: BUILDWIN INTERNATIONAL (ZHUHAI) Ltd. |
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| TR01 | Transfer of patent right |