CN110233582A - The method of inverter circuit and the driver in control inverter circuit - Google Patents
The method of inverter circuit and the driver in control inverter circuit Download PDFInfo
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- CN110233582A CN110233582A CN201811591487.XA CN201811591487A CN110233582A CN 110233582 A CN110233582 A CN 110233582A CN 201811591487 A CN201811591487 A CN 201811591487A CN 110233582 A CN110233582 A CN 110233582A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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Abstract
The present invention provides a kind of inverter circuits, comprising: inverter, driver and conversion rate control module, driver are coupled to the inverter, which is configured as receiving the first signal；And, conversion rate control module couples are in the driver, the conversion rate control module is configured as receiving the first signal and the second signal, the second signal indicates the size of the load of inverter circuit driving, wherein, which adjusts the conversion rate of the driver based on the second signal.Correspondingly, the present invention also provides a kind of methods of the driver in control inverter circuit.Using the present invention, the conversion rate of driver is dynamically adjusted according to the payload size that inverter circuit drives, can be improved the performance of inverter circuit.
Description
Technical Field
The present invention relates generally to an inverter circuit, and more particularly, to an inverter circuit having dynamic slew rate control and a method of controlling a driver in the inverter circuit.
Background
Inverter circuits may be used in many applications, such as output bus drivers, switching regulators, and direct current to direct current (DC-DC) converters, among others. The inverter circuit may be connected with other circuits on a Printed Circuit Board (PCB) to form an electronic assembly, which may be packaged separately or together with other electronic assemblies.
Disclosure of Invention
It is an object of the present invention to provide an inverter circuit with dynamic slew rate control and a method of controlling a driver in an inverter circuit.
The invention provides an inverter circuit, comprising an inverter, a driver and a slew rate control module, wherein the driver is coupled with the inverter and is configured to receive a first signal; and a slew rate control module coupled to the driver and configured to receive the first signal and a second signal, the second signal indicating a magnitude of a load driven by the inverter circuit, wherein the slew rate control module adjusts a slew rate of the driver based on the second signal.
The present invention also provides a method of controlling a driver in an inverter circuit, the method comprising: detecting the size of a load driven by the inverter circuit; and adjusting the slew rate of the driver according to the size of the load.
In the above technical solution, the slew rate of the driver is dynamically adjusted according to the magnitude of the load driven by the inverter circuit, so that the performance of the inverter circuit can be improved.
These and other objects of the present invention will be readily apparent to those skilled in the art from the following detailed description of the preferred embodiments as illustrated in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings.
Drawings
The present invention may be more completely understood by reading the following detailed description and examples given with reference to the accompanying drawings.
Fig. 1A is a schematic diagram of an inverter circuit without dynamic slew rate control.
Fig. 1B is a schematic timing diagram illustrating signal bounce in the inverter circuit of fig. 1A.
Fig. 2 is a schematic diagram illustrating an inverter circuit with dynamic slew rate control (with current representative of load current) in accordance with some embodiments.
Fig. 3 is a schematic diagram illustrating some implementation details of the inverter circuit of fig. 2, in accordance with some embodiments.
Fig. 4 is a flow diagram illustrating a method for dynamically controlling the slew rate of a driver in the inverter circuit of fig. 2, in accordance with some embodiments.
Fig. 5 is a schematic diagram illustrating an inverter circuit with dynamic slew rate control (using a voltage representative of an input voltage) in accordance with some embodiments.
Fig. 6 is a schematic diagram illustrating some implementation details of the inverter circuit of fig. 5, in accordance with some embodiments.
Fig. 7 is a flow diagram illustrating a method for dynamically controlling the slew rate of a driver in the inverter circuit of fig. 5, in accordance with some embodiments.
Fig. 8 is a schematic diagram illustrating an inverter circuit with dynamic slew rate control (with a mode configuration of the inverter circuit) in accordance with some embodiments.
Fig. 9 is a flow diagram illustrating a method for dynamically controlling the slew rate of a driver in the inverter circuit of fig. 8, in accordance with some embodiments.
Fig. 10A is a schematic diagram comparing Safe Operating Area (SOA) under different load conditions for transistors in a driver without a dynamic slew rate controlled inverter circuit.
Fig. 10B is a graph diagram illustrating comparison of SOAs under different load conditions for transistors in a driver with an inverter circuit with dynamic slew rate control, in accordance with some embodiments.
In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that different embodiments may be combined as desired, and should not be limited to the embodiments set forth in the accompanying drawings.
Detailed Description
The following description is of the preferred embodiments of the present invention, which are provided for illustration of the technical features of the present invention and are not intended to limit the scope of the present invention. Certain terms are used throughout the description and claims to refer to particular elements, it being understood by those skilled in the art that manufacturers may refer to a like element by different names. Therefore, the present specification and claims do not intend to distinguish between components that differ in name but not function. The terms "component," "system," and "apparatus" used herein may be an entity associated with a computer, wherein the computer may be hardware, software, or a combination of hardware and software. In the following description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to …". Furthermore, the term "coupled" means either an indirect or direct electrical connection. Thus, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Wherein corresponding numerals and symbols in the various figures of the drawing generally refer to corresponding parts unless otherwise indicated. The accompanying drawings, which are drawn to clearly illustrate the relevant portions of the embodiments, are not necessarily drawn to scale.
The term "substantially" or "approximately" as used herein means within an acceptable range that a person skilled in the art can solve the technical problem to substantially achieve the technical effect to be achieved. For example, "substantially equal" refers to a manner that is acceptable to the skilled artisan with some error from "substantially equal" without affecting the correctness of the results.
Applicants have discovered through research that for inverter circuits with a wide dynamic current range, parasitic resistance and inductance introduced by Printed Circuit Boards (PCBs) or other package components can cause signal bounce (signal bounce) where signals vary in the circuit in response to transients. The signal bounce includes, for example, ground bounce, supply voltage bounce, and output voltage bounce. Taking ground bounce as an example, the parasitic inductance is connected between the internal device ground and the external system ground. Due to the varying current, the voltage across the parasitic inductance may cause the internal ground to be at a different potential than the external ground. Some devices in the circuit are subject to stress (be stressed) and may even be damaged due to the difference between the internal ground potential and the external ground potential.
The conventional solution keeps the slew rate (slew rate) of the DRIVER of the inverter circuit at the same rate for different load conditions and mode configurations (e.g., in fig. 1A, the slew rates of the output signals of the DRIVERs UGATE _ DRIVER and LGATE _ DRIVER for transitioning from 0 to 1 or from 1 to 0 are the same in different load conditions and/or different mode configurations). However, applicants have found that the option of choosing one slew rate for different load conditions and mode configurations can cause problems. For example, if the slew rate is selected under the heaviest load conditions, the peak power efficiency of the converter circuit (e.g., buck converter) is poor, e.g., below 80%. On the other hand, if Pulse Frequency Mode (PFM) peak current selects the slew rate, it is difficult to design package components (e.g., PCB layout), or Lateral Diffused MOSFETs (LDMOS) are required. Therefore, a safe operation region of transistors in a driver of the inverter circuit: (safe operating area, SOA) is reduced (e.g., fig. 10A). SOA refers to the voltage and current conditions under which a transistor can be expected to operate normally. Transistors operating outside the SOA can cause circuit failure. Those of ordinary skill in the art will recognize that SOAs may be present in a transistor datasheet as having a drain-source voltage (V)DS) As the x-axis and gate-source voltage (V)GS) Graph as y-axis; SOA may refer to the area under the curve. However, the techniques described herein are not limited to the particular manner of illustrating an SOA.
Applicants have discovered through research that dynamically controlling the slew rate of an inverter circuit can improve or maximize SOA utilization of the transistors. Signal bounce is more severe when the inverter circuit drives a heavy (heavy) load than when driving a light (light) or medium (middle-level) load. The current and/or voltage at which the inverter circuit drives a heavy load (that is, the current and/or voltage can reflect the magnitude of the load) is higher than when driving a light or medium load. The inverter circuit and the method for controlling the driver in the inverter circuit provided by the invention adjust the conversion rate of the driver according to the size of the load driven by the inverter circuit. In some embodiments, when an increase in load is detected, the slew rate of the driver in the inverter circuit is reduced. In some embodiments, when a decrease in load is detected, the slew rate of the driver in the inverter circuit is increased. In other embodiments, the slew rate of the driver is set to the first predetermined rate when the load is detected to be higher than the predetermined load (e.g., the load current is detected to be higher than the reference current, or the input voltage, which can reflect the load size, is detected to be higher than the reference voltage). In other embodiments, the slew rate of the driver is set to a second predetermined rate when the load is detected to be below the predetermined load, wherein the second predetermined rate is higher than the first predetermined rate. By comparing the current and/or voltage with one or more thresholds, the load driven by the inverter circuit can be determined to be heavy, medium or light. In some embodiments, when the inverter circuit drives a heavy load (e.g., the load is detected to be higher than a predetermined load, in particular, the load current is detected to be higher than a reference current, or,capable of reflecting the magnitude of the load is higher than the reference voltage), reducing the slew rate of the driver in the (reduce) inverter circuit may mitigate the effects of signal bounce, thereby allowing the transistors in the inverter circuit to utilize the input voltage for a particular VGSV ofDSTo operate safely over a wider range. On the other hand, when the inverter circuit drives a light or medium load (for example, it is detected that the load is lower than a predetermined load, in particular, that the load current is lower than a reference current, or that the input voltage that can reflect the magnitude of the load is lower than a reference voltage), the slew rate of the driver in the inverter circuit is increased (increased) on the basis of the slew rate used when the inverter circuit drives a heavy load, so that the inverter can generate an output voltage that responds faster.
In some embodiments, the inverter circuit includes an inverter, which is driven by the driver. The slew rate of the output of the driver is controlled by a slew rate control module. Both the driver and the slew rate control module receive the first signal. In some embodiments, the first signal is a Pulse Width Modulated (PWM) signal. The slew rate control module receives a second signal indicative of (or capable of reflecting) a magnitude of a load driven by the inverter circuit. In some embodiments, the slew rate control module decreases (or decreases) the slew rate of the output of the driver when the second signal indicates that the magnitude of the load is increasing. In some embodiments, the slew rate control module increases the slew rate of the output of the driver when the second signal indicates that the size of the load is decreasing.
In some embodiments, the second signal indicative of the magnitude of the load driven by the inverter circuit may be a signal representative of the load current. In some embodiments, the second signal indicative of the magnitude of the load driven by the inverter circuit may be a voltage representative of the input voltage.
In some embodiments, the slew rate control module receives a third signal indicating a mode configuration of the inverter circuit. The mode configuration is selected from a plurality of modes including a Dynamic Voltage Scaling (DVS) mode and a multi-phase mode. The slew rate control module modifies or adjusts a slew rate of a driver in the inverter circuit based on a mode configuration of the inverter circuit. In some embodiments, the slew rate control module reduces or decreases the slew rate of the driver in the inverter circuit when the third signal indicates that the inverter circuit is operating in the DVS mode or the multiphase mode.
Fig. 1A is a schematic diagram of an inverter circuit 100 without dynamic slew rate control. The inverter circuit 100 includes an input 112 (for receiving a Pulse Width Modulation (PWM) waveform 150), an inverter 102 (having a first transistor UGATE and a second transistor LGATE), a first DRIVER UGATE _ DRIVER for driving the first transistor UGATE, a second DRIVER LGATE _ DRIVER for driving the second transistor LGATE, and an output capacitor 132 (having a capacitance value C0) An output 116 for driving a load (not shown) (output 116 for outputting voltage V0), and a power supply 114 (which is shared by the load). The power supply 114 includes a positive supply voltage VDD (e.g., an external positive supply voltage) and a negative supply voltage VSS (e.g., an external negative supply voltage). Inverter 102 includes an internal positive supply voltage PVDD, an internal negative supply voltage PVSS, and an internal output LX. The first DRIVER UGATE _ DRIVER and the second DRIVER LGATE _ DRIVER share the internal positive supply voltage PVDD and the internal negative supply voltage PVSS with the inverter 102.
Inverter circuit 100 also includes parasitic resistances and inductances introduced by the package components. For example, parasitic resistance and inductance 124 introduced by bond wires (bondingwires); parasitic resistance and inductance 126 and parasitic capacitance 130 (capacitance value CIN) introduced by the PCB routing. Parasitic resistances and inductances 124, 126 cause a difference between the internal positive supply voltage PVDD and the external positive supply voltage VDD. The parasitic resistances and inductances 124, 126 also cause a difference between the internal negative supply voltage PVSS and the external negative supply voltage VSS.
The output 116 may be switched from a high voltage to a low voltage, which is referred to as a falling edge transition (falling edge transition), or from a low voltage to a high voltage,which is called a rising edge transition (rising edge transition). During switching, the output capacitance 132 and the parasitic capacitance 130 charge or discharge and generate a transient current. The transient current is C0CIN and C0And the voltage on CIN as a function of time t (av/at). The transient current flowing through the parasitic resistance and inductance 124, 126 creates a voltage across the parasitic resistance and inductance. The voltage across the parasitic inductance is a function of the transient current over time t (Δ I/Δ t). Thus, the internal positive supply voltage PVDD is at a different voltage than the external positive supply voltage VDD; the internal negative supply voltage PVSS is at a different voltage than the external negative supply voltage VSS.
Fig. 1B is a schematic timing diagram illustrating signal bounce in the inverter circuit 100 during a falling edge transition of the PWM waveform 150. The voltage level of the internal positive supply voltage PVDD over time t is shown by curve 138, from which the supply voltage bounce 144 can be seen. The voltage level of the internal negative supply voltage PVSS over time t is shown by curve 140, from which curve 140 the ground bounce 146 can be seen. The curve 142 shows the voltage level of the internal output LX over time t. During the falling edge transition of the PWM waveform 150, the internal output LX follows the internal negative supply voltage PVSS, and the ground bounce 148 can be seen from the curve 142. Thus, NMOS transistors (NMOS transistors coupled to the internal negative supply voltage PVSS, e.g., NMOS transistors in UGATE _ DRIVER) are stressed by ground bounce (e.g., 146 and 148), and PMOS transistors (PMOS transistors coupled to the internal positive supply voltage PVDD, e.g., PMOS transistors in LGATE _ DRIVER) are stressed, or even damaged, by supply voltage bounce (e.g., 144).
Fig. 2 is a schematic diagram illustrating an inverter circuit 200 with dynamic slew rate control in accordance with some embodiments. Inverter circuit 200 includes an external input 212, an inverter 202, a driver 248, and a slew rate control module 244. In some embodiments, external input 212 receives a Pulse Width Modulation (PWM) waveform 350, e.g., Pulse Width Modulation (PWM) waveform 350 from a controller. Inverter 202 has an input 252 and an output 250. In some embodiments, the output 250 of the inverter 202 may be used to drive a load (not shown). Driver 248 has a first input 256, a second input 258, and an output 254. A first input 256 of driver 248 is coupled to external input 212 of inverter circuit 200. An output 254 of the driver 248 is coupled to the input 252 of the inverter 202.
The slew rate control module 244 has a first input 262, a second input 264 and an output 260. A first input 262 of the slew rate control module 244 is coupled to the external input 212 of the inverter circuit 200. A second input 246 of the slew rate control module 244 receives a load current IL indicative of (indicative of) a magnitude (magnitude) of a load driven by the inverter circuit 200. In some embodiments, the load current IL is compared to one or more reference currents. For example, based on the comparison result, the load driven by the inverter circuit may be determined to be heavy, light, or medium. An output 260 of the slew rate control module 244 is coupled to a second input 258 of the driver 248.
Fig. 3 is a schematic diagram illustrating some implementation details of inverter circuit 200, according to some embodiments. For ease of understanding and illustration, the configuration of fig. 3 is exemplified by the slew rate of the rising edge transition of the control signal at the output 254 of the driver 248 from 0 to 1, and it should be understood by those skilled in the art that the following would be understood accordingly based on the embodiment shown in fig. 3: a configuration that controls the slew rate of the falling edge transition of the signal on output 254 of driver 248 from 1 to 0. As shown in fig. 3, the inverter 202 includes a first transistor UGATE and a second transistor LGATE. In some embodiments, the first transistor UGATE may be a p-type transistor; the second transistor LGATE may be an n-type transistor. The driver 248 may include a transistor C, a transistor D, and a transistor E. Transistors C and E may be p-type transistors. The transistor D may be an n-type transistor. Transistors C and E are connected in parallel. The transistor C is connected in series to the transistor D. It should be noted that the embodiment of the present invention does not limit the specific type of the transistor, and may be, for example, a field effect transistor, a bipolar junction transistor, or the like.
The slew rate control module 244 includes a comparator 266 and an OR gate (OR gate) 272. Comparator 266 has an input 264 and an output 268. Comparator 266 compares the sensed current Isense to the reference current IREF. In some embodiments, the sense current Isense is related to the load current IL. For example, the sense current Isense represents the magnitude of the load current IL. In some embodiments, when the sense current Isense is higher than the reference current IREF, the output 268 of the comparator 266 is a high voltage level (e.g., a high voltage level representing a logic 1); when the sense current Isense is lower than the reference current IREF, the output 268 of the comparator 266 is a low voltage level (e.g., a low voltage level representing a logic 0). Or gate 272 has a first input 270, a second input 262 and an output 260. The first input 270 of the OR gate 272 is coupled to the output 268 of the comparator 266. Second input 262 of or gate 272 is coupled to external input 212 of inverter circuit 200. The output 260 of the OR gate 272 is coupled to the gate terminal 258 of the transistor E.
In the example shown in fig. 3, the circuit configuration discussed above sets the slew rate of driver 248 (e.g., the transition rate of the rising edge transition of the signal on output 254 of driver 248 from 0 to 1) to a lower first predetermined rate when inverter circuit 200 is driving a heavy load, and sets the slew rate of driver 248 to a higher second predetermined rate when inverter circuit 200 is driving a light or medium load. In an embodiment of the present invention, the slew rate of driver 248 is controlled by both output 260 of slew rate control module 244 and external input 212 of inverter circuit 200, wherein the signal on output 260 of slew rate control module 244 is controlled by the load magnitude and PWM waveform 350. For example, during the time that the PWM waveform 350 outputs a low voltage level, transistor C is on, on the other hand, if the comparator 266 detects that the sense current Isense is higher than the reference current IREF (e.g., the load is heavier), then the comparator 266 outputs a high voltage level on its output 268, and correspondingly, the output 260 of the slew rate control module 244 outputs a high voltage level, such that transistor E is off, such that the slew rate of the driver 248 has a first predetermined rate (transistor C is on and transistor E is off) when the PWM waveform 350 transitions from the high voltage level to the low voltage level; conversely, if the comparator 266 detects that the sensed current Isense is below the reference current IREF (e.g., the load is light), the comparator 266 outputs a low voltage level at its output 268 and, correspondingly, the output 260 of the slew rate control module 244 outputs a low voltage level (because the PWM waveform 350 is now low), such that the transistor E is on, such that the slew rate of the driver 248 has a second predetermined rate (both transistor C and transistor E are on) as the PWM waveform 350 transitions from the high voltage level to the low voltage level, and therefore, the second predetermined rate is higher than the first predetermined rate. The first transistor UGATE is turned off (turn off) when the output 254 of the driver 248 goes high. The slew rate at the output 254 of the driver 248 is controlled by both the output 260 of the slew rate control module 244 and the external input 212 of the inverter circuit 200. The falling edge transition of the PWM waveform 350 turns transistor C on and transistor D off. The output 260 of the slew rate control module 244 goes low turning on transistor E. To bring the output 260 of the or gate 272 low, the output 270 of the comparator 266 and the PWM waveform 350 must be low. Although the slew rate control module is illustrated with respect to the first transistor UGATE, it will be understood by those of ordinary skill in the art that the second transistor LGATE may have a slew rate control module with respect to the rising edge transition of the PWM waveform 350, the implementation details of which may be found with reference to the transistors E, C and D provided in the driver 248 for the first transistor UGATE, respectively, resulting in a modified design for the second transistor LGATE. It should be noted that fig. 3 is only an exemplary structure to which the present invention is not limited, for example, in a modified design, one or more other transistors may also be present in parallel with transistors E and/or C, etc.
Fig. 4 is a flow diagram illustrating a method 400 of dynamically controlling the slew rate of drive 248, according to some embodiments. The method 400 may begin at step 402 when the inverter circuit is instructed to operate with dynamic slew rate control (e.g., by a system signal from the controller). At step 404, the magnitude of the load current is detected. The load current may be a current flowing through a load driven by the inverter circuit 200. The magnitude of the load current may be indicative of the magnitude of the load driven by the inverter circuit. At step 406, the magnitude of the detected load current may be evaluated, for example, by using comparator 266. In some embodiments, if the magnitude of the detected load current is determined to be heavy (e.g., the load current is large, such as above the reference current IREF), the slew rate of driver 248 is modified to a first rate (step 408), which means slower falling/rising edge transitions, so that the problem of signal bounce can be mitigated. On the other hand, if the magnitude of the detected load current is determined to be not heavy (e.g., below the reference current IREF), the slew rate of the driver 248 is modified to a second rate that is higher than the first rate (step 410), which means faster falling/rising edge transitions.
Fig. 5 is a schematic diagram illustrating an inverter circuit 500 with dynamic slew rate control in accordance with some embodiments. Unlike fig. 2, where inverter circuit 500 includes a slew rate control module 544, a driver 548, and an inverter 502, slew rate control module 544 receives an input voltage VIN, which may be indicative of a magnitude of a load driven by inverter circuit 500, and slew rate control module 244 in inverter circuit 200 shown in fig. 2 receives a load current IL. In some embodiments, the input voltage VIN may be compared to one or more reference voltages. Based on the comparison result, the load driven by the inverter circuit can be determined to be heavy, light, or medium.
Fig. 6 is a schematic diagram illustrating some implementation details of an inverter circuit 500, according to some embodiments. Rather than comparing the sense current Isense to the reference current IREF as shown in fig. 3, the slew rate control module 544 compares the input voltage VIN to the reference voltage VREF. In some embodiments, when the input voltage VIN is higher than the reference voltage VREF, the output 568 of the comparator 566 is high; when VIN is lower than reference VREF, output 568 of comparator 566 is low. Although fig. 6 depicts a slew rate control module with respect to the first transistor UGATE, one of ordinary skill in the art will appreciate that the second transistor LGATE may have a slew rate control module with respect to the falling edge transition of the PWM waveform 650.
Fig. 7 is a flow diagram illustrating a method 700 for dynamically controlling the slew rate of a driver 548 of an inverter, in accordance with some embodiments. The method 700 may begin at step 702 when the inverter circuit is instructed to operate with dynamic slew-rate control (e.g., instructed by a system signal from the controller). At step 704, the magnitude of the input voltage is detected. The input voltage may be a voltage shared by the loads driven by inverter circuit 500. The magnitude of the input voltage may be indicative of the magnitude of a load driven by the inverter circuit. At step 706, the magnitude of the detected input voltage may be evaluated, for example, by using comparator 566. In some embodiments, if the magnitude of the detected input voltage is determined to be high, e.g., above the reference voltage VREF, the slew rate of driver 548 can be modified (or set) to a third rate (step 708), which means slower falling/rising edge transitions, so that the problem of signal bounce can be mitigated. On the other hand, if the magnitude of the detected input voltage is determined not to be high, e.g., below the reference voltage VREF, the slew rate of driver 548 can be modified (or set) to a fourth rate that is higher than the third rate (step 710), which means faster falling/rising edge transitions.
Fig. 8 is a schematic diagram illustrating an inverter circuit 800 with dynamic slew-rate control, the inverter circuit 800 including a slew-rate control module 844, a driver 848, and an inverter 802, in accordance with some embodiments. The slew rate control module 844 may receive the load current IL as shown in fig. 2 or the input voltage VIN as shown in fig. 5, and in addition, the slew rate control module 844 may receive a mode signal 882 from the controller 880. Mode signal 882 indicates the mode configuration of inverter circuit 800. The mode configuration of the inverter circuit is selected from a plurality of modes, such as a dynamic voltage regulation (DVS) mode and a multiphase mode.
Fig. 9 is a flow diagram illustrating a method 900 for dynamically controlling the slew rate of the driver 848 of the inverter in fig. 8. The method 900 may begin at step 902 when the inverter circuit is instructed to operate with dynamic slew rate control (e.g., by a system signal from the controller). At step 904, the mode configuration of the inverter circuit 800 is detected. The mode configuration of the inverter circuit may be selected from a plurality of modes, such as a Dynamic Voltage Scaling (DVS) mode and a multiphase mode. At step 906, it is determined whether the inverter circuit 800 is operating in a Dynamic Voltage Scaling (DVS) mode or a multi-phase mode. In some embodiments, if it is determined that inverter circuit 800 is operating in a Dynamic Voltage Scaling (DVS) mode or a multi-phase mode, the slew rate of driver 848 is modified to a fifth rate (step 908), which means slower falling/rising edge transitions, thereby mitigating the problem of signal bounce. On the other hand, if it is determined that inverter circuit 800 is operating in neither a Dynamic Voltage Scaling (DVS) mode nor a multiphase mode, method 900 proceeds to step 910.
In some embodiments, the magnitude of the load driven by the inverter circuit 800 may also be detected at step 904. In some embodiments, detecting the magnitude of the load driven by the inverter circuit 800 may be performed in a later step, e.g., after step 906. In some embodiments, the magnitude of the load driven by the inverter circuit may be indicated by the load current. In some embodiments, the magnitude of the load driven by the inverter circuit may be indicated by the input voltage. At step 910, the magnitude of the load driven by the inverter circuit is evaluated (e.g., whether the load is heavy is evaluated by the load current IL or the input voltage VIN). In some embodiments, if the load driven by the inverter circuit is sized to be heavy, the slew rate of the driver 848 is modified to a fifth rate (step 908), which means slower falling/rising edge transitions, so that the problem of signal bounce can be mitigated. On the other hand, if the load driven by the inverter circuit is sized not heavy, the slew rate of the driver 848 is modified to a sixth rate that is higher than the fifth rate (step 912), which means faster falling/rising edge transitions.
Fig. 10A is a schematic diagram of a Safe Operating Area (SOA) comparison of transistors in an inverter DRIVER without dynamic slew rate control (e.g., first DRIVER UGATE DRIVER) under different load conditions. Curve 1002A shows the inherent SOA of the transistor, e.g. without any load effect. A curve 1004A (SOA _ heaviload) represents the SOA with the transistor under heavy load conditions. Curve 1006A (SOA _ LightLoad) represents the SOA with the transistor under light load conditions. The SOA of the transistor is disadvantageously reduced from the inherent SOA due to the load condition. For example, when the gate terminal (V _ GS) of the transistor is biased at 2V, curve 1002A represents no load, as long as the drain terminal (V _ DS) of the transistor is biased below 8V, the transistor will operate normally; curve 1004A indicates that under heavy loading, the drain terminal of the transistor should be biased below 6.4V to ensure that the transistor is operating properly; curve 1006A indicates that under light load, the drain terminal of the transistor should be biased below 6V to ensure that the transistor operates properly.
Fig. 10B is a graphical illustration of SOA comparison for transistors in an inverter driver with dynamic slew-rate control under different load conditions, in accordance with some embodiments. Curve 1002B shows the inherent SOA of the transistor, e.g., without any load effects. Curve 1004B represents the SOA with the transistor under heavy load conditions. Curve 1006B represents the SOA with the transistor under light load conditions. While the SOA of the transistors is still disadvantageously reduced from the inherent SOA due to load conditions, as shown by circle 10B, curves 1004B and 1006B represent transistors in the inverter driver with dynamic slew-rate control having an extended SOA compared to transistors in the inverter driver without slew-rate control. For example, when the gate terminal (V _ GS) of the transistor is biased to 2V, as represented by curve 1002A, curve 1002B, the transistor will operate normally without any load as long as the drain terminal (V _ DS) of the transistor is biased below 8V; unlike the curve 1004A, the curve 1004B indicates that, under heavy load, the safe operating range of the drain terminal of the transistor is extended from 6.4V to (is extended to) 7.2V; and, unlike curve 1006A, curve 1006B indicates that the safe operating range of the drain terminal of the transistor is extended from 6V to 7.2V under light load.
In the foregoing detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the invention. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that different embodiments, or different features disclosed in different embodiments, may be combined as desired and should not be limited to the embodiments illustrated in the drawings.
While the invention has been described by way of example and in terms of preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art), e.g., combinations or substitutions of different features in different embodiments. The scope of the appended claims should, therefore, be accorded the broadest interpretation so as to encompass all such modifications and similar structures.
Claims (12)
1. An inverter circuit comprising:
an inverter;
a driver coupled to the inverter, the driver configured to receive a first signal; and the number of the first and second groups,
a slew rate control module coupled to the driver, the slew rate control module configured to receive the first signal and a second signal, the second signal indicating a magnitude of a load driven by the inverter circuit, wherein the slew rate control module adjusts a slew rate of the driver based on the second signal.
2. The inverter circuit of claim 1, wherein the slew rate control module is further configured to receive a third signal indicative of a mode configuration of the inverter circuit, and wherein the slew rate control module is further configured to adjust the slew rate of the driver based on the third signal.
3. The inverter circuit of claim 2, wherein the mode configuration of the inverter circuit is selected from a plurality of modes including a Dynamic Voltage Scaling (DVS) mode and a multiphase mode.
4. The inverter circuit of claim 1, wherein the second signal is a current representative of a load current or a voltage representative of an input voltage, and wherein the slew rate control module comprises a comparator configured to compare the second signal to a reference signal to control the driver based on the comparison.
5. The inverter circuit of claim 4, wherein the slew rate control module further comprises an OR gate configured to receive the first signal and the output of the comparator, and the OR gate outputs to the driver.
6. The inverter circuit of claim 1, wherein the slew rate control module decreases the slew rate of the driver when the second signal indicates an increase in the magnitude of the load and/or increases the slew rate of the driver when the second signal indicates a decrease in the magnitude of the load.
7. The inverter circuit of claim 1, wherein the slew rate control module sets the slew rate of the driver to a first predetermined rate when the second signal indicates that the load is above a predetermined load, and sets the slew rate of the driver to a second predetermined rate when the second signal indicates that the load is below the predetermined load, wherein the second predetermined rate is higher than the first predetermined rate.
8. A method of controlling a driver in an inverter circuit, the method comprising:
detecting the size of a load driven by the inverter circuit; and
the slew rate of the driver is adjusted according to the size of the load.
9. The method of claim 8, wherein the step of adjusting the slew rate of the driver based on the size of the load comprises: when the load increase is detected, reducing the slew rate of the driver; and/or the presence of a gas in the gas,
when a decrease in the load is detected, the slew rate of the driver is increased.
10. The method of claim 8, further comprising: a mode configuration of the inverter circuit is detected, and a slew rate of the driver is adjusted based on the mode configuration, wherein the mode configuration of the inverter circuit is selected from a plurality of modes including a Dynamic Voltage Scaling (DVS) mode and a multiphase mode.
11. The method of claim 8, wherein the step of adjusting the slew rate of the driver based on the size of the load comprises: the slew rate of the driver is set to a first predetermined rate when the load is higher than a predetermined load, and the slew rate of the driver is set to a second predetermined rate when the load is lower than the predetermined load, wherein the second predetermined rate is higher than the first predetermined rate.
12. The method of claim 8, wherein the step of detecting the magnitude of the load driven by the inverter circuit comprises: detecting the magnitude of the load driven by the inverter circuit by detecting a current representing a load current, wherein when the current is higher than a reference current, it represents that the load driven by the inverter circuit is higher than a predetermined load, and when the current is lower than the reference current, it represents that the load driven by the inverter circuit is lower than the predetermined load; or,
the magnitude of the load driven by the inverter circuit is detected by detecting a voltage representing an input voltage, wherein when the voltage is higher than a reference voltage, it represents that the load driven by the inverter circuit is higher than a predetermined load, and when the voltage is lower than the reference voltage, it represents that the load driven by the inverter circuit is lower than the predetermined load.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/912,396 | 2018-03-05 | ||
| US15/912,396 US10784763B2 (en) | 2017-03-07 | 2018-03-05 | Dynamic slew rate control |
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| CN110233582B CN110233582B (en) | 2021-01-26 |
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| US20220302910A1 (en) * | 2021-03-22 | 2022-09-22 | Magnachip Semiconductor, Ltd. | Slew rate acceleration circuit and buffer circuit including the same |
| WO2024048884A1 (en) * | 2022-09-02 | 2024-03-07 | Lg Electronics Inc. | Power supply device and operating method thereof |
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Also Published As
| Publication number | Publication date |
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| CN110233582B (en) | 2021-01-26 |
| TWI678064B (en) | 2019-11-21 |
| TW201939874A (en) | 2019-10-01 |
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