CN205484499U - A equipment for measuring transmit average inductor current of giving load - Google Patents
A equipment for measuring transmit average inductor current of giving load Download PDFInfo
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- CN205484499U CN205484499U CN201520940660.8U CN201520940660U CN205484499U CN 205484499 U CN205484499 U CN 205484499U CN 201520940660 U CN201520940660 U CN 201520940660U CN 205484499 U CN205484499 U CN 205484499U
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Abstract
The utility model relates to a circuit, including electric current sensing circuit, electric current sensing circuit is configured as and is used for generating the sensing electric current, the sensing electric current is with to flow through the inductor current of inductor in response to pulsewidth modulation (PWM) control signal corresponding, and averaging circuit, the averaging circuit is in the operation is in order to handle in each stage in the one or more PWM cycle in PWM control signal's the one or more PWM cycle the sensing electric current to generate to instruct and flow through the output signal of the average current of inductor.
Description
Technical field
This utility model relates to current sense, and passes to load in particular to by inductive circuit measurement
Average current.
Background technology
With reference to Fig. 1, the figure shows the circuit diagram of basic switch adjuster circuit 10.This circuit includes having first (more
Just) node 14 and the supply voltage 12 of second (more negative or ground connection) node 16.Transistor switch 18 (in this example, n-channel
MOSFET element) there is the current conduction path (source drain path) being coupled between node 14 and intermediate node 20.Crystal
The control terminal (grid) of pipe switch 18 receives pulsewidth modulation (PWM) control signal generated by control circuit 22.Diode 24
It is connected between node 20 and ground nodes 16 that (wherein anode terminal is coupled to node 16 and cathode terminal is coupled to joint
Point 20).It will be understood by those skilled in the art that if necessary, diode 24 is readily modified as by transistor switch (such as n
Trench MOSFET device) replace, this transistor switch is by the suitable stage control of pwm control signal.During inducer 26 is coupled in
Between intermediate node 20 and output node 28.Current sensing circuit 30 may be used for sensing electric current of flowing in inducer 26, its
Middle sensing electric current is used for generating pwm signal to regulate output by control circuit 22.Voltage sensing circuit 32 may be used for sensing defeated
The voltage in source, wherein sensing voltage is used for generating pwm signal to regulate output by control circuit 22.Capacitor 34 and load 36
Coupled in parallel is between output node 28 and node 16.Pwm signal has fixing frequency, but has and set by control circuit 22
The variable duty ratio put.
Fig. 2 shows the general configuration of pwm signal.During the first stage 40 of the PWM cycle of pwm signal, crystal
Pipe switch 18 connection and electric current flow through inducer 26 to charge capacitor 34 from supply voltage 12.In this phase in stage 40
Between, the electric current through inducer 26 increases.During the second stage 42 of PWM cycle, transistor switch 18 turns off and power supply
Voltage 12 disconnects from inducer 26.Diode 24 becomes forward biased and inductor current flows through load 26.In this stage
During 42, the electric current through inducer 26 reduces.Fig. 3 shows the electric current flowing waveform of inductor current.
In some cases, the measurement to the average current (Iav) flowing through inducer be it is to be understood that important operation special
Point.This area what is desired is that a kind of circuit for measuring average inductor current and method.
Utility model content
According to an aspect of this disclosure, it is provided that a kind of circuit, including: current sensing circuit, described current sensing circuit
Be configured for generate sensing electric current, described sensing electric current with flow through inductance in response to pulsewidth modulation (PWM) control signal
The inductor current of device is corresponding；And average circuit, described average circuit is one or more described pwm control signal
Run to process described sensing electric current in each stage of one or more PWM cycle in PWM cycle, thus generate instruction and flow through
The output signal of the average current of described inducer.
Alternatively, described inductor current has a stage phase with the one or more cycles in described PWM cycle
The maximum current associated and the minimum current being associated with another stage in the one or more cycles in described PWM cycle, institute
State average circuit and during the one stage, process described sensing electric current to obtain the first value and in another phase in stage described
Between process described sensing electric current and be used for generating described output signal to obtain the second value, described first value and described second value.
Alternatively, described average circuit includes: capacitor, described capacitor during the one stage by described sensing
Electric current charges, and described first value includes charging voltage, and described capacitor is discharging current, described electric current during another stage described
The amplitude having is the integral multiple of the amplitude of described sensing electric current, and described second value includes discharge voltage；Resistor, described sensing
Electric current flows through described resistor to generate voltage；And sample-and-hold circuit, described sample-and-hold circuit is by described discharge voltage
Trigger with to described voltage sampling and generate instruction and flow through the described output signal of average current of described inducer.
Alternatively, described integral multiple is 2.
Alternatively, described average circuit farther includes comparison circuit, and described comparison circuit is configured for described
Discharge voltage compares with reference voltage and generates in response to described comparison for triggering described sample-and-hold circuit
Trigger signal.
Alternatively, each PWM cycle includes first stage and second stage, and wherein, the one stage is first
The first stage of PWM cycle, and wherein, another stage described is different from the second PWM cycle of described first PWM cycle
First stage.
Alternatively, farther including analog-digital converter circuit, described analog-digital converter circuit is configured for described
The output signal generated is converted into numeral output.
Alternatively, described average circuit includes: the first capacitor, described first capacitor during the one stage by
Described sensing electric current charges, and described first value includes the first charging voltage；Second capacitor, described second capacitor described separately
Being charged by described sensing electric current during one stage, described second value includes the second charging voltage；Electric charge shares circuit, described electric charge
Shared circuit is configured for optionally sharing electric charge between described first capacitor and described second capacitor；And
Sample-and-hold circuit, described sample-and-hold circuit by electric charge shared trigger service with to described first capacitor and described second capacitor
Share voltage sampling and generate instruction and flow through the described output signal of average current of described inducer.
Alternatively, described average circuit farther includes: the first switch, and described first switch is in response to the one stage
And be selectively activated, thus to described first capacitor charging；And second switch, described second switch is in response to described
Another stage and be selectively activated, thus to described second capacitor charging.
Alternatively, described second switch was the most optionally activated in response to the one stage.
Alternatively, described average circuit farther includes the 3rd switch, and described 3rd switch is selectively activated, thus
Described first capacitor and described second capacitor are connected in parallel to share electric charge.
Alternatively, farther including analog-digital converter circuit, described analog-digital converter circuit is configured for described
The output signal generated is converted into numeral output.
Alternatively, described average circuit includes: resistor, and described sensing electric current flows through described resistor to generate and inductance
The voltage that device electric current is corresponding；And sample-and-hold circuit, described sample-and-hold circuit is in response to corresponding with inductor current
Described voltage and be triggered with to the average voltage sampling generated and generate instruction and flow through the average current of described inducer
Described output signal.
Alternatively, farther including analog-digital converter circuit, described analog-digital converter circuit is configured for described
The output signal generated is converted into numeral output.
Alternatively, farther including buffer circuit, described buffer circuit is coupled in described resistor and keeps with described sampling
To buffer described average voltage between circuit.
Alternatively, described average circuit farther includes: the first capacitor, and described first capacitor is by described sensing electric current
Charge with generating the first charging voltage being associated with maximum inductor current；Second capacitor, described second capacitor is by institute
State the second charging voltage that sensing electric current charging is associated with maximum inductor current with generation；And electric charge shares circuit, institute
State electric charge share circuit be configured between described first capacitor and described second capacitor optionally share electricity
Lotus and export described average voltage.
Alternatively, described average circuit farther includes: the first switch, and described first switch is in response to the of PWM cycle
One stage and be selectively activated, thus to described first capacitor charging；And second switch, described second switch responds
It is selectively activated in the second stage of described PWM cycle, thus to described second capacitor charging.
Alternatively, described second switch was the most optionally activated in response to the described first stage.
Alternatively, described average circuit farther includes the 3rd switch, described 3rd switch quilt during follow-up PWM cycle
Optionally activate, thus described first capacitor and described second capacitor are connected in parallel to share electric charge.
Alternatively, described average circuit includes: capacitor, described capacitor during the stage of the first PWM cycle by institute
Stating sensing electric current to charge to generate charging voltage, described capacitor is discharging current during the stage of the second PWM cycle, thus raw
Becoming discharge voltage, the amplitude that described electric current has is the integral multiple of the amplitude of described sensing electric current；And comparison circuit, described ratio
Relatively circuit is configured for being compared with reference voltage by described discharge voltage and generating use in response to described comparison
In the triggering signal triggering described sample-and-hold circuit.
Alternatively, described integral multiple is 2.
Accompanying drawing explanation
In order to be more fully understood that embodiment, now will the most referring to the drawings, in the accompanying drawings:
Fig. 1 is the circuit diagram of basic switch adjuster circuit；
Fig. 2 shows the pwm control signal waveform used in the circuit in fig. 1；
Fig. 3 shows the inductor current waveform of the operation of the circuit for Fig. 1；
Fig. 4 is the circuit diagram of the embodiment of the circuit for sensing average inductor current；
Fig. 5 shows the operation waveform of the circuit of Fig. 4；
Fig. 6 is the circuit diagram of the embodiment of the circuit for sensing average inductor current；And
Fig. 7 shows the operation waveform of the circuit of Fig. 6.
Detailed description of the invention
Referring now to Fig. 4, the figure shows the circuit of the embodiment of circuit 100 for sensing average inductor current
Figure.In response to pwm control signal, inductor current Iind flows through inducer 126.Such as, this electric current can be by shown in Fig. 1
Converter circuit 10 generate, or use include that any other circuit of inductance element generates, variable at circuit run duration
Inductor current flows through this inductance element.
Circuit 100 includes current sensing circuit 130, and this circuit is configured for sensing inductor current Iind and defeated
Go out to indicate the electric current I of inductor current IindSensing.Current sensing circuit 130 includes sense resistor 102, this sense resistor coupling
It is connected between a terminal and the output node 128 of inducer 126.Resistor 102 has resistance value RSensing.Current sensing circuit
130 farther include trsanscondutance amplifier 104, and this trsanscondutance amplifier has and is coupled between inducer 126 and sense resistor 102
The non-inverting input of node 106 and there is anti-phase input further that be coupled to output node 128.Trsanscondutance amplifier 104
Sensing is crossed over the voltage drop of sense resistor 102 and according to below equation, this sensing voltage drop is converted into output electric current
ISensing:
ISensing=gm* (V+-V-)=gm*Iind*RSensing,
Wherein: " gm " is the transconductance value of amplifier 104.
Capacitor 134 and load 136 coupled in parallel are between output node 128 and ground nodes 116.
Circuit 100 farther includes circuit 150, and this Circuit responce is in output electric current ISensingWith pwm signal and being configured to
For generating the output signal that the average current of inducer 126 is flow through in instruction.Circuit 150 includes the first current source 152, this electric current
Source is coupled between the first terminal of supply voltage Vdd and on-off circuit 154.Such as, on-off circuit 154 can include transistor
Switch (such as n-channel MOSFET element).Second terminal of on-off circuit 154 is coupled to node 156.Circuit 150 farther includes
Second current source 158, this current source is coupled between the first terminal of reference voltage V ref and on-off circuit 160.Such as, switch
Circuit 160 can include transistor switch, such as n-channel MOSFET element.Second terminal of on-off circuit 160 is coupled to node
156.Capacitor sensor 162 is coupled between node 156 and ground nodes 116.First current source 152 is configured for generating
First electric current I1, this first electric current is equal to output electric current ISensing.Second current source 158 is configured for generating the second electric current I2,
This electric current is equal to output electric current ISensingTwice (that is, 2*ISensing).Such as, the generation of these electric currents can use as known in the art
Conventional current mirror circuit completes.Reference voltage V ref is less than supply voltage Vdd, but is greater than the ground connection at ground nodes 116
Voltage.
Circuit 150 farther includes comparator 170, and this comparator has non-inverting input and the coupling being coupled to node 156
It is connected into the anti-phase input for receiving reference voltage V ref.The function of comparator 170 be by node 156 at voltage (by sensing
Capacitor 162 stores) compare with reference voltage and compare in response to that and generate triggering signal (trig).
Circuit 150 still further comprises the 3rd current source 176, and this current source is coupled in supply voltage Vdd and intermediate node
Between 178.Resistor 180 is coupled between intermediate node 178 and ground nodes 116.Sampling keeps (S/H) circuit 184 to have
It is coupled to the input of intermediate node 178.The function of S/H circuit 184 is in response to trigger signal (trig) and electricity to input
Pressure (that is, the voltage at intermediate node 178) samples and exports that sampled voltage.Analog-digital converter (ADC) circuit 188
There is input and the digital signal output of the output being couple to S/H circuit 184.The function of adc circuit 188 is by S/H circuit
Voltage that is sampled and that keep at the output of 184 is converted into multi-bit word output signal OUT (digital), and this signal represents
Flow through the average current of inducer 126.
The timing circuit 190 being such as implemented as Digital Logical Circuits receives pwm control signal and generates clock signal
φ 1 and φ 2, these clock signals control the actuating of on-off circuit 154 and 160 respectively.
Referring additionally now to Fig. 5, the figure shows the operation waveform of circuit 150.Circuit 150 is according to middle point-measurement technique
Run.Electric current in inducer 126 has minima and maximum.Desired average current between minima and maximum it
Between centre.There is the beginning/end in each cycle 200 at pwm control signal in minimum current value.Maximum current value occurs
The end of the first stage 40 of PWM cycle.Then there is the end of the second stage 42 at PWM cycle in minimum current value.
Timing circuit 190 generates clock signal φ 1 and φ 2 from pwm control signal.In response to the first PWM cycle 200 (1)
In the beginning of first stage 40, timing circuit 190 asserts clock signal φ 1 (reference number 202) and ON switch 154.The
Then one current source 152 starts to charge capacitor sensor 162 204 from reference voltage V ref.When on the voltage on capacitor 162
When being raised on reference voltage V ref, comparator 170 changes state and triggers signal (trig) and be converted to logic low (reference number
206).The charging of capacitor sensor 162 terminates at the end of first stage 40, and timing circuit 190 goes to assert that clock is believed
Number φ 1 (reference number 208) and turn off switch 154.During the second stage 42 of the first PWM cycle 200 (1), sense capacitance
Voltage on device 162 is kept 210.In response to the beginning of the first stage 40 in the second PWM cycle 200 (2), such as, immediately
After the first PWM cycle 200 (1), timing circuit 190 asserts clock signal φ 2 (reference number 212) and ON switch 160.
Then capacitor sensor 162 is discharged 214 by the second current source 158.But, owing to discharge current I2 is the value of charging current I1
Twice (I2=2*I1), therefore discharge rate will be the twice of charge rate.Voltage on capacitor sensor 162 will correspondingly exist
Substantially midpoint (that is, in average current value) between minimum current and maximum current returns 216 to reference voltage V ref.When
When voltage on capacitor sensor 162 drops to reference voltage V ref, comparator 170 changes state and triggers signal (trig)
It is converted to logic high (reference number 218).Thus, the logic high triggering signal is asserted when flowing with average inductor current
Time point is basically identical.That triggers signal asserts that height (i.e. rising edge) causes S/H circuit 184 to the voltage at intermediate node 178
Sampling.Sampling voltage at node 178 indicates average inductor current according to below equation:
V (178)=ISensing*R(180)；
Wherein, when sampling, ISensing=Iav.Sampling voltage is converted to digital value (output signal OUT by adc circuit 188
(digital)), this value represents the average current flowing through inducer 126.Actual average current value is by by the digital value of sampling voltage
Resistance divided by resistor 180 calculates.The end of the timing circuit 190 first stage 40 in the second PWM cycle 200 (2)
Time cancel and assert clock signal φ 2 (reference number 220) and turn off switch 160.
The process for determining average inductor current can be started again in next PWM cycle 200.Substituting
Ground, can before starting again at this process the one or more PWM cycle of constrained delay 200.
Average current determines the most accurate.But, the delay when logic high of comparator 170 generation triggering signal is asserted
Cause slight offset error, as shown in reference number 222.
Referring now to Fig. 6, the figure shows the circuit of the embodiment of circuit 110 for sensing average inductor current
Figure.In response to pwm control signal, inductor current Iind flows through inducer 126.Such as, this electric current can be by such as institute in Fig. 1
The converter circuit 10 shown generates, or use includes that any other circuit of inductance element generates, can at circuit run duration
Time-dependent current flows through this inductance element.
Circuit 102 includes current sensing circuit 130, and this circuit is configured for sensing inductor current Iind and defeated
Go out to indicate the electric current I of inductor current IindSensing.Current sensing circuit 130 includes sense resistor 102, this sense resistor coupling
It is connected between a terminal and the output node 128 of inducer 126.Resistor 102 has resistance value RSensing.Current sensing circuit
130 farther include trsanscondutance amplifier 104, and this trsanscondutance amplifier has and is coupled between inducer 126 and sense resistor 102
The non-inverting input of node 106 and there is anti-phase input further that be coupled to output node 128.Trsanscondutance amplifier 104
Sensing is crossed over the voltage drop of sense resistor 102 and according to below equation, this sensing voltage drop is converted into output electric current
ISensing:
ISensing=gm* (V+-V-)=gm*Iind*RSensing,
Wherein: " gm " is the transconductance value of amplifier 104.
Capacitor 134 and load 136 coupled in parallel are between output node 128 and ground nodes 116.
Circuit 102 farther includes circuit 250, and this Circuit responce is in output electric current ISensingWith pwm signal and being configured to
For generating the output signal that the average current of inducer 126 is flow through in instruction.Circuit 250 includes the first current source 252, and this is first years old
Current source is coupled between supply voltage Vdd and the first intermediate node 254.Resistor 256 is coupled in intermediate node 254 and ground connection
Between node 116.First current source 252 is configured for generating the first electric current I1, and this first electric current is equal to output electric current
ISensing.Such as, this can use conventional current mirror circuit as known in the art to complete.Voltage at node 252 is according to following
Equation follow current I1 (ISensing):
V (254)=ISensing*R(256)。
Unity gain buffer 260 has and is coupled to the input of intermediate node 254 and how to be coupled to the second intermediate node 262
Output.First on-off circuit 264 and the first capacitor 266 are coupled in series between intermediate node 262 and ground nodes 116.Example
As, on-off circuit 264 can include transistor switch (such as n-channel MOSFET element).During the first terminal of switch 264 is connected to
Intermediate node 262 and the second terminal switched are connected to the 3rd intermediate node 268.During first pole plate of capacitor 266 is connected to
Second pole plate of intermediate node 268 and capacitor is connected to ground nodes 116.Second switch circuit 274 and the second capacitor 276
It is coupled in series between intermediate node 262 and ground nodes 116.Such as, on-off circuit 274 can include that transistor switch is (such as n
Trench MOSFET device).The first terminal of switch 274 is connected to intermediate node 262 and the second terminal of switching is connected to the
Four intermediate nodes 278.First pole plate of capacitor 276 is connected to the second pole plate of intermediate node 278 and capacitor and is connected to
Ground nodes 116.3rd on-off circuit 290 is coupled between intermediate node 268 and intermediate node 278.Such as, on-off circuit
290 can include transistor switch (such as n-channel MOSFET element).
Second unity gain buffer 292 has input and the output 294 being coupled to intermediate node 278.Sampling keeps
(S/H) circuit 184 has the input being coupled to export 294.The function of S/H circuit 184 be in response to trigger signal (trig) and
The voltage (that is, the voltage at output 294) of its input is sampled and exports that sampling voltage.Analog-digital converter
(ADC) circuit 188 has input and the digital signal output of the output being couple to S/H circuit 184.The function of adc circuit 188
Be by the output of S/H circuit 184 at voltage that is sampled and that keep be converted into multi-bit word output signal OUT (number
Word), this signal represents the average current flowing through inducer 126.
The timing circuit 298 being such as implemented as Digital Logical Circuits receives pwm control signal and generates clock signal
φ 1, φ 2 and φ 3, these clock signals control the actuating of on-off circuit 264,274 and 290 respectively.Timing circuit 298 is further
Generate and trigger signal.
Referring additionally now to Fig. 7, the figure shows the operation waveform of circuit 250.Circuit 250 is according to peak value point-measurement technique
Run.Electric current in inducer 126 has minima at minimum peak point and has maximum, peak value in maximal peak point
Point is determined by pwm signal.Desired average current centre between minimum peak point and maximal peak point.Detection with
Voltage that small leak point is corresponding with each in maximal peak point and being then averaged, the average voltage wherein obtained
Corresponding to average inductor current.
Timing circuit 298 generates clock signal φ 1, φ 2 and φ 3 from pwm control signal.In response to the first PWM cycle 200
(1) second stage 42 in, timing circuit 298 asserts clock signal φ 1 (reference number 300) and φ 2 (reference number 302) and connect
Open up pass 264 and 274.Current source 252 is crossed over resistor 256 and is applied electric current I1=ISensing, to form electricity at intermediate node 254
Pressure.This voltage is buffered and is applied to capacitor 266 and 276.Owing to electric current I1 successively decreases during second stage 42, therefore node
Voltage at 254 and the voltage consequently across capacitor 266 and 276 also successively decrease (reference number 304).Electricity at capacitor 266
Press indicated by the solid line, and the voltage at capacitor 276 is represented by dashed line.
At the end of the second stage 42 of the first PWM cycle 200 (1), timing circuit 298 is cancelled and is asserted clock signal φ 1
(reference number 306) and turn off switch 264.Capacitor 266 is now when corresponding with the minimum peak of inductor current point
Between put from node 254 and 262 disconnect.The storage 308 voltage on capacitor 266 is thus indicate that minimum inductor current.
But, timing circuit 298 continue to assert clock signal φ 2 (reference number 310) and thus switch 274 holding connect
Logical.The first stage 40 of the second PWM cycle 200 (2) starts.Current source 252 continues to apply electric current I1=I across resistor 256Sensing,
To form voltage at intermediate node 254.Voltage is buffered and is applied to capacitor 276.Owing to electric current I1 is on the first rank
It is incremented by during section 40, therefore voltage at node 254 and thus be also incremented by (reference number 312) across the voltage of capacitor 276.
At the end of the first stage 40 of the second PWM cycle 200 (2), timing circuit 298 is cancelled and is asserted clock signal φ 2
(reference number 314) and turn off switch 274.Capacitor 276 is now when corresponding with the maximal peak point of inductor current
Between put from node 254 and 262 disconnect.316 voltages on capacitor 276 are stored thus indicate that maximum during second stage 42
Inductor current.
The instruction minimum peak point of inductor current and maximal peak point has been stored at capacitor 266 and 276
Any point after voltage, timing circuit 298 asserts clock signal φ 3 (reference number 318) and ON switch 290.Shown
In embodiment, starting of this operation and next PWM cycle 200 (3) is Tong Bu, but this is example.This action is by capacitor
266 and 276 are serially connected.Electric charge is shared between these capacitors generation, and the voltage at node 278 moves to refer to
Show between the storage voltage (from capacitor 266) of minimum peak point and the storage voltage (from capacitor 276) of the maximum peak dot of instruction
Midrange.This situation is shown at reference number 320.Mid-point voltage at node 278 is thus indicate that average inductor current.
This voltage is buffered by unity gain buffer 292 and presents in output 294.
Timing circuit 298 is asserted further and is triggered signal (trig), thus causes the S/H circuit 184 electricity to exporting at 294
Pressure sampling.This triggers signal generation and occurs the voltage at node 278 to settle out it after the actuating of switch 290
After.Export the voltage of sampling at 294 and be converted into digital value (output signal OUT (digital)), this digital value table by adc circuit 188
Show the average current flowing through inducer 126.Actual average current value by by the digital value of sampling voltage divided by resistor 256
Resistance calculates.Cancel at the end of the timing circuit 298 first stage 40 in the 3rd PWM cycle 200 (3) and assert clock signal
φ 3 (reference number 322) and turn off switch 290.
The process for determining average inductor current can be started again in next PWM cycle 200.Substituting
Ground, can before starting again at this process the one or more PWM cycle of constrained delay 200.
By to the exemplary of the complete of exemplary embodiment of the present utility model and informational description and non-limit
The example of property processed provide before description.But, for those skilled in the relevant art, in view of description above, when
When reading this specification in conjunction with accompanying drawing and appended claims, various amendments and adaptation can become obvious.But, to this reality
This utility model limited such as appended claims will be still fallen within all such with the similar amendment of novel teachings
Within the scope of.
Claims (21)
1. the equipment of the average inductor current passing to load for measurement, it is characterised in that including:
Current sensing circuit, described current sensing circuit is configured for generating sensing electric current, described sensing electric current and response
The inductor current flowing through inducer in pulse-width modulation control signal is corresponding；And
Average circuit, described average circuit runs in one or more pulse width modulation cycles of described pulse-width modulation control signal
To process described sensing electric current in each stage of one or more pulse width modulation cycles, thus generate instruction and flow through described inductance
The output signal of the average current of device.
2. equipment as claimed in claim 1, it is characterised in that described inductor current have with in described pulse width modulation cycle
The maximum current that is associated of stage in one or more cycles and one or more with described pulse width modulation cycle
The minimum current that another stage in cycle is associated, described average circuit processes described sensing electric current during the one stage
To obtain the first value and to process described sensing electric current during another stage described to obtain the second value, described first is worth and institute
State the second value for generating described output signal.
3. equipment as claimed in claim 2, it is characterised in that described average circuit includes:
Capacitor, described capacitor was charged by described sensing electric current during the one stage, and described first value includes charging
Voltage, described capacitor is discharging current during another stage described, and the amplitude that described electric current has is described sensing electric current
The integral multiple of amplitude, described second value includes discharge voltage；
Resistor, described sensing electric current flows through described resistor to generate voltage；And
Sample-and-hold circuit, described sample-and-hold circuit is triggered by described discharge voltage to refer to described voltage sampling and generation
Show the described output signal of the average current flowing through described inducer.
4. equipment as claimed in claim 3, it is characterised in that described integral multiple is 2.
5. equipment as claimed in claim 3, it is characterised in that described average circuit farther includes comparison circuit, described ratio
Relatively circuit is configured for being compared with reference voltage by described discharge voltage and generating use in response to described comparison
In the triggering signal triggering described sample-and-hold circuit.
6. equipment as claimed in claim 3, it is characterised in that each pulse width modulation cycle includes first stage and second-order
Section, and wherein, the one stage is the first stage of the first pulse width modulation cycle, and wherein, and another stage described is
It is different from the first stage of the second pulse width modulation cycle of described first pulse width modulation cycle.
7. equipment as claimed in claim 3, it is characterised in that farther include analog-digital converter circuit, described analog digital conversion
Device circuit is configured for the output signal of described generation is converted into numeral output.
8. equipment as claimed in claim 2, it is characterised in that described average circuit includes:
First capacitor, described first capacitor was charged by described sensing electric current during the one stage, described first value
Including the first charging voltage；
Second capacitor, described second capacitor was charged by described sensing electric current during another stage described, described second value
Including the second charging voltage；
Electric charge shares circuit, and described electric charge is shared circuit and is configured at described first capacitor and described second capacitor
Between optionally share electric charge；And
Sample-and-hold circuit, described sample-and-hold circuit by electric charge shared trigger service with to described first capacitor and described second electricity
The share voltage of container samples and generates the described output signal that the average current of described inducer is flow through in instruction.
9. equipment as claimed in claim 8, it is characterised in that described average circuit farther includes:
First switch, described first switch was selectively activated in response to the one stage, thus to described first electricity
Condenser charge；And
Second switch, described second switch was selectively activated in response to another stage described, thus to described second electricity
Condenser charge.
10. equipment as claimed in claim 9, it is characterised in that described second switch was entered in response to the one stage
One step optionally activates.
11. equipment as claimed in claim 9, it is characterised in that described average circuit farther includes the 3rd switch, described
Three switches are selectively activated, thus described first capacitor and described second capacitor are connected in parallel to share electricity
Lotus.
12. equipment as claimed in claim 8, it is characterised in that farther include analog-digital converter circuit, described analog digital conversion
Device circuit is configured for the output signal of described generation is converted into numeral output.
13. equipment as claimed in claim 1, it is characterised in that described average circuit includes:
Resistor, described sensing electric current flows through described resistor to generate the voltage corresponding with inductor current；And
Sample-and-hold circuit, described sample-and-hold circuit be triggered in response to the described voltage corresponding with inductor current with
The average voltage generated samples and generates the described output signal that the average current of described inducer is flow through in instruction.
14. equipment as claimed in claim 13, it is characterised in that farther including analog-digital converter circuit, described modulus turns
Converter circuit is configured for the output signal of described generation is converted into numeral output.
15. equipment as claimed in claim 13, it is characterised in that farther including buffer circuit, described buffer circuit couples
To buffer described average voltage between described resistor and described sample-and-hold circuit.
16. equipment as claimed in claim 13, it is characterised in that described average circuit farther includes:
First capacitor, described first capacitor is associated with maximum inductor current with generation by the charging of described sensing electric current
First charging voltage；
Second capacitor, described second capacitor is associated with maximum inductor current with generation by the charging of described sensing electric current
Second charging voltage；And
Electric charge shares circuit, and described electric charge is shared circuit and is configured at described first capacitor and described second capacitor
Between optionally share electric charge and export described average voltage.
17. equipment as claimed in claim 16, it is characterised in that described average circuit farther includes:
First switch, described first switch was selectively activated in response to the first stage of pulse width modulation cycle, thus right
Described first capacitor charging；And
Second switch, described second switch is selectively activated in response to the second stage of described pulse width modulation cycle, from
And to described second capacitor charging.
18. equipment as claimed in claim 17, it is characterised in that described second switch was entered in response to the described first stage
One step optionally activates.
19. equipment as claimed in claim 17, it is characterised in that described average circuit farther includes the 3rd switch, described
3rd switch is selectively activated during follow-up pulse width modulation cycle, thus by described first capacitor and described second electricity
Container is connected in parallel to share electric charge.
20. equipment as claimed in claim 13, it is characterised in that described average circuit includes:
Capacitor, described capacitor was charged by described sensing electric current to generate charging during the stage of the first pulse width modulation cycle
Voltage, described capacitor is discharging current during the stage of the second pulse width modulation cycle, thus generates discharge voltage, described electricity
The amplitude that stream has is the integral multiple of the amplitude of described sensing electric current；And
Comparison circuit, described comparison circuit is configured for being compared with reference voltage by described discharge voltage and responding
The triggering signal for triggering described sample-and-hold circuit is generated in described comparison.
21. equipment as claimed in claim 20, it is characterised in that described integral multiple is 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520940660.8U CN205484499U (en) | 2015-11-23 | 2015-11-23 | A equipment for measuring transmit average inductor current of giving load |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520940660.8U CN205484499U (en) | 2015-11-23 | 2015-11-23 | A equipment for measuring transmit average inductor current of giving load |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205484499U true CN205484499U (en) | 2016-08-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520940660.8U Withdrawn - After Issue CN205484499U (en) | 2015-11-23 | 2015-11-23 | A equipment for measuring transmit average inductor current of giving load |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205484499U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771472A (en) * | 2015-11-23 | 2017-05-31 | 意法半导体研发(深圳)有限公司 | Method and apparatus for measuring the average inductor current for passing to load |
| CN107526022A (en) * | 2017-08-17 | 2017-12-29 | 京东方科技集团股份有限公司 | Shared circuit, detection circuit and detection method |
-
2015
- 2015-11-23 CN CN201520940660.8U patent/CN205484499U/en not_active Withdrawn - After Issue
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106771472A (en) * | 2015-11-23 | 2017-05-31 | 意法半导体研发(深圳)有限公司 | Method and apparatus for measuring the average inductor current for passing to load |
| CN106771472B (en) * | 2015-11-23 | 2023-09-19 | 意法半导体研发(深圳)有限公司 | Method and apparatus for measuring average inductor current delivered to a load |
| CN107526022A (en) * | 2017-08-17 | 2017-12-29 | 京东方科技集团股份有限公司 | Shared circuit, detection circuit and detection method |
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Address after: 5 / F East B501, South B502, North B503, 6th floor, block B, TCL Industrial Research Institute building, No. 006, Gaoxin South 1st Road, Nanshan District, Shenzhen City, Guangdong Province Patentee after: STMicroelectronics (Shenzhen) R&D Co.,Ltd. Address before: 4 / 5 / F, block B, Skyworth building, South District, high tech Zone, Nanshan District, Shenzhen City, Guangdong Province Patentee before: STMicroelectronics (Shenzhen) R&D Co.,Ltd. |
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Granted publication date: 20160817 Effective date of abandoning: 20230919 |