CN205452290U - Horizontal semiconductor device - Google Patents

Abstract

Horizontal semiconductor device. The utility model discloses the horizontal semiconductor device of the production that can prevent current concentration is provided with the low cost. Horizontal semiconductor device sets up on the semiconductor substrate who has the 1st interarea faced each other and the 2nd interarea, and this horizontal semiconductor device has: the drift region of the 1st conduction type, the drain region of the 1st conduction type, the base region of the 2nd conduction type, the source region of the 1st conduction type, the drain electrode, its with the drain region electricity is connected, the source electrode, its with the source region electricity is connected, and the gate electrode, it is separating the gate insulating film and is setting up in the quilt the source region with the drain region is pressing from both sides the base region top is when overlooking the inner edge length of source electrode compares the position that outer fringe length is long of drain electrode the source region with department partly at least between the source electrode has insulation layer.

Description

Lateral semiconductor devices

Technical field

This utility model relates to the lateral semiconductor devices being arranged at Semiconductor substrate.

Background technology

Patent document 1 discloses that a kind of lateral semiconductor devices, it has multiple metal level and contact disc, the plurality of metal level is arranged at the surface of active region, being provided with lateral transistor in this active region, described contact disc is respectively equipped with one for connection wire on each metal level of multiple metal levels.The area of the multiple metal levels metal level from the side close to outside connection member, to the metal level away from outside connection member, is sequentially reduced.Conventional lateral semiconductor devices makes to flow through the uniform current density of lateral transistor by adjusting the area of metal level, therefore, it is possible to prevent from occurring current convergence in lateral semiconductor devices.

[patent documentation 1]: CN101174626A

But, conventional lateral semiconductor devices need multiple metal levels each on joint dish connection wire are set.Therefore, conventional lateral semiconductor devices may cause cost to increase due to the quantity of wire rod and chip area.

Utility model content

This utility model provides the lateral semiconductor devices of a kind of generation being prevented from current convergence with low cost.

This utility model provides a kind of lateral semiconductor devices, it is arranged in the Semiconductor substrate with opposed facing 1st interarea and the 2nd interarea, this lateral semiconductor devices is characterised by, described lateral semiconductor devices has: the drift region of the 1st conductivity type, its described 1st interarea side being arranged in described Semiconductor substrate；The drain region of described 1st conductivity type, its described 1st interarea side being arranged in described drift region；The base of the 2nd conductivity type, its described 1st interarea side being arranged in described drift region；The source region of described 1st conductivity type, its described 1st interarea side being arranged in described base, and by overlook time surround described drain region in the way of arrange；Drain electrode, it electrically connects with described drain region；Source electrode, it electrically connects with described source region；And gate electrode, it is arranged at above the described base clipped by described drain region and described source region across gate insulating film, the position that the inner edge length of described source electrode is longer than the outer rim length of described drain electrode when overlooking, at least some of place between described source region and described source electrode has insulation layer.

According to this utility model, it is possible to provide the lateral semiconductor devices of a kind of generation preventing current convergence with low cost.

Accompanying drawing explanation

Fig. 1 is the top view of the structure of the semiconductor device representing embodiment of the present utility model.

Fig. 2 is the sectional view of the structure of the semiconductor device representing embodiment of the present utility model.

Fig. 3 is the sectional view of the structure of the semiconductor device representing variation of the present utility model.

Fig. 4 is the sectional view of the structure of the semiconductor device representing variation of the present utility model.

Label declaration

1: Semiconductor substrate；2: drift region；3: semiconductor region；4: drain region；5: base；6: source region；7: gate insulating film；8: dielectric film；9: insulation layer；10: the 1 interareas；11: the 2 interareas；D: drain electrode；S: source electrode；G: gate electrode.

Detailed description of the invention

Then, it is explained with reference to embodiment of the present utility model.In the record of following accompanying drawing, the label same or like to same or like part mark.It should, however, be noted that accompanying drawing is the most schematically.It addition, embodiment shown below is to illustrate the device for making the technological thought of this utility model embody or method, the embodiment of this utility model does not make the structure of component parts, configuration etc. be defined to the example below.The embodiment of this utility model can apply various change in the range of being claimed.

Fig. 1～Fig. 4 is top view and the sectional view of the structure of the lateral semiconductor devices representing embodiment of the present utility model.Fig. 2 is the a-a sectional view of Fig. 1, and Fig. 3 is the b-b sectional view of Fig. 1, and Fig. 4 is the b-b sectional view of Fig. 1.

The lateral semiconductor devices of the present embodiment is disposed on the lateral semiconductor devices of Semiconductor substrate 1, and this lateral semiconductor devices has drift region 2, drain region 4, base 5, source region 6, source electrode S, drain electrode D and gate electrode G.It addition, the lateral semiconductor devices of the present embodiment position that the inner edge length of source electrode is longer than the outer rim length of drain electrode when overlooking, there is between source region 6 and source electrode S insulation layer 9.

When overlooking, the inner edge of source electrode S and the outer rim of drain electrode D are the position that the two length of linearity is equal, and lateral semiconductor devices is constituted as shown in Figure 2.Semiconductor substrate 1 has opposed facing 1st interarea the 10 and the 2nd interarea 11.Semiconductor substrate 1 has drift region 2, semiconductor region 3, drain region 4, base 5 and source region 6.Drift region 2 is the semiconductor region of the N-shaped arranged in the way of being exposed to the 1st interarea 10 side of Semiconductor substrate 1.Semiconductor region 3 is the semiconductor region of the p-type arranged in the way of being exposed to the 2nd interarea 11 side of Semiconductor substrate 1.Drain region 4 is the semiconductor region of the N-shaped arranged in the way of the 1st interarea 10 side in being exposed to drift region 2.Base 5 is the semiconductor region of the p-type arranged in the way of the 1st interarea 10 side in being exposed to drift region 2.It addition, base 5 is between drain region 4 and source region 6.Source region 6 is the 1st interarea 10 side being exposed in base 5, and the semiconductor region of the N-shaped that the mode in encirclement drain region 4 is arranged when overlooking.

Drain electrode D is the main electrode electrically connected with drain region 4 of lateral semiconductor devices.Source electrode S is the main electrode electrically connected with base 5 and source region 6 of lateral semiconductor devices.Gate electrode G is the control electrode of lateral semiconductor devices, its across gate insulating film 7 at least provided with above the base 5 clipped by drain region 4 and source region 6.Gate insulating film 7 is at least provided with on the 1st interarea 10 of base 5.Drain electrode D, source electrode S and gate electrode G be mutually insulated across dielectric film 8.By such structure, after the voltage that gate electrode G applies regulation, lateral semiconductor devices becomes conducting state, it is possible to flow through electric current from drain electrode D to source electrode S.

During vertical view, at the position that the inner edge length that outer rim is arc-shaped, i.e. source electrode S of the inner edge of source electrode S and the drain electrode D outer rim length than drain electrode D is long, lateral semiconductor devices is constituted as shown in Figure 3.That is, lateral semiconductor devices has the insulation layer 9 formed by pn-junction, and described pn-junction is made up of base 5 and source region 6.At this position, source electrode S does not electrically connects with source region 6, but electrically connects with base 5.

By such structure, after the voltage that gate electrode G applies regulation, the electric current being intended to flow to source electrode S from drain electrode D is stoped by the pn-junction as insulation layer 9.It addition, in the manufacturing process of lateral semiconductor devices, insulation layer 9 can be readily formed by adjusting the pattern of dielectric film 8 and source electrode S.Therefore, the lateral semiconductor devices of the present embodiment can prevent current convergence with low cost in the arc sections office being susceptible to current convergence by limiting current path.

Source electrode S can also be configured to as shown in Figure 4: does not electrically connects with any one of source region 6 and base 5.By such structure, the electric current being intended to flow to source electrode S from drain electrode D is stoped by the dielectric film 8 as insulation layer 9.Therefore, it is possible to obtain action effect same as described above.

As above, by embodiment, this utility model is illustrated, it is understood that constitute the discussion of a part disclosed above and this utility model is not limited by accompanying drawing.To those skilled in the art, can obtain various alternative embodiment, embodiment and application technology from the disclosure, this is apparent from.That is, this utility model includes the various embodiments etc. do not recorded at this certainly.Therefore, technical scope of the present utility model is only determined by the specific item of utility model involved by the suitable scope being claimed obtained based on described above.

For example, it is also possible to arrange the element (diode, CMOS) beyond lateral transistor on semiconductor substrate 1.Or, during vertical view, at the position that the inner edge length of the source electrode S outer rim length than drain electrode D is long, insulation layer 9 can be set by entire surface, it is also possible to the inner edge along source electrode S arranges insulation layer 9 partly.

Claims (4)

1. a lateral semiconductor devices, it is arranged in the Semiconductor substrate with opposed facing 1st interarea and the 2nd interarea, and this lateral semiconductor devices is characterised by,

Described lateral semiconductor devices has:

The drift region of the 1st conductivity type, its described 1st interarea side being arranged in described Semiconductor substrate；

The drain region of described 1st conductivity type, its described 1st interarea side being arranged in described drift region；

The base of the 2nd conductivity type, its described 1st interarea side being arranged in described drift region；

The source region of described 1st conductivity type, its described 1st interarea side being arranged in described base, arrange in the way of surrounding described drain region in time overlooking；

Drain electrode, it electrically connects with described drain region；

Source electrode, it electrically connects with described source region；And

Gate electrode, it is arranged at above the described base clipped by described source region and described drain region across gate insulating film,

The position that the inner edge length of described source electrode is longer than the outer rim length of described drain electrode when overlooking, at least some of place between described source region and described source electrode has insulation layer.

Lateral semiconductor devices the most according to claim 1, it is characterised in that

Described insulation layer is made up of pn-junction.

Lateral semiconductor devices the most according to claim 2, it is characterised in that

Described pn-junction is made up of described base and described source region.

Lateral semiconductor devices the most according to claim 1, it is characterised in that

Described insulation layer is made up of a part for dielectric film.