CN205452269U - Stromatolite chip package structure - Google Patents
Stromatolite chip package structure Download PDFInfo
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- CN205452269U CN205452269U CN201521115945.4U CN201521115945U CN205452269U CN 205452269 U CN205452269 U CN 205452269U CN 201521115945 U CN201521115945 U CN 201521115945U CN 205452269 U CN205452269 U CN 205452269U
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- chip
- packaging structure
- stacked die
- die packaging
- component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides a stromatolite chip package structure among the stromatolite chip package structure, the active face of upper and lower two -layer chip orientation is relative, and the electrode on lower floor's chip is drawn forth through the part that reroutes arrange again in stromatolite chip package structure's surface, the electrode of upper chip through the conductive projection be electrically connected to the pad of lower floor's chip on, the rethread reroutes the surface that the part drew forth stromatolite chip package structure and arranges again, upper chip has still played the effect of bearing the support to lower floor's chip. Therefore, stromatolite chip package structure need not to use the lead frame of formulating in advance, and has the part of rerouting for packaging design has more the flexibility, and the packaging structure area is littleer, and the integrated level is higher.
Description
Technical field
This utility model relates to chip encapsulation technology field, particularly relates to a kind of Stacked Die Packaging structure.
Background technology
Chip package is to be wrapped in encapsulating compound by chip, thus semi-conducting material and external environment is separated and provide and the technique of electrical connection of external circuit.The package assembling formed after chip package process i.e. can be at the chip product of market sale.
Along with people's raising to the integrated level demand of integrated circuit, polylith integrated chip is encapsulated in encapsulating compound and becomes the study hotspot of present stage.Existing a kind of common Stacked Die Packaging structure generally includes the lead frame pre-established, the electrode in layers of chips up and down in Stacked Die Packaging structure is all electrically connected with the pin of lead frame by conductive projection or bonding wire, and then plastic-sealed body is encapsulated chip.
Above-mentioned Stacked Die Packaging structure needs to use the lead frame that pre-establishes to carry chip and to draw the electrode of chip, and the electrode on the chip of upper strata is typically only capable to electrically connect with the pin being positioned at around lower layer chip.Therefore, the package area of this Stacked Die Packaging structure is big, and integrated level is low, and the flexibility ratio of encapsulation design is low, limits the motility of the layout of electrode on chip.
Expect to study the Stacked Die Packaging structure made new advances, to improve integrated level and the motility of encapsulation of integrated circuit further.
Utility model content
In view of this, this utility model provides a kind of Stacked Die Packaging structure, the motility of integrated level Yu encapsulation to provide integrated circuit.
A kind of Stacked Die Packaging structure, including:
First chip, the active face of described first chip is provided with multiple pad,
Second chip, the active face of described second chip is towards the active face of described first chip, and the electrode of described second chip is electrically connected with at least part of described pad by conductive projection,
Reroute parts, described rewiring parts electrically connect with at least part of described pad, and partial denudation is on the surface of described Stacked Die Packaging structure, with by the electrode of described first chip and/or the second chip in the surface rearrangement of described Stacked Die Packaging structure
Plastic-sealed body, described plastic-sealed body is encapsulated by described first chip, the second chip, conductive projection and reroutes the assembly that parts are constituted.
Preferably, described rewiring parts include first component, second component and the 3rd parts,
One end of described first component electrically connects with described pad, and the other end extends to described second component to first direction,
Described second component extends to second direction, using the rewiring layer as described Stacked Die Packaging structure so that the electrode of described first chip and/or the second chip by described rewiring parts in the surface rearrangement of described Stacked Die Packaging structure,
One end of described 3rd parts electrically connects with described second component, and the other end extends to third direction,
Wherein, described second direction is vertical with described first direction, and described third direction is parallel with described first direction.
Preferably, described third direction is opposite to the first direction.
Preferably, described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface, and described second surface is the surface of described Stacked Die Packaging structure,
Described first component is extended to described first surface by described pad, and described second component extends on the first surface, and described 3rd parts are extended to described second surface by described first surface,
Described second plastic-sealed body covers on described second component.
Preferably, described third direction is identical with described first direction.
Preferably, described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface,
Described first component is extended to described first surface by described pad, described second component extends on the first surface, described second plastic-sealed body covers on described second component, described 3rd parts are extended to the upper surface of described second plastic-sealed body by described second component, and described upper surface is the surface of described Stacked Die Packaging.
Preferably, described first component is one-body molded with described second component.
Preferably, the described pad of part and the device electric insulation in described first chip.
Preferably, the surface of described Stacked Die Packaging structure being additionally provided with the weld layer electrically connected with described rewiring parts or soldered ball, Stacked Die Packaging structure is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball.
Preferably, described Stacked Die Packaging structure also includes insulating barrier or the metal conducting layer being positioned at the back side of described first chip, and described insulating barrier or metal conducting layer are exposed on described second surface.
Therefore, according in Stacked Die Packaging structure of the present utility model, the active face of layers of chips is towards relatively up and down, electrode in lower layer chip is by rerouting the surface rearrangement of the described Stacked Die Packaging structure that parts are drawn, the electrode of upper strata chip is by the pad being electrically connected to lower layer chip of conductive projection, be drawn out to the surface rearrangement of Stacked Die Packaging structure again by rerouting parts, upper strata chip also acts the effect that carrying supports for lower layer chip.Therefore, the lead frame that described Stacked Die Packaging structure pre-establishes without use, and there are rewiring parts so that encapsulation designs more motility, and encapsulating structure area is less, and integrated level is higher.
Accompanying drawing explanation
By description to this utility model embodiment referring to the drawings, of the present utility model above-mentioned and other objects, features and advantages will be apparent from, in the accompanying drawings:
Fig. 1 is the profile of the Stacked Die Packaging structure according to this utility model embodiment one；
Fig. 2 is the profile of the Stacked Die Packaging structure according to this utility model embodiment two.
Detailed description of the invention
It is more fully described this utility model hereinafter with reference to accompanying drawing.In various figures, identical ingredient uses similar reference to represent.For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.Furthermore, it is possible to not shown part known to some.For brevity, the structure that can obtain after several steps described in the width figure.Describe hereinafter the specific details of many of the present utility model, the structure of the most each ingredient, material, size, process technique and technology, in order to be more clearly understood that this utility model.But the most as the skilled person will understand, this utility model can not be realized according to these specific details.
Embodiment one
Fig. 1 is the profile of the Stacked Die Packaging structure according to this utility model embodiment one.
With reference to shown in Fig. 1, Stacked Die Packaging structure 01 mainly includes chip 11, chip 21, reroutes parts 31 and plastic-sealed body 41.
Wherein, chip 11 all includes relative active face and the back side with chip 21, and chip 11 and chip 21 all include the device made, such as active devices such as diode, MOS memory (MOSFET), insulated gate bipolar transistors (IGBT).Active device in described usual chip includes each active area of being formed in chip and exposed pad on the active face of chip, such pad is the electrode pad of active device in chip, the input and output terminal of electrode or chip can also be directly becoming, the electrode pad that at least part of pad is chip 11 being such as positioned in the multiple pads 111 on chip 11 active face, and the electrode pad on chip 21 is not drawn in FIG.In addition the part pad in pad 111 can also be virtual pad, and i.e. with the pad of the device phase electric insulation in chip 11, virtual pad, in Stacked Die Packaging structure 01, is mainly used in drawing the electrode on chip 21.
The active face of chip 21 is towards the active face of chip 11, and the electrode (electrode pad) on chip 21 is electrically connected with the part in multiple pads 111 by conductive projection 211, thus realize the electrical connection in Stacked Die Packaging inside configuration of the electrode on chip 21 and the electrode on chip 11, and electrode on chip 21 is made to be drawn out to the position at pad 111 place.
Rerouting parts 31 to electrically connect with at least part of pad 111, and partial denudation is on the surface of Stacked Die Packaging structure 01, thus realization is by the rearrangement in Stacked Die Packaging structure 01 of the electrode on chip 11 and chip 21.Therefore, chip 11 can be in the optional position rearrangement on Stacked Die Packaging structure 01 surface with the electrode on chip 21, and it is not limited to arrangement around only above chip 11 and chip 21 stacked structure, in the case of identical package area, allow to arrange more electrode on chip 11 and chip 21, effectively raise the integrated level of encapsulating structure.
As it is shown in figure 1, reroute parts 31 to include first component 311, second component 312 and the 3rd parts 313.One end of first component 311 electrically connects with pad 111, the other end extends at second component 312 to first direction, second component 312 extends to second direction, using the rewiring layer as Stacked Die Packaging structure 01 so that the electrode of described chip 11 and/or chip 21 is by rerouting the parts 31 surface rearrangement in Stacked Die Packaging structure 01.One end of 3rd parts 313 electrically connects with second component 312, and the other end extends to third direction.Wherein, described second direction is vertical with described first direction, and described third direction is parallel with described first direction, and direction is parallel includes that direction is identical or contrary, and the most in the present embodiment, third direction is contrary with first direction.First component 311 can be one-body molded with second component 312, one of forming method of the two can be: first form opening on the surface of plastic-sealed body 41, described opening extends at pad 111, and then the surface at opening with plastic-sealed body covers conductive layer, last patterned conductive layer.First component 311 and second component 312 can be copper product and be formed, and the 3rd parts 313 can also select the conductive material identical with first component 311 to be formed.
Plastic-sealed body 41 is encapsulated chip 11, chip 21, conductive projection 211 and reroutes parts 21, to protect chip 11 to be difficult to damaged with chip 21.It is encapsulated the meaning referring to not exclusively encapsulate, the most in this application, the exposed surface at plastic-sealed body 41 of parts of rewiring parts 31, and the surface that this surface is Stacked Die Packaging structure 01.
In the present embodiment, plastic-sealed body 41 includes the first plastic-sealed body 411 and the second plastic-sealed body 412.First plastic-sealed body 411 covers on chip 11 and chip 21, and there is relative first surface and second surface, first plastic-sealed body 411 second surface is the surface of Stacked Die Packaging structure 01, i.e. reroutes parts 31 exposed on the second surface of the first plastic-sealed body 411.First component 311 is extended to the first surface of the first encapsulated member 411 by pad 111, second component 312 extends on the first surface of the first encapsulated member 411, and the 3rd parts 313 are extended to the second surface of the first plastic-sealed body 411 by the first surface of the first plastic-sealed body 411.Additionally, the second plastic-sealed body 412 covers on second component on 312, to prevent it from being affected by external environment.
Additionally, be additionally provided with on the surface of Stacked Die Packaging structure 01 and reroute weld layer or the soldered ball (not shown) that parts 31 electrically connect, Stacked Die Packaging structure 01 is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball.The most in the present embodiment, described weld layer or soldered ball can be formed on exposed the 3rd parts 313 on the second surface of the first plastic-sealed body 412.
When being connected on printed circuit board (PCB) use due to some packaged chip, remainder in addition to pin needs have good insulating properties with printed circuit board (PCB), and require to reduce to the thermal diffusivity of chip, therefore, in Stacked Die Packaging structure 01, the back side of chip 11 can also arrange a layer insulating (being not drawn in Fig. 1), the exposed surface in Stacked Die Packaging structure 01 of described insulating barrier, namely on the second surface of the second plastic-sealed body 412.And another chip is when being connected on printed circuit board (PCB) use, it is necessary to ensure that chip has extraordinary thermal diffusivity, therefore the back side of the chip 11 in Stacked Die Packaging structure 01 can also form metal conducting layer (being not drawn in Fig. 1), the exposed surface in Stacked Die Packaging structure 01 of described metal conducting layer, namely on the second surface of the second plastic-sealed body 412.
Embodiment two
Fig. 2 is the profile of the Stacked Die Packaging structure according to this utility model embodiment two.
With reference to shown in Fig. 2, Stacked Die Packaging structure 02 includes chip 12, chip 22, reroutes parts 32 and plastic-sealed body 42.
Chip 12, chip 22 are identical with fact Example one, and the device on the active face of chip 22 is electrically connected with the pad 121 on the active face of chip 12 by conductive projection 221.
In the present embodiment, reroute parts 32 and the most also include first component 321, second component the 322, the 3rd parts 323.One end of first component 321 electrically connects with pad 121, the other end extends at second component 322 to first direction, second component 322 extends to second direction, using the rewiring layer as Stacked Die Packaging structure 01 so that the electrode of described chip 12 and/or chip 22 is by rerouting the parts 32 surface rearrangement in Stacked Die Packaging structure 02.One end of 3rd parts 323 electrically connects with second component 322, and the other end extends to third direction.Wherein, described second direction is vertical with described first direction, and third direction is contrary with first direction.
Identical with embodiment one, plastic-sealed body 42 is also made up of two parts, the respectively first plastic-sealed body 421 and the second plastic-sealed body 422.First plastic-sealed body 421 covers on chip 12 and chip 22, and there is relative first surface and second surface, first component 321 is extended to the first surface of the first plastic-sealed body 421 by pad 121, second component 322 extends on the first surface of the first plastic-sealed body 421, second plastic-sealed body 422 covers on second component 322,3rd parts 323 are extended to the upper surface of the second plastic-sealed body 422 by second component 322, the surface that upper surface is Stacked Die Packaging 02 of the second plastic-sealed body 422.
Stacked Die Packaging structure 02 and Stacked Die Packaging structure 01 are in addition to rerouting parts and there is some differences, and remaining is the most identical, no longer illustrates at this.
Therefore, according in Stacked Die Packaging structure of the present utility model, the active face of layers of chips is towards relatively up and down, electrode in lower layer chip is by rerouting the surface rearrangement of the described Stacked Die Packaging structure that parts are drawn, the electrode of upper strata chip is by the pad being electrically connected to lower layer chip of conductive projection, be drawn out to the surface rearrangement of Stacked Die Packaging structure again by rerouting parts, upper strata chip also acts the effect that carrying supports for lower layer chip.Therefore, the lead frame that described Stacked Die Packaging structure pre-establishes without use, and there are rewiring parts so that encapsulation designs more motility, and encapsulating structure area is less, and integrated level is higher.
According to embodiment of the present utility model as described above, these embodiments do not have all of details of detailed descriptionthe, are not intended to the specific embodiment that this utility model is only described yet.Obviously, as described above, can make many modifications and variations.These embodiments are chosen and specifically described to this specification, is to preferably explain principle of the present utility model and actual application, so that skilled artisan can utilize this utility model and the amendment on the basis of this utility model to use well.This utility model is only limited by claims and four corner thereof and equivalent.
Claims (10)
1. a Stacked Die Packaging structure, it is characterised in that including:
First chip, the active face of described first chip is provided with multiple pad,
Second chip, the active face of described second chip is towards the active face of described first chip, and the electrode of described second chip is electrically connected with at least part of described pad by conductive projection,
Reroute parts, described rewiring parts electrically connect with at least part of described pad, and partial denudation is on the surface of described Stacked Die Packaging structure, with by the electrode of described first chip and/or the second chip in the surface rearrangement of described Stacked Die Packaging structure
Plastic-sealed body, described plastic-sealed body is encapsulated by described first chip, the second chip, conductive projection and reroutes the assembly that parts are constituted.
Stacked Die Packaging structure the most according to claim 1, it is characterised in that described rewiring parts include first component, second component and the 3rd parts,
One end of described first component electrically connects with described pad, and the other end extends to described second component to first direction,
Described second component extends to second direction, using the rewiring layer as described Stacked Die Packaging structure so that the electrode of described first chip and/or the second chip by described rewiring parts in the surface rearrangement of described Stacked Die Packaging structure,
One end of described 3rd parts electrically connects with described second component, and the other end extends to third direction,
Wherein, described second direction is vertical with described first direction, and described third direction is parallel with described first direction.
Stacked Die Packaging structure the most according to claim 2, it is characterised in that described third direction is opposite to the first direction.
Stacked Die Packaging structure the most according to claim 3, it is characterised in that described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface, and described second surface is the surface of described Stacked Die Packaging structure,
Described first component is extended to described first surface by described pad, and described second component extends on the first surface, and described 3rd parts are extended to described second surface by described first surface,
Described second plastic-sealed body covers on described second component.
Stacked Die Packaging structure the most according to claim 2, it is characterised in that described third direction is identical with described first direction.
Stacked Die Packaging structure the most according to claim 5, it is characterised in that described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface,
Described first component is extended to described first surface by described pad, described second component extends on the first surface, described second plastic-sealed body covers on described second component, described 3rd parts are extended to the upper surface of described second plastic-sealed body by described second component, and described upper surface is the surface of described Stacked Die Packaging.
Stacked Die Packaging structure the most according to claim 2, it is characterised in that described first component is one-body molded with described second component.
Stacked Die Packaging structure the most according to claim 1, it is characterised in that the described pad of part and the device electric insulation in described first chip.
Stacked Die Packaging structure the most as claimed in any of claims 1 to 8, it is characterized in that, being additionally provided with the weld layer electrically connected with described rewiring parts or soldered ball on the surface of described Stacked Die Packaging structure, Stacked Die Packaging structure is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball.
10. according to the Stacked Die Packaging structure described in claim 4 or 6, it is characterised in that also including insulating barrier or the metal conducting layer being positioned at the back side of described first chip, described insulating barrier or metal conducting layer are exposed on described second surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521115945.4U CN205452269U (en) | 2015-12-24 | 2015-12-24 | Stromatolite chip package structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521115945.4U CN205452269U (en) | 2015-12-24 | 2015-12-24 | Stromatolite chip package structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205452269U true CN205452269U (en) | 2016-08-10 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521115945.4U Active CN205452269U (en) | 2015-12-24 | 2015-12-24 | Stromatolite chip package structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205452269U (en) |
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2015
- 2015-12-24 CN CN201521115945.4U patent/CN205452269U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180201 Address after: 230000 room 208, A2 building, No. 800 Innovation Industrial Park, No. 800, Wangjiang West Road, Anhui high tech Zone Patentee after: Hefei silicon microelectronics technology Co., Ltd. Address before: Room 190, room H2, two, innovation industrial park, No. 2800, new avenue of innovation, Hefei high tech Zone, Anhui Patentee before: HEFEI ZUAN INVESTMENT PARTNERSHIP ENTERPRISE |
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| TR01 | Transfer of patent right |