CN205282470U - Stromatolite chip package structure - Google Patents
Stromatolite chip package structure Download PDFInfo
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- CN205282470U CN205282470U CN201521115977.4U CN201521115977U CN205282470U CN 205282470 U CN205282470 U CN 205282470U CN 201521115977 U CN201521115977 U CN 201521115977U CN 205282470 U CN205282470 U CN 205282470U
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73259—Bump and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model provides an among the stromatolite chip package structure among the stromatolite chip package structure, the active face of upper and lower two -layer chip orientation is relative, and the electrode on lower floor's chip is drawn forth through the electrically conductive passageway of third arranging in stromatolite chip package structure's surface, perhaps draws forth through the electrically conductive passageway of first electrically conductive passageway and second stromatolite chip package structure's surface, the electrode of upper chip through the conductive projection be electrically connected to the pad of lower floor's chip on to with some electric connection of lower floor's chip, and the accessible the electrically conductive passageway of third perhaps first electrically conductive passageway with the electrically conductive passageway of second is drawn forth stromatolite chip package structure's surface, upper chip has still played the effect of bearing the support to lower floor's chip. Therefore, stromatolite chip package structure need not to use the lead frame of formulating in advance, and has the part of rerouting for the encapsulation design has more the flexibility, and the packaging structure area is littleer, and the integrated level is higher.
Description
Technical field
This utility model relates to chip encapsulation technology field, particularly relates to a kind of Stacked Die Packaging structure.
Background technology
Chip package is to be wrapped in encapsulating compound by chip, thus semi-conducting material and external environment being separated and providing and the technique of electrical connection of external circuit. The package assembling being subsequently formed at chip package process namely can at the chip product of market sale.
Along with people's raising to the integrated level demand of integrated circuit, being encapsulated in encapsulating compound by polylith integrated chip becomes the study hotspot of present stage. Existing a kind of common Stacked Die Packaging structure generally includes the lead frame pre-established, the electrode in layers of chips up and down in Stacked Die Packaging structure electrically connects with the pin of lead frame each through conductive projection or bonding wire, and then plastic-sealed body is encapsulated chip.
Above-mentioned Stacked Die Packaging structure needs to use the lead frame pre-established to carry chip and to draw the electrode of chip, and the electrode on the chip of upper strata is typically only capable to electrically connect with the pin being positioned at around lower layer chip. Therefore, the package area of this Stacked Die Packaging structure is big, and integrated level is low, and the flexibility ratio of encapsulation design is low, limits the motility of the layout of electrode on chip.
Expect to study the Stacked Die Packaging structure made new advances, the motility of integrated level and encapsulation to improve integrated circuit further.
Utility model content
In view of this, this utility model provides a kind of Stacked Die Packaging structure, the agile kernel model of integrated level and encapsulation to improve integrated circuit.
A kind of Stacked Die Packaging structure, it is characterised in that including:
First chip, the active face of described first chip is provided with multiple pad,
Second chip, the active face of described second chip towards the active face of described first chip,
First conductive channel, is extended to the device in described second chip by the back side of described second chip or extends to the active face place of described second chip, and the back side of described second chip is relative with the active face of described second chip,
First conductive channel at device in described second chip or the active face place that extends to described second chip is electrically connected with the described pad of part by conductive projection,
Second conductive channel, described second conductive channel electrically connects with described first conductive channel, and partial denudation is to the surface of described Stacked Die Packaging structure, so that the partial electrode of described first chip and/or the second chip is arranged to the surface of described Stacked Die Packaging structure
3rd conductive channel, described 3rd conductive channel electrically connects with the described pad of part, and partial denudation is to the surface of described Stacked Die Packaging structure, so that the partial electrode of described first chip and/or the second chip is arranged to the surface of described Stacked Die Packaging structure
Plastic-sealed body, described plastic-sealed body is encapsulated the assembly being made up of described first chip, the second chip, conductive projection, the second conductive channel and the 3rd conductive channel.
Preferably, described first conductive channel includes conductive hole and the conductive material being filled in conductive hole.
Preferably, extending to the solder side that first conductive channel at the active face place of described second chip also includes electrically connecting with described conductive hole, described solder side is exposed on the active face of described second chip, and electrically connects with described conductive projection.
Preferably, described second conductive channel includes first component, second component and the 3rd parts,
One end of described first component electrically connects with described first conductive channel, and the other end extends to described second component towards first direction,
Described second component extends in a second direction, using the rewiring layer as described Stacked Die Packaging structure, partial electrode on described first chip and/or the second chip is arranged on the surface of described Stacked Die Packaging structure again by described second conductive channel
One end of described 3rd parts electrically connects with described second component, and the other end extends to the surface of described Stacked Die Packaging structure towards described first direction,
Described first direction is vertical with described second direction.
Preferably, described 3rd conductive channel includes Part I, Part II and Part III,
One end of described Part I electrically connects with described pad, and the other end extends to described second component towards described first direction,
Described Part II extends in this second direction, using the rewiring layer as described Stacked Die Packaging structure, partial electrode on described first chip and/or the second chip is arranged on the surface of described Stacked Die Packaging structure again by described 3rd conductive channel
One end of described Part III electrically connects with described Part II, and the other end extends to the surface of described Stacked Die Packaging structure towards described first direction.
Preferably, described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface, and described second plastic-sealed body covers on the first surface,
Described first component is extended to described first surface place by described first conductive channel, and described Part I is extended to described first surface place by described pad,
Described second component and described Part II all extend on the first surface, and are all covered by described second plastic-sealed body,
Described 3rd parts are extended to the upper surface of described second plastic-sealed body by described second component, and described Part III is extended to described upper surface by described Part II, and described upper surface is the surface of described Stacked Die Packaging structure.
Preferably, described first component is one-body molded with second component, and described Part I is one-body molded with described Part II,
The formation material of described first component, second component, Part I and Part II is identical.
Preferably, described 3rd parts are identical with the formation material of Part III.
Preferably, described Stacked Die Packaging structure also includes the insulating barrier or the metal conducting layer that are positioned at the back side of described first chip, and described insulating barrier or metal conducting layer are exposed described.
Preferably, being additionally provided with the weld layer or soldered ball that electrically connect with described second conductive channel and the 3rd conductive channel on the surface of described Stacked Die Packaging structure, Stacked Die Packaging structure is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball.
Therefore, according in Stacked Die Packaging structure of the present utility model, the active face of upper and lower layers of chips is towards relatively, electrode in lower layer chip is drawn out to the surface arrangement of described Stacked Die Packaging structure by the 3rd conductive channel, or the surface of described Stacked Die Packaging structure it is drawn out to by the first conductive channel and the second conductive channel, the electrode of upper strata chip is by the pad being electrically connected to lower layer chip of conductive projection, electrically connect with the partial electrode with lower layer chip, and the surface of described Stacked Die Packaging structure can be drawn out to by described 3rd conductive channel or described first conductive channel and described second conductive channel, lower layer chip is also acted the effect that carrying supports by upper strata chip. therefore, the lead frame that described Stacked Die Packaging structure pre-establishes without use, and there are rewiring parts so that encapsulation designs more motility, and encapsulating structure area is less, and integrated level is higher.
Accompanying drawing explanation
By referring to the accompanying drawing description to this utility model embodiment, of the present utility model above-mentioned and other purposes, feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 is the Stacked Die Packaging structural representation according to this utility model embodiment.
Detailed description of the invention
It is more fully described this utility model hereinafter with reference to accompanying drawing. In various figures, identical ingredient adopts similar accompanying drawing labelling to represent. For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale. Furthermore, it is possible to some known part not shown. For brevity, it is possible in the structure obtained after several steps described in a width figure. Describe hereinafter many specific details of the present utility model, for instance the structure of each ingredient, material, size, process technique and technology, in order to be more clearly understood that this utility model. But just as the skilled person will understand, it is possible to do not realize this utility model according to these specific details.
Fig. 1 is the Stacked Die Packaging structural representation according to this utility model embodiment.
With reference to shown in Fig. 1, Stacked Die Packaging structure 01 specifically includes that chip 11, chip the 21, first conductive channel the 31, second conductive channel the 41, the 3rd conductive channel 51 and plastic-sealed body 61.
Wherein, chip 11 all includes relative active face and the back side with chip 21, and chip 11 and chip 21 all include the device made, such as active devices such as diode, MOS memory (MOSFET), insulated gate bipolar transistors (IGBT). Each active area that active device in described usual chip includes being formed in chip and exposed pad on the active face of chip, such pad is the electrode pad of active device in chip, the input and output terminal of electrode or chip can also be directly becoming, the electrode pad that at least part of pad is chip 11 of the multiple pads 111 being such as arranged on chip 11 active face, and the electrode pad on chip 21 is not drawn in FIG. In addition the part pad in pad 111 can also be virtual pad, namely with the pad of the device phase electric insulation in chip 11, virtual pad is in Stacked Die Packaging structure 01, the electrode being mainly used in drawing on chip 21, to pad 111, is then drawn out to the surface of Stacked Die Packaging structure 01 again through the 3rd conductive channel and again arranges.
In Stacked Die Packaging structure 01, the active face of chip 21 is towards the active face of chip 11, and is provided with the first conductive channel 31 in chip 21. first conductive channel 31 is extended to the device in chip 21 by the back side of chip 21 or extends to the active face place of chip 21. first conductive channel 31 of device in chip 21 or the active face that extended to chip 21 by the back side of chip 21 is electrically connected with part pad 111 by conductive projection 211, thus so that the partial electrode on chip 21 is electrically connected in the inside of Stacked Die Packaging structure 01 with the partial electrode on chip 11, and make the partial electrode on chip 21 guide on pad 111, the surface arrangement of Stacked Die Packaging structure 01 is guided to eventually through the 3rd conductive channel 51, simultaneously the electrode on chip 11 passes through the first conductive channel 31 also by conductive projection 211 and the second conductive channel 41 is guided to the surface of Stacked Die Packaging structure 01 and arranged after electrically connect with the electrode on chip 21. additionally, the back side that the electrode on chip 11 is also by conductive projection 11, by chip 21 extends to the first conductive channel 31 of the active face of chip 21 and the second conductive trace 41 guides to the surface arrangement of Stacked Die Packaging structure 01.
The first conductive channel 31 being extended to the device in chip 21 by chip 21 back side includes conductive hole and the conductive material (specifically not drawing in Fig. 1) being filled in conductive hole. One of its forming method can be: carries out perforate process at the back side of chip and forms the conductive hole extending to device place in chip 21, then filled conductive material in conductive hole again. Wherein, conductive hole may extend to the electrode place of device in chip 21, to electrically connect with the device in chip 21. In addition, first conductive channel 31 of active face of chip 21 is extended to except including above-mentioned conductive hole and being arranged in the material of conductive hole by the back side of chip 21, also can farther include to be positioned at the solder side electrically connected below described conductive hole and with described conductive hole, described solder side is exposed on the active face of chip 21, and electrically connects with conductive projection 211.
The second above-mentioned conductive channel 41 is positioned on the back side of chip 21, and electrically connect with the first conductive channel 31, and second conductive channel 41 partial denudation on the surface of Stacked Die Packaging structure 01, with the electrode on chip 11 and/or chip 21 is drawn out to Stacked Die Packaging structure 01 surface arrangement.
In the present embodiment, the second conductive channel 41 includes first component 411, second component 412 and the 3rd parts 413, and one end of first component 411 electrically connects with the first conductive channel 31, and the other end extends to the 2nd 412 towards first direction. Second component 412 extends in a second direction, using the rewiring layer as Stacked Die Packaging structure 01 so that arrange again in the surface that chip 11 and/or the partial electrode on chip 21 state Stacked Die Packaging structure 01 by the second conductive channel 41. One end of 3rd parts 413 electrically connects with second component 412, and the other end extends to the surface of Stacked Die Packaging structure 01 towards described first direction. Wherein, described first direction is vertical with described second direction.
The 3rd above-mentioned conductive channel 51 electrically connects with part pad 111, and partial denudation is to the surface of Stacked Die Packaging structure 01, arranges with the surface by the partial electrode of chip 11 and/or chip 21 arrangement to described Stacked Die Packaging structure.
3rd conductive channel 51 includes Part I 511, Part II 512 and Part III 513. One end of Part I 511 electrically connects with pad 111, and the other end extends to second component 512 towards first direction. Part II 512 extends in this second direction, using the rewiring layer as Stacked Die Packaging structure 01 so that chip 11 and/or the partial electrode on chip 21 are arranged on the surface of Stacked Die Packaging structure 01 again by the 3rd conductive channel 51. One end of Part III 513 electrically connects with Part II 512, and the other end extends to the surface of Stacked Die Packaging structure 01 towards described first direction.
Due in Stacked Die Packaging structure 01, second conductive channel 41 and the 3rd conductive channel 51 all have rewiring layer, thus the partial electrode on chip 11 and/or chip 21 can be arranged on the surface of Stacked Die Packaging structure 01 again by the 3rd conductive channel 51, therefore, chip 11 can be arranged in the optional position on Stacked Die Packaging structure 01 surface again with the electrode on chip 21, and it is not limited to arrangement around only above chip 11 and chip 21 stacked structure, in identical package area situation, allow chip 11 and chip 21 arrange more electrode, effectively raise the integrated level of encapsulating structure.
Plastic-sealed body 61 is encapsulated the assembly being made up of chip 11, chip 21, conductive projection the 211, second conductive channel 41 and the 3rd conductive channel 51, to protect described assembly, it is to avoid it is damaged. Wherein, it is encapsulated and refers to incomplete encapsulating, namely the partial denudation in described assembly is on plastic-sealed body 61 surface, for instance a surface of plastic-sealed body 61 is using the surface as Stacked Die Packaging structure, and the partial denudation of the second conductive channel 41 and the 3rd conductive channel 51 is on plastic-sealed body 61 surface.
As it is shown in figure 1, plastic-sealed body 61 can include the first plastic-sealed body 611 and the second plastic-sealed body 612. First plastic-sealed body 611 covers on chip 11 and chip 21, and has relative first surface and second surface, and the second plastic-sealed body 612 covers on the first surface of the first plastic-sealed body 611. First component 411 is extended to the first surface place of the first plastic-sealed body 611 by the first conductive channel 31, and Part I 611 is extended to the first surface place of the first plastic-sealed body 611 by pad 111. And second component 412 and Part II 512 all extend on the first surface of the first plastic-sealed body 611, and all covered by the second plastic-sealed body 611. 3rd parts 413 are extended to the upper surface of the second plastic-sealed body 612 by second component 412, and Part III 513 is extended to the upper surface of the second plastic-sealed body 612 by Part II 512. Wherein, the upper surface of 612 is the surface of 01 Stacked Die Packaging structure.
In the present embodiment, first component 411 is one-body molded with second component 412, and Part I 511 is also one-body molded with Part II 512. Additionally, the formation material of first component 411, second component 412, Part I 511 and Part II 512 is identical, chip 11 can be reduced and draw conductive channel and parasitic capacitance on path with the electrode on chip 21, improve the reliability of encapsulation. In order to improve the reliability of encapsulation further, the formation material of the 3rd parts 413 and Part III 513 also can be identical.
When being connected to use on printed circuit board (PCB) due to some packaged chip, the remainder except pin needs the other parts with printed circuit board (PCB) to need have good insulating properties, and requires to reduce to the thermal diffusivity of chip. Therefore to guarantee the cause specific at the back side of chip 21 and the insulating properties of other parts or other side, in Stacked Die Packaging structure 01, the back side of chip 11 can also arrange a layer insulating (being not drawn in Fig. 1), the exposed surface in Stacked Die Packaging structure 01 of described insulating barrier, namely on the second surface of the second plastic-sealed body 412. And another chip is when being connected to use on printed circuit board (PCB), it is necessary to ensure that chip has extraordinary thermal diffusivity, therefore the back side of the chip 11 in Stacked Die Packaging structure 01 can also form metal conducting layer (being not drawn in Fig. 1), on the second surface of naked second plastic-sealed body 412 of described metal conducting layer.
In addition, being additionally provided with on the surface of Stacked Die Packaging structure 01 and reroute parts the second conductive channel 41 and weld layer that the 3rd conductive channel 51 electrically connects or soldered ball (not shown), Stacked Die Packaging structure 01 is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball. Such as in the present embodiment, it is possible on second conductive channel 41 and the 3rd conductive channel 51 of the exposed upper surface at the second plastic-sealed body 612, form described weld layer or soldered ball.
Therefore, according in Stacked Die Packaging structure of the present utility model, the active face of upper and lower layers of chips is towards relatively, electrode in lower layer chip is drawn out to the surface arrangement of described Stacked Die Packaging structure by the 3rd conductive channel, or the surface of described Stacked Die Packaging structure it is drawn out to by the first conductive channel and the second conductive channel, the electrode of upper strata chip is by the pad being electrically connected to lower layer chip of conductive projection, electrically connect with the partial electrode with lower layer chip, and the surface of described Stacked Die Packaging structure can be drawn out to by described 3rd conductive channel or described first conductive channel and described second conductive channel, lower layer chip is also acted the effect that carrying supports by upper strata chip. therefore, the lead frame that described Stacked Die Packaging structure pre-establishes without use, and there are rewiring parts so that encapsulation designs more motility, and encapsulating structure area is less, and integrated level is higher.
According to embodiment of the present utility model as described above, these embodiments do not have all of details of detailed descriptionthe, are not intended to the specific embodiment that this utility model is only described yet. Obviously, as described above, can make many modifications and variations. These embodiments are chosen and specifically described to this specification, is to explain principle of the present utility model and practical application better, so that skilled artisan can utilize this utility model and the amendment on this utility model basis to use well. This utility model is limited only by the restriction of claims and four corner thereof and equivalent.
Claims (10)
1. a Stacked Die Packaging structure, it is characterised in that including:
First chip, the active face of described first chip is provided with multiple pad,
Second chip, the active face of described second chip towards the active face of described first chip,
First conductive channel, is extended to the device in described second chip by the back side of described second chip or extends to the active face place of described second chip, and the back side of described second chip is relative with the active face of described second chip,
First conductive channel at device in described second chip or the active face place that extends to described second chip is electrically connected with the described pad of part by conductive projection,
Second conductive channel, described second conductive channel electrically connects with described first conductive channel, and partial denudation is to the surface of described Stacked Die Packaging structure, so that the partial electrode of described first chip and/or the second chip is arranged to the surface of described Stacked Die Packaging structure
3rd conductive channel, described 3rd conductive channel electrically connects with the described pad of part, and partial denudation is to the surface of described Stacked Die Packaging structure, so that the partial electrode of described first chip and/or the second chip is arranged to the surface of described Stacked Die Packaging structure
Plastic-sealed body, described plastic-sealed body is encapsulated the assembly being made up of described first chip, the second chip, conductive projection, the second conductive channel and the 3rd conductive channel.
2. Stacked Die Packaging structure according to claim 1, it is characterised in that described first conductive channel includes conductive hole and the conductive material being filled in conductive hole.
3. Stacked Die Packaging structure according to claim 2, it is characterized in that, extend to the solder side that first conductive channel at the active face place of described second chip also includes electrically connecting with described conductive hole, described solder side is exposed on the active face of described second chip, and electrically connects with described conductive projection.
4. Stacked Die Packaging structure according to claim 1, it is characterised in that described second conductive channel includes first component, second component and the 3rd parts,
One end of described first component electrically connects with described first conductive channel, and the other end extends to described second component towards first direction,
Described second component extends in a second direction, using the rewiring layer as described Stacked Die Packaging structure, partial electrode on described first chip and/or the second chip is arranged on the surface of described Stacked Die Packaging structure again by described second conductive channel
One end of described 3rd parts electrically connects with described second component, and the other end extends to the surface of described Stacked Die Packaging structure towards described first direction,
Described first direction is vertical with described second direction.
5. Stacked Die Packaging structure according to claim 4, it is characterised in that described 3rd conductive channel includes Part I, Part II and Part III,
One end of described Part I electrically connects with described pad, and the other end extends to described second component towards described first direction,
Described Part II extends in this second direction, using the rewiring layer as described Stacked Die Packaging structure, partial electrode on described first chip and/or the second chip is arranged on the surface of described Stacked Die Packaging structure again by described 3rd conductive channel
One end of described Part III electrically connects with described Part II, and the other end extends to the surface of described Stacked Die Packaging structure towards described first direction.
6. Stacked Die Packaging structure according to claim 5, it is characterised in that described plastic-sealed body includes the first plastic-sealed body and the second plastic-sealed body,
Described first plastic-sealed body covers on described first chip and the second chip, and has relative first surface and second surface, and described second plastic-sealed body covers on the first surface,
Described first component is extended to described first surface place by described first conductive channel, and described Part I is extended to described first surface place by described pad,
Described second component and described Part II all extend on the first surface, and are all covered by described second plastic-sealed body,
Described 3rd parts are extended to the upper surface of described second plastic-sealed body by described second component, and described Part III is extended to described upper surface by described Part II, and described upper surface is the surface of described Stacked Die Packaging structure.
7. Stacked Die Packaging structure according to claim 6, it is characterised in that described first component is one-body molded with second component, described Part I is one-body molded with described Part II,
The formation material of described first component, second component, Part I and Part II is identical.
8. Stacked Die Packaging structure according to claim 7, it is characterised in that described 3rd parts are identical with the formation material of Part III.
9. Stacked Die Packaging structure according to claim 6, it is characterised in that also including the insulating barrier or the metal conducting layer that are positioned at the back side of described first chip, described insulating barrier or metal conducting layer are exposed described.
10. Stacked Die Packaging structure as claimed in any of claims 1 to 9, it is characterized in that, being additionally provided with the weld layer or soldered ball that electrically connect with described second conductive channel and the 3rd conductive channel on the surface of described Stacked Die Packaging structure, Stacked Die Packaging structure is electrically connected with printed circuit board (PCB) by described weld layer or soldered ball.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521115977.4U CN205282470U (en) | 2015-12-24 | 2015-12-24 | Stromatolite chip package structure |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201521115977.4U CN205282470U (en) | 2015-12-24 | 2015-12-24 | Stromatolite chip package structure |
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| CN205282470U true CN205282470U (en) | 2016-06-01 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609480A (en) * | 2015-12-24 | 2016-05-25 | 合肥祖安投资合伙企业(有限合伙) | Stacked chip package structure |
| CN110148566A (en) * | 2019-06-03 | 2019-08-20 | 珠海格力电器股份有限公司 | Intelligent power module with stacked structure and manufacturing method thereof |
-
2015
- 2015-12-24 CN CN201521115977.4U patent/CN205282470U/en active Active
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105609480A (en) * | 2015-12-24 | 2016-05-25 | 合肥祖安投资合伙企业(有限合伙) | Stacked chip package structure |
| CN110148566A (en) * | 2019-06-03 | 2019-08-20 | 珠海格力电器股份有限公司 | Intelligent power module with stacked structure and manufacturing method thereof |
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Effective date of registration: 20180131 Address after: 230000 room 208, A2 building, No. 800 Innovation Industrial Park, No. 800, Wangjiang West Road, Anhui high tech Zone Patentee after: Hefei silicon microelectronics technology Co., Ltd. Address before: Room 190, room H2, two, innovation industrial park, No. 2800, new avenue of innovation, Hefei high tech Zone, Anhui Patentee before: HEFEI ZUAN INVESTMENT PARTNERSHIP ENTERPRISE |