CN205451037U - Efficient parallel distributed data processing system - Google Patents

Efficient parallel distributed data processing system Download PDF

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Publication number
CN205451037U
CN205451037U CN201521106910.4U CN201521106910U CN205451037U CN 205451037 U CN205451037 U CN 205451037U CN 201521106910 U CN201521106910 U CN 201521106910U CN 205451037 U CN205451037 U CN 205451037U
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CN
China
Prior art keywords
data
data processing
processing module
circuit
handling efficiency
Prior art date
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Expired - Fee Related
Application number
CN201521106910.4U
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Chinese (zh)
Inventor
高若飞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tianjin Qinglian Network Incubator Co Ltd
Original Assignee
Tianjin Lianyun Hechuang Information Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Priority to CN201521106910.4U priority Critical patent/CN205451037U/en
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Publication of CN205451037U publication Critical patent/CN205451037U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a high-efficient parallel distributed data processing system, which comprises a housin, one side of casing is equipped with the data input interface, and is equipped with first data processing module, second data processing module, third data processing module, fourth data processing module and main control panel in the casing respectively, the data input interface is connected with main control panel, main control panel respectively with first data processing module, second data processing module, third data processing module and fourth data processing module, and be equipped with first data processing efficiency test circuit, second data processing efficiency test circuit, third data processing efficiency test circuit, fourth data processing efficiency test circuit, data acquisition circuit, data transmission circuit, data processing efficiency comparison circuit and control circuit on the main control panel. The utility model discloses can handle a plurality of data flows simultaneously, also can select the most suitable data processing module, it is with low costs, efficient.

Description

A kind of efficient parallel distributed data processing system
Technical field
This utility model relates to technical field of data processing, particularly relates to a kind of efficient parallel distributed data processing system.
Background technology
Along with the progress of science and technology, increasing intelligent artifact emerges, and data handling system needs data volume to be processed increasing, and people have had higher requirement to data handling system.
Data can only directly be processed by existing data handling system mostly, does not possess multiple data processing module, can not select most suitable data processing module according to the treatment effeciency of each module, improve the efficiency that data process.
Utility model content
The purpose of this utility model is to solve shortcoming present in prior art, and a kind of efficient parallel distributed data processing system proposed.
To achieve these goals, this utility model adopts the technical scheme that
nullA kind of efficient parallel distributed data processing system,Including housing,The side of described housing is provided with Data Input Interface,And in housing, it is respectively equipped with the first data processing module、Second data processing module、3rd data processing module、4th data processing module and master control panel,Described Data Input Interface is connected with master control panel,Described master control panel respectively with the first data processing module、Second data processing module、3rd data processing module and the 4th data processing module,And master control panel is provided with the first data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit、4th data-handling efficiency test circuit、Data acquisition circuit、Data transmission circuit、Data-handling efficiency contrast circuit and control circuit,Described first data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit and the 4th data-handling efficiency test circuit are all connected with data-handling efficiency contrast circuit,Described data-handling efficiency contrast circuit is connected with control circuit,Described control circuit is connected with data transmission circuit,Described data transmission circuit respectively with data acquisition circuit、First data processing module、Second data processing module、3rd data processing module and the 4th data processing module connect.
Preferably, described first data-handling efficiency test circuit and the first data processing module connect, and described second data-handling efficiency test circuit and the second data processing module connect.
Preferably, described 3rd data-handling efficiency test circuit and the 3rd data processing module connect, and described 4th data-handling efficiency test circuit and the 4th data processing module connect.
Preferably, described data acquisition circuit is connected with Data Input Interface.
In this utility model, this efficient parallel distributed data processing system passes through the first data processing module, second data processing module, multiple data streams can be processed by the 3rd data processing module and the 4th data processing module simultaneously, improve the treatment effeciency of data handling system, data can be acquired by data acquisition circuit, remove junk data, can the treatment effeciency of testing data processing module by data-handling efficiency test circuit, the treatment effeciency of each data processing module can be compared by data-handling efficiency contrast circuit, multiple data streams can be processed by this utility model simultaneously, it also is able to select optimal data processing module, simple in construction, easy to use, low cost, efficiency is high.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of efficient parallel distributed data processing system that the utility model proposes;
Fig. 2 is the system schematic of a kind of efficient parallel distributed data processing system that the utility model proposes.
In figure: 1 housing, 2 first data processing modules, 3 second data processing modules, 4 the 3rd data processing modules, 5 the 4th data processing modules, 6 Data Input Interfaces, 7 master control panels.
Detailed description of the invention
Below in conjunction with the accompanying drawing in this utility model embodiment, the technical scheme in this utility model embodiment is clearly and completely described, it is clear that described embodiment is only a part of embodiment of this utility model rather than whole embodiments.
nullWith reference to Fig. 1-2,A kind of efficient parallel distributed data processing system,Including housing 1,The side of housing 1 is provided with Data Input Interface 6,And in housing 1, it is respectively equipped with the first data processing module 2、Second data processing module 3、3rd data processing module 4、4th data processing module 5 and master control panel 7,Data Input Interface 6 is connected with master control panel 7,Master control panel 7 respectively with the first data processing module 2、Second data processing module 3、3rd data processing module 4 and the 4th data processing module 5,And master control panel 7 is provided with the first data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit、4th data-handling efficiency test circuit、Data acquisition circuit、Data transmission circuit、Data-handling efficiency contrast circuit and control circuit,First data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit and the 4th data-handling efficiency test circuit are all connected with data-handling efficiency contrast circuit,Data-handling efficiency contrast circuit is connected with control circuit,Control circuit is connected with data transmission circuit,Data transmission circuit respectively with data acquisition circuit、First data processing module 2、Second data processing module 3、3rd data processing module 4 and the 4th data processing module 5 connect,This efficient parallel distributed data processing system passes through the first data processing module 2、Second data processing module 3、Multiple data streams can be processed by the 3rd data processing module 4 and the 4th data processing module 5 simultaneously,Improve the treatment effeciency of data handling system,Data can be acquired by data acquisition circuit,Remove junk data,Can the treatment effeciency of testing data processing module by data-handling efficiency test circuit,The treatment effeciency of each data processing module can be compared by data-handling efficiency contrast circuit,Multiple data streams can be processed by this utility model simultaneously,It also is able to select optimal data processing module,Simple in construction,Easy to use,Low cost,Efficiency is high.
nullFirst data-handling efficiency test circuit and the first data processing module 2 connect,Second data-handling efficiency test circuit and the second data processing module 3 connect,3rd data-handling efficiency test circuit and the 3rd data processing module 4 connect,4th data-handling efficiency test circuit and the 4th data processing module 5 connect,Data acquisition circuit is connected with Data Input Interface 6,This efficient parallel distributed data processing system passes through the first data processing module 2、Second data processing module 3、Multiple data streams can be processed by the 3rd data processing module 4 and the 4th data processing module 5 simultaneously,Improve the treatment effeciency of data handling system,Data can be acquired by data acquisition circuit,Remove junk data,Can the treatment effeciency of testing data processing module by data-handling efficiency test circuit,The treatment effeciency of each data processing module can be compared by data-handling efficiency contrast circuit,Multiple data streams can be processed by this utility model simultaneously,It also is able to select optimal data processing module,Simple in construction,Easy to use,Low cost,Efficiency is high.
Operation principle: data flow through Data Input Interface 6 and input into data handling system, junk data is removed through data acquisition circuit, test to each data processing module through data transmission circuit transmission, the treatment effeciency of each data processing module is tested by data-handling efficiency test circuit, test result compares in data-handling efficiency contrast circuit, after comparing optimal data processing module, transmitting the result to control circuit, control circuit sends data to process in corresponding data processing module.
The above; it is only this utility model preferably detailed description of the invention; but protection domain of the present utility model is not limited thereto; any those familiar with the art is in the technical scope that this utility model discloses; conceive equivalent or change in addition according to the technical solution of the utility model and utility model thereof, all should contain within protection domain of the present utility model.

Claims (4)

  1. null1. an efficient parallel distributed data processing system,Including housing (1),It is characterized in that,The side of described housing (1) is provided with Data Input Interface (6),And in housing (1), it is respectively equipped with the first data processing module (2)、Second data processing module (3)、3rd data processing module (4)、4th data processing module (5) and master control panel (7),Described Data Input Interface (6) is connected with master control panel (7),Described master control panel (7) respectively with the first data processing module (2)、Second data processing module (3)、3rd data processing module (4) and the 4th data processing module (5),And master control panel (7) is provided with the first data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit、4th data-handling efficiency test circuit、Data acquisition circuit、Data transmission circuit、Data-handling efficiency contrast circuit and control circuit,Described first data-handling efficiency test circuit、Second data-handling efficiency test circuit、3rd data-handling efficiency test circuit and the 4th data-handling efficiency test circuit are all connected with data-handling efficiency contrast circuit,Described data-handling efficiency contrast circuit is connected with control circuit,Described control circuit is connected with data transmission circuit,Described data transmission circuit respectively with data acquisition circuit、First data processing module (2)、Second data processing module (3)、3rd data processing module (4) and the 4th data processing module (5) connect.
  2. A kind of efficient parallel distributed data processing system the most according to claim 1, it is characterized in that, described first data-handling efficiency test circuit and the first data processing module (2) connect, and described second data-handling efficiency test circuit and the second data processing module (3) connect.
  3. A kind of efficient parallel distributed data processing system the most according to claim 1, it is characterized in that, described 3rd data-handling efficiency test circuit and the 3rd data processing module (4) connect, and described 4th data-handling efficiency test circuit and the 4th data processing module (5) connect.
  4. A kind of efficient parallel distributed data processing system the most according to claim 1, it is characterised in that described data acquisition circuit is connected with Data Input Interface (6).
CN201521106910.4U 2015-12-25 2015-12-25 Efficient parallel distributed data processing system Expired - Fee Related CN205451037U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201521106910.4U CN205451037U (en) 2015-12-25 2015-12-25 Efficient parallel distributed data processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201521106910.4U CN205451037U (en) 2015-12-25 2015-12-25 Efficient parallel distributed data processing system

Publications (1)

Publication Number Publication Date
CN205451037U true CN205451037U (en) 2016-08-10

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107368370A (en) * 2017-07-04 2017-11-21 合肥市乐腾科技咨询有限公司 High-efficiency data processing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107368370A (en) * 2017-07-04 2017-11-21 合肥市乐腾科技咨询有限公司 High-efficiency data processing system

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CB03 Change of inventor or designer information

Inventor after: Zhao Rong

Inventor before: Gao Ruofei

CB03 Change of inventor or designer information
TR01 Transfer of patent right

Effective date of registration: 20170823

Address after: Binhai New Area 300000 Binhai New Area of Tianjin Huayuan Industrial Zone Industrial Road one block D No. 2, 1102, 1103, 1101, 1104, 1105

Patentee after: TIANJIN QINGLIAN NETWORK INCUBATOR CO., LTD.

Address before: Binhai New Area 300000 Binhai New Area of Tianjin Huayuan Industrial Zone Industrial Road one block D No. 2, 1102, 1103, 1101, 1104 (1105 in Tianjin Qing Lian network Incubator Co., Ltd.)

Patentee before: TIANJIN LIANYUN HECHUANG INFORMATION TECHNOLOGY CO., LTD.

TR01 Transfer of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160810

Termination date: 20181225

CF01 Termination of patent right due to non-payment of annual fee