CN205427072U - LCR testing arrangement - Google Patents
LCR testing arrangement Download PDFInfo
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- CN205427072U CN205427072U CN201620138955.8U CN201620138955U CN205427072U CN 205427072 U CN205427072 U CN 205427072U CN 201620138955 U CN201620138955 U CN 201620138955U CN 205427072 U CN205427072 U CN 205427072U
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- programmable logic
- lcr
- chip microcomputer
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Abstract
The utility model relates to a LCR testing arrangement has the singlechip, connect through data bus between singlechip and the programmable logic circuit, and the level control of singlechip end, filtering control end, range control end and IV switching end link to each other with the input that the input of sinusoidal signal generator, filtering power amplifier circuit's input, the input of range selection circuit, differential fortune were put respectively, the programmable logic circuit loops through and is connected to differential fortune behind sinusoidal signal generator, filtering power amplifier circuit, source series resistance zx and the range selection circuit and puts, the output that differential fortune was put is through the input of programme -controlled mirror looks circuit connection to AD converting circuit, the input of AD converting circuit's output termination singlechip, the component is surveyed in the drive of source series resistance zx. The utility model has the characteristics of benchmark etc. Is calculated to the high performance -price ratio, help knowing the actual performance of components and parts under actual operating condition, improve the performance and the reliability of product.
Description
Technical field
This utility model relates to a kind of test device technique field, tests device particularly to a kind of LCR.
Background technology
LCR inductance (L), electric capacity (C) and resistance (R), as basic components and parts, are widely used in electronic product.Along with technology and performance development and the raising of electronic product, the requirement of the detection technique of components and parts is also constantly being improved, particularly to low cost LCR electric bridge it is also proposed that carried out the highest requirement by domestic relevant industries.The frequency of LCR tester of the prior art is the highest, is unfavorable for understanding components and parts actual performance under actual operating conditions, and the performance and reliability of product is relatively low.
Summary of the invention
The purpose of this utility model is the defect overcoming prior art to exist, it is provided that a kind of high performance-price ratio, contributes to understanding components and parts actual performance under actual operating conditions, and the LCR of the performance and reliability improving product tests device.
The technical scheme realizing this utility model purpose is: a kind of LCR tests device, has single-chip microcomputer, Programmable Logic Device, sinusoidal signal generator, filtering power amplifier, selective circuit of measuring range, differential amplifier, program control phase discriminator and A/D change-over circuit；Connected by data/address bus between described single-chip microcomputer and Programmable Logic Device, and the Automatic level control end of single-chip microcomputer, filtering control end, range control end and I/V switch terminal are connected with the input of sinusoidal signal generator, the filtering input of power amplifier, the input of selective circuit of measuring range, the input of differential amplifier respectively；Described Programmable Logic Device is connected to differential amplifier after passing sequentially through sinusoidal signal generator, filtering power amplifier, source resistance Zx and selective circuit of measuring range, and the phase controlling of Programmable Logic Device terminates the input of program control phase discriminator, A/D starts the input of termination A/D change-over circuit；The outfan of described differential amplifier is connected to the input of A/D change-over circuit by program control phase discriminator；The outfan of described A/D change-over circuit connects the input of single-chip microcomputer；Described source resistance Zx drives detected element；Described detected element is connected by input circuit and one group of four terminal pair configuration.
Technique scheme also has variable gain circuit；The input of described variable gain circuit connects the gain of single-chip microcomputer respectively and selects end and the outfan of differential amplifier, the input of output termination A/D change-over circuit.
Described in technique scheme, four terminal pair configuration includes self-balancing bridge circuit, by coaxial cable isolation signals voltage path and current path, the return current screen layer by coaxial cable, makes screen layer counteract magnetic flux produced by inner wire；Hp end and the Hc end of described self-balancing bridge circuit are mutually isolated, and electric current flows to Lc end from Hc end, rely on a feedback control loop so that G point maintains virtual earth and makes current flow through range resistance Rs.
Programmable Logic Device described in technique scheme includes DDS module and counting module；The outfan of described DDS module is connected with the input of sine-wave generator；The outfan of described counting module connects the input of single-chip microcomputer by data/address bus.
Selective circuit of measuring range described in technique scheme includes range resistance Rs and amplifier A1.
The outfan of the input termination reference clock of Programmable Logic Device described in technique scheme；Described reference clock includes the crystal oscillator of 38.4MHz.
The outfan of the input termination reference clock of Programmable Logic Device described in technique scheme；Described reference clock includes the crystal oscillator of 38.4MHz.
Connected by data wire on single-chip microcomputer described in technique scheme and have keyboard and LCD display.
Using after technique scheme, this utility model has a following positive effect:
(1) this utility model has high performance-price ratio, calculates the features such as benchmark, contributes to understanding components and parts actual performance under actual operating conditions, improves the performance and reliability of product.
(2) this utility model also has variable gain circuit；The input of described variable gain circuit connects the gain of single-chip microcomputer respectively and selects end and the outfan of differential amplifier, the input of output termination A/D change-over circuit, for reaching higher resolution, give necessarily to amplify at variable gain amplifier to the signal of varying level and deliver to phase discriminator again.
Accompanying drawing explanation
In order to make content of the present utility model be easier to be clearly understood, below according to specific embodiment and combine accompanying drawing, this utility model is described in further detail, wherein
Fig. 1 is theory diagram of the present utility model；
Fig. 2 is that CPLD of the present utility model produces sinusoidal signal and control circuit；
Fig. 3 is multi-channel filter circuit of the present utility model；
Fig. 4 is power amplification circuit of the present utility model；
Fig. 5 is selective circuit of measuring range of the present utility model；
Fig. 6 is program control phase discriminator of the present utility model；
Fig. 7 is charge balance type A/D change-over circuit of the present utility model；
Fig. 8 is four terminal pair configuration of the present utility model (4TP) schematic diagram；
Accompanying drawing is numbered: single-chip microcomputer 1, Programmable Logic Device 2, sinusoidal signal generator 3, filtering power amplifier 4, selective circuit of measuring range 5, differential amplifier 6, program control phase discriminator 7, A/D change-over circuit 8, variable gain circuit 9, reference clock 10, keyboard 11, LCD display 12.
Detailed description of the invention
(embodiment 1)
See that Fig. 1, this utility model have single-chip microcomputer 1, Programmable Logic Device 2, sinusoidal signal generator 3, filtering power amplifier 4, selective circuit of measuring range 5, differential amplifier 6, program control phase discriminator 7 and A/D change-over circuit 8；Connected by data/address bus between single-chip microcomputer 1 and Programmable Logic Device 2, and the Automatic level control end of single-chip microcomputer 1, filtering control end, range control end and I/V switch terminal are connected with the input of sinusoidal signal generator 3, the filtering input of power amplifier 4, the input of selective circuit of measuring range 5, the input of differential amplifier 6 respectively；Programmable Logic Device 2 is connected to differential amplifier 6 after passing sequentially through sinusoidal signal generator 3, filtering power amplifier 4, source resistance Zx and selective circuit of measuring range 5, and the phase controlling of Programmable Logic Device 2 terminates the input of program control phase discriminator 7, A/D starts the input of termination A/D change-over circuit 8；The outfan of differential amplifier 6 is connected to the input of A/D change-over circuit 8 by program control phase discriminator 7；The outfan of A/D change-over circuit 8 connects the input of single-chip microcomputer 1；Source resistance Zx drives detected element；Detected element is connected by input circuit and one group of four terminal pair configuration.
Also there is variable gain circuit 9；The input of variable gain circuit 9 connects the gain of single-chip microcomputer 1 respectively and selects end and the outfan of differential amplifier 6, the input of output termination A/D change-over circuit 8.
Four terminal pair configuration includes self-balancing bridge circuit, by coaxial cable isolation signals voltage path and current path, the return current screen layer by coaxial cable, makes screen layer counteract magnetic flux produced by inner wire；Hp end and the Hc end of self-balancing bridge circuit are mutually isolated, and electric current flows to Lc end from Hc end, rely on a feedback control loop so that G point maintains virtual earth and makes current flow through range resistance Rs.
Programmable Logic Device 2 includes DDS module and counting module；The outfan of DDS module is connected with the input of sine-wave generator；The outfan of counting module connects the input of single-chip microcomputer 1 by data/address bus.
Selective circuit of measuring range 5 includes range resistance Rs and amplifier A1.
The outfan of the input termination reference clock 10 of Programmable Logic Device 2；Reference clock 10 includes the crystal oscillator of 38.4MHz.
Connected by data wire on single-chip microcomputer 1 and have keyboard 11 and LCD display 12.
Operation principle of the present utility model is: the measuring transmitter of native system can produce the sinusoidal signal that frequency changes from 50Hz～100kHz, amplitude 0.1Vrms～1Vrms.Test signal, after one group of wave filter, is sent into power amplifier and is amplified, then goes to drive detected element by source resistance.Detected element is connected by input circuit and one group of four terminal pair configuration, and self-balancing bridge circuit makes Lp end virtual earth all the time, forms two-way vector voltage.Tested two-way vector voltage sends into phase discriminator phase demodulation through analog switch timesharing, and phase discriminator exports the phase discrimination signal of four groups of difference fixed phases.A/D change-over circuit is converted to digital quantity these four groups of vector voltages, and input C8051F120 single-chip microcomputer processes, and finally calculates the different electrical quantity such as Z, L, C, R and carries out showing or sorting.
V--I method impedance measurement principle: this instrument uses V--I (voltage--electric current) method to carry out impedance measurement.In figure, Ei is signal source, and Vu is the voltage being added on tested impedance two ends, and Vs is the output of amplifier A, and Ro is output impedance, and it is unlikely excessive that it act as limiting signal source output electric current, it is ensured that amplifier A steady operation.Ix is the electric current flowing through Zx, and Rs is accurate range resistance.
If Zx is tested impedance, then:
Zx=Rs+Xs (5-1)
Obtain according to Ohm's law:
Amplifier A output Vs can be expressed from the next:
Formula 5-3 substitutes into 5-2 and obtains:
If Vu, Vs are represented by following vector form:
Vu=V0+jV1
Vs=V2+jV3(5-5)
Formula 5-5 substitutes into 5-4 and obtains:
If tested impedance is inductance, then:
Xs=ω Lx=2 π fLx (5-7)
If tested impedance is electric capacity, then:
Can be obtained by formula 5-6,5-7:
Can be obtained by formula 5-6,5-8:
V0,V1,V2,V3Being converted to digital signal through a/d converter after being detected by phase discriminator, C8051F120 obtains its value back-pushed-type 5-9,5-10 calculating i.e. can obtain Lx, Cx.
Testing source: the signal source circuit condition that simulation is actual in time measuring, the signal source of native system can produce the multiple signal levels between 50Hz～100kHz.Native system is produced a clock reference by the crystal oscillator of 38.400MHz, and the PLD EPM570T100C of input ALTERA produces a sinusoidal digital signal, is converted to stairstepping sinusoidal signal through DAC0800 digital to analog converter.This signal sends into power amplification circuit after being filtered by low pass filter, then exports in detected element through output resistance.
Four terminal pair configuration: four terminal pair configuration (4TP) schematic diagram, four terminal pair configuration solves the problems such as Mutual Inductance Coupling, stray capacitance, lead-in inductance, lead resistance, because it is isolated signal voltage path with coaxial cable with current path, the return current screen layer by coaxial cable, makes outer conductor (screen layer) counteract magnetic flux produced by inner wire.The measurement scope of this configuration structure can reach 1 below Ω more than 100M Ω, in conjunction with method of auto balancing bridge, in 50Hz～100kHz, it can be carried out accurate impedance measurement.
Self-balancing bridge circuit: self-balancing bridge circuit carrys out the parameters such as computing impedance by the voltage and the electric current flow through on Zx measuring Zx two ends.Hp end and Hc end are mutually isolated, so can accurately measure the voltage on Zx.Electric current flows to Lc end from Hc end, relies on a feedback control loop so that G point maintains virtual earth and makes current flow through range resistance Rs.Therefore, by measuring the ohmically voltage of range, the electric current flowing through on Zx can be recorded.
A/D change-over circuit: phase discriminator and A/D converter that vector voltage Vu and Vs meeting timesharing is controlled by EPM570T100C by one are changed.Real part corresponding for Vu with Vs and imaginary part conversion value is read from EPM570T100C data terminal by C8051F120 microprocessor.By voltage Vu and the real component of electric current Vs and imaginary, C8051F120 microprocessor just can calculate a series of electrical quantity such as equivalent series reactance or equivalent parallel reactance.
C8051F120 single-chip microcomputer is the control centre of instrument all operations, and it obtains input from keyboard and controls to complete all measurement sequential.Gained measured value is also calculated by certain formula and it is delivered to display and shows by it.
During work, C8051F120 single-chip microcomputer passes through data/address bus transmission frequency control word to Programmable Logic Controller EPM570T100C, the digital quantity of sinusoidal variations is exported by the DDS module in EPM570T100C, obtaining, through sine-wave generator, the ladder sine wave that frequency is certain, this signal is added in tested impedance Z x by after low pass filter filtering power amplification after level translation.
Flow through the current signal on Zx and be converted to reflect the voltage output Vs of current signal through range resistance Rs, differential amplifier measures voltage signal Vu and Vs being added on Zx under the control of C8051F120 successively, for reaching higher resolution, give necessarily to amplify at variable gain amplifier to the signal of varying level and deliver to phase discriminator again, under the control of C8051F120 and EPM570T100C, phase discriminator exports the exchange phase demodulation output of four groups of difference fixed phases, is respectively (seeing formula 5-5):
0 degree of phase demodulation output (Vu real part) of V0:Vu
90 degree of phase demodulations output (Vu imaginary part) of V1:Vu
0 degree of phase demodulation output (Vs real part) of V2:Vs
90 degree of phase demodulations output (Vs imaginary part) of V3:Vs
These signals are produced counting controling signal by a/d converter respectively, 8253 counting modules controlled in EPM570T100C are converted to digital quantity, by becoming all kinds of electrical quantitys such as LCR by formula manipulation after data/address bus input C8051F120, result of calculation shows on LCD the most at last.
Particular embodiments described above; the purpose of this utility model, technical scheme and beneficial effect are further described; it is it should be understood that; the foregoing is only specific embodiment of the utility model; it is not limited to this utility model; all within spirit of the present utility model and principle, any modification, equivalent substitution and improvement etc. done, within should be included in protection domain of the present utility model.
Claims (7)
1. a LCR tests device, it is characterised in that: there is single-chip microcomputer (1), Programmable Logic Device (2), sinusoidal signal generator (3), filtering power amplifier (4), selective circuit of measuring range (5), differential amplifier (6), program control phase discriminator (7) and A/D change-over circuit (8)；Connected by data/address bus between described single-chip microcomputer (1) and Programmable Logic Device (2), and the Automatic level control end of single-chip microcomputer (1), filtering control end, range control end and I/V switch terminal are connected with the input of sinusoidal signal generator (3), the input of filtering power amplifier (4), the input of selective circuit of measuring range (5), the input of differential amplifier (6) respectively；Described Programmable Logic Device (2) is connected to differential amplifier (6) after passing sequentially through sinusoidal signal generator (3), filtering power amplifier (4), source resistance Zx and selective circuit of measuring range (5), and the phase controlling of Programmable Logic Device (2) terminates the input of program control phase discriminator (7), A/D starts the input of termination A/D change-over circuit (8)；The outfan of described differential amplifier (6) is connected to the input of A/D change-over circuit (8) by program control phase discriminator (7)；The outfan of described A/D change-over circuit (8) connects the input of single-chip microcomputer (1)；Described source resistance Zx drives detected element；Described detected element is connected by input circuit and one group of four terminal pair configuration.
LCR the most according to claim 1 tests device, it is characterised in that: also there is variable gain circuit (9)；The input of described variable gain circuit (9) connects the gain of single-chip microcomputer (1) respectively and selects end and the outfan of differential amplifier (6), the input of output termination A/D change-over circuit (8).
LCR the most according to claim 1 tests device, it is characterized in that: described four terminal pair configuration includes self-balancing bridge circuit, by coaxial cable isolation signals voltage path and current path, the return current screen layer by coaxial cable, screen layer is made to counteract magnetic flux produced by inner wire；Hp end and the Hc end of described self-balancing bridge circuit are mutually isolated, and electric current flows to Lc end from Hc end, rely on a feedback control loop so that G point maintains virtual earth and makes current flow through range resistance Rs.
LCR the most according to claim 1 tests device, it is characterised in that: described Programmable Logic Device (2) includes DDS module and counting module；The outfan of described DDS module is connected with the input of sine-wave generator；The outfan of described counting module connects the input of single-chip microcomputer (1) by data/address bus.
LCR the most according to claim 1 tests device, it is characterised in that: described selective circuit of measuring range (5) includes range resistance Rs and amplifier A1.
LCR the most according to claim 1 tests device, it is characterised in that: the outfan of input termination reference clock (10) of described Programmable Logic Device (2)；Described reference clock (10) includes the crystal oscillator of 38.4MHz.
LCR the most according to claim 1 tests device, it is characterised in that: connected by data wire on described single-chip microcomputer (1) and have keyboard (11) and LCD display (12).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620138955.8U CN205427072U (en) | 2016-02-24 | 2016-02-24 | LCR testing arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620138955.8U CN205427072U (en) | 2016-02-24 | 2016-02-24 | LCR testing arrangement |
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| CN205427072U true CN205427072U (en) | 2016-08-03 |
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| CN201620138955.8U Expired - Fee Related CN205427072U (en) | 2016-02-24 | 2016-02-24 | LCR testing arrangement |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444588A (en) * | 2018-11-15 | 2019-03-08 | 东南大学 | A kind of LCR measuring system based on FPGA+DDS+PLL |
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2016
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109444588A (en) * | 2018-11-15 | 2019-03-08 | 东南大学 | A kind of LCR measuring system based on FPGA+DDS+PLL |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160803 Termination date: 20200224 |
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| CF01 | Termination of patent right due to non-payment of annual fee |