CN205404798U - Hardware architecture of section sonar - Google Patents
Hardware architecture of section sonar Download PDFInfo
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- CN205404798U CN205404798U CN201620206220.4U CN201620206220U CN205404798U CN 205404798 U CN205404798 U CN 205404798U CN 201620206220 U CN201620206220 U CN 201620206220U CN 205404798 U CN205404798 U CN 205404798U
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Abstract
The utility model relates to a hardware architecture of section sonar in FPGA, the sonar signal process unit based on FPGA including sonar communication unit, sonar signal emission unit, sonar signal receiving element and sonar transducer array and above -mentioned each unit of control: sonar communication unit links to each other with the sonar signal processing unit, and sonar signal processing unit connection sonar signal emission unit, sonar signal emission unit connect sonar transducer array, and sonar transducer array connects sonar signal sonar signal processing 0, and sonar signal sonar signal processing 0 connects the sonar signal processing unit. The utility model discloses an advantage embodies: owing to take above technical scheme, a slice is simplified into by past two to the required hardware of treater, so it has following advantage: hardware architecture is simple, and is small, the low power dissipation, the hardware pin is abundant, and the extension is upgraded portably, the data link node is few, and the reliability is high.
Description
Technical field
This utility model relates to a kind of sonar detection hardware configuration, is specifically related to the hardware configuration of a kind of section sonar.
Background technology
In recent years, along with the development of marine resources development technology, the demand of high resolution section sonar is more and more urgent, and as a kind of important undersea detection means, undersea detection field, development of resources field are played an important role by high resolution section sonar.
But, of the prior art have drawbacks in that
Current section sonar signal processing device adopts high speed digital signal processor (DSP) as primary processor, divisor word signal processor (DSP) is outward, process device and must just can be configured to coordinate the signal processing device of each several part circuit cooperation division of labor in conjunction with FPGA, owing to signal processor (DSP) lacks motility, cause that sonar system upgrading is highly difficult, once sonar system increases array element quantity, necessarily imply that data bit width increases, and the interface bit wide of signal processor (DSP) is fixing, in order to adapt to the data bit width of new system, signal processor must be redesigned；Additionally signal processor (DSP) needs and FPGA coordinated operation, this adds increased the data link node of system, and data link node is more many, and the reliability of system necessarily becomes more poor；Owing to system structure is complicated, required electronic device is many, causes signal processing body to amass excessive, and power consumption is too high.
Utility model content
The purpose of this utility model is for deficiency of the prior art, it is provided that the hardware configuration of the section sonar of a kind of function admirable.
This utility model adopts FPGA to constitute signal processing device, fast development due to FPGA technology, the disposal ability making the FPGA device with data processing function has been over DSP device, and a piece of FPGA device thus can be used to complete over just being completed by DSP and FPGA two panels device of task；And due to FPGA pin enrich, pin can flexible allocation function, so no matter increase data bit width or reduce data bit width, it is only necessary to redistributing the pin of FPGA, it is not necessary to carry out the change of total system.
For achieving the above object, the utility model discloses following technical scheme:
The hardware configuration of a kind of section sonar based on FPGA, receives unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and controls the signal processing unit based on FPGA of above-mentioned each unit:
Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit；
Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively；
Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit.
Further, described sonar communication unit is made up of a piece of network chip W5300.
Further, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, and the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit.
Further, after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form.
The hardware configuration of a kind of section sonar disclosed in this utility model, owing to taking above technical scheme, processor necessary hardware is simplified to a piece of by the two panels in past, therefore it has the advantage that hardware configuration is simple, and volume is little, low in energy consumption；Hardware pins enriches, extension upgrading simplicity；Data link node is few, and reliability is high.
Accompanying drawing explanation
Fig. 1 is structured flowchart of the present utility model.
Detailed description of the invention
Also with reference to accompanying drawing, this utility model is further described below in conjunction with embodiment.
Refer to Fig. 1.
This utility model adopts FPGA to constitute signal processing device, fast development due to FPGA technology, the disposal ability making the FPGA device with data processing function has been over DSP device, and a piece of FPGA device thus can be used to complete over just being completed by DSP and FPGA two panels device of task；And due to FPGA pin enrich, pin can flexible allocation function, so no matter increase data bit width or reduce data bit width, it is only necessary to redistributing the pin of FPGA, it is not necessary to carry out the change of total system.
The hardware configuration of a kind of section sonar based on FPGA, receives unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and controls the signal processing unit based on FPGA of above-mentioned each unit:
Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit；
Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively；
Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit.
In this utility model, described sonar communication unit is made up of a piece of network chip W5300.
In this utility model, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, and the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit.
In this utility model, after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form.
Realize a kind of multiple beam section sonar signal processor based on high speed FPGA, the logical TCP/IP network control FPGA of main frame waterborne produces pulse signal, FPGA is carried out power amplification by power amplifier after producing analog waveform according to the Wave data write D/A that the order of main frame waterborne will be launched and be simulated signal condition by filter amplification circuit again, thus promoting transmitting transducer to launch signal, sent by transmitting transducer after the amplified conditioning of this signal, target receives transducer acoustic reflection tieback, the output signal receiving transducer processes by being transferred to FPGA Parallel signal processing part after collection of simulant signal hop collection, then again by process result with main frame in conducting water on TCP/IP latticed form；This process is controlled by TCP/IP network in real time by main frame waterborne, produces to control the synchronizing signal of collection of simulant signal hop while launching signal；Collection of simulant signal hop gathers echo-signal under the control of FPGA, and the data parallel collected is transferred to FPGA and processes in real time, and result is transferred to main frame waterborne by network and displays and store.
Signal processor of the present utility model is installed on sonar and receives in transducer housing, and sonar transmission signal is transferred to transmitting transducer by cable by receiving transducer.
After this novel entrance duty that powers on, first start main frame waterborne and enter aobvious prosecutor formula, then pass through network and set up the connection novel with book.
After connection establishment is got up, signal processing device can be carried out parameter configuration by main frame waterborne, as arranged range, arranges signal transmitter unit and launches power level signal, arrange the pulse width launching signal, arrange transmitting signal-pulse repetition frequency.
Workflow is: signal processor is upon receipt of starting order, then according to the parameter set, launch ping with certain pulsewidth and frequency.The impulse waveform of different length is stored in FPGA program in the form of data, the FPGA order according to main frame waterborne, this waveform data is delivered on data/address bus, these data are converted into waveform and give power amplifier amplification and launch by D/A, after coupling transmitting in 35kHz-65kHz, sound source level reaches 206dB, fluctuating 3dB in band.FPGA Parallel signal processing device gathers and does low-pass filtering taking-up envelope after signal carries out related operation with the copy launching signal again.The data of the data after initial data, correlation computations and envelope are both passed through network interface and deliver to main frame waterborne by FPGA signal processing.
The above is only preferred implementation of the present utility model, is not intended to limit；Should be understood that, although this utility model being described in detail with reference to the various embodiments described above, it will be understood by those within the art that, the technical scheme described in the various embodiments described above still can be modified by it, or wherein some or all of technical characteristic carries out equivalent replacement；And these amendments and replacement, do not make the essence of corresponding technical scheme depart from the scope of each embodiment technical scheme of this utility model.
Claims (4)
1. the hardware configuration based on the section sonar of FPGA, it is characterized in that, receive unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and control the signal processing unit based on FPGA of above-mentioned each unit:
Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit；
Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively；
Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit.
2. the hardware configuration of a kind of section sonar based on FPGA according to claim 1, it is characterised in that described sonar communication unit is made up of a piece of network chip W5300.
3. the hardware configuration of a kind of section sonar based on FPGA according to claim 2, it is characterized in that, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit.
4. the hardware configuration of a kind of section sonar based on FPGA according to claim 3, it is characterised in that after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form.
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| CN201620206220.4U CN205404798U (en) | 2016-03-17 | 2016-03-17 | Hardware architecture of section sonar |
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| CN201620206220.4U CN205404798U (en) | 2016-03-17 | 2016-03-17 | Hardware architecture of section sonar |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105699956A (en) * | 2016-03-17 | 2016-06-22 | 天津海之星海洋科技发展有限公司 | Chirp sonar hardware structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105699956A (en) * | 2016-03-17 | 2016-06-22 | 天津海之星海洋科技发展有限公司 | Chirp sonar hardware structure |
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| C14 | Grant of patent or utility model | ||
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| TR01 | Transfer of patent right |
Effective date of registration: 20170904 Address after: 300450, Tianjin, Tanggu District, Tianjin TEDA SME Park, building 4, floor 107 plant Patentee after: Tianjin sea star underwater robot Co., Ltd. Address before: 300457, Tianjin Binhai New Area Economic and Technological Development Zone, Tianjin TEDA SME Park Building 1, block C1, 603 Patentee before: TIANJIN OSTAR OCEAN SCIENCE AND TECHNOLOGY DEVELOPMENT CO., LTD. |
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| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210426 Address after: 202-1, building a, Edie Science Park (Ningbo), 1277 Zhongguan West Road, Zhuangshi street, Zhenhai District, Ningbo, Zhejiang 315000 Patentee after: Ningbo xinghehai Technology Co.,Ltd. Address before: 300450 No. 107 factory building, building 4, Tianjin TEDA medium and small business park, Tanggu, Tianjin Patentee before: TIANJIN OSTAR UNDERWATER ROBOT Co.,Ltd. |
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| TR01 | Transfer of patent right |