CN105699956A - Chirp sonar hardware structure - Google Patents

Chirp sonar hardware structure Download PDF

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Publication number
CN105699956A
CN105699956A CN201610152898.3A CN201610152898A CN105699956A CN 105699956 A CN105699956 A CN 105699956A CN 201610152898 A CN201610152898 A CN 201610152898A CN 105699956 A CN105699956 A CN 105699956A
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CN
China
Prior art keywords
sonar
unit
signal processing
processing unit
signal
Prior art date
Application number
CN201610152898.3A
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Chinese (zh)
Inventor
王晓峰
谢磊
张超
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天津海之星海洋科技发展有限公司
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Application filed by 天津海之星海洋科技发展有限公司 filed Critical 天津海之星海洋科技发展有限公司
Priority to CN201610152898.3A priority Critical patent/CN105699956A/en
Publication of CN105699956A publication Critical patent/CN105699956A/en

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01SRADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/521Constructional features

Abstract

The invention relates to an FPGA-based chirp sonar hardware structure, which comprises a sonar communication unit, a sonar signal transmitting unit, a sonar signal receiving unit, a sonar transducer array and an FPGA-based sonar signal processing unit for controlling the above units, wherein the sonar communication unit is connected with the sonar signal processing unit; the sonar signal processing unit is connected with the sonar signal transmitting unit; the sonar signal transmitting unit is connected with the sonar transducer array; the sonar transducer array is connected with the sonar signal receiving unit; and the sonar signal receiving unit is connected with the sonar signal processing unit. By adopting the above technical scheme, the chirp sonar hardware structure of the invention has the advantages that the hardware needed by the processor is simplified into one piece compared with the original two pieces, the hardware has a simple structure, the size is small, the power consumption is low, the hardware has rich pins, the extension and the updating are simple and convenient, the data link has few nodes, and the reliability is high.

Description

A kind of hardware configuration of section sonar

Technical field

The present invention relates to a kind of sonar detection hardware configuration, be specifically related to the hardware configuration of a kind of section sonar。

Background technology

In recent years, along with the development of marine resources development technology, the demand of high resolution section sonar is more and more urgent, and as a kind of important undersea detection means, undersea detection field, development of resources field are played an important role by high resolution section sonar。

But, of the prior art have drawbacks in that

Current section sonar signal processing device adopts high speed digital signal processor (DSP) as primary processor, divisor word signal processor (DSP) is outward, process device and must just can be configured to coordinate the signal processing device of each several part circuit cooperation division of labor in conjunction with FPGA, owing to signal processor (DSP) lacks motility, cause that sonar system upgrading is highly difficult, once sonar system increases array element quantity, necessarily imply that data bit width increases, and the interface bit wide of signal processor (DSP) is fixing, in order to adapt to the data bit width of new system, signal processor must be redesigned;Additionally signal processor (DSP) needs and FPGA coordinated operation, this adds increased the data link node of system, and data link node is more many, and the reliability of system necessarily becomes more poor;Owing to system structure is complicated, required electronic device is many, causes signal processing body to amass excessive, and power consumption is too high。

Summary of the invention

It is an object of the invention to for deficiency of the prior art, it is provided that the hardware configuration of the section sonar of a kind of function admirable。

The present invention adopts FPGA to constitute signal processing device, fast development due to FPGA technology, the disposal ability making the FPGA device with data processing function has been over DSP device, and a piece of FPGA device thus can be used to complete over just being completed by DSP and FPGA two panels device of task;And due to FPGA pin enrich, pin can flexible allocation function, so no matter increase data bit width or reduce data bit width, it is only necessary to redistributing the pin of FPGA, it is not necessary to carry out the change of total system。

For achieving the above object, the invention discloses following technical scheme:

The hardware configuration of a kind of section sonar based on FPGA, receives unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and controls the signal processing unit based on FPGA of above-mentioned each unit:

Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit;

Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively;

Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit。

Further, described sonar communication unit is made up of a piece of network chip W5300。

Further, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, and the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit。

Further, after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form。

The hardware configuration of a kind of section sonar disclosed by the invention, owing to taking above technical scheme, processor necessary hardware is simplified to a piece of by the two panels in past, therefore it has the advantage that hardware configuration is simple, and volume is little, low in energy consumption;Hardware pins enriches, extension upgrading simplicity;Data link node is few, and reliability is high。

Accompanying drawing explanation

Fig. 1 is the structured flowchart of the present invention。

Detailed description of the invention

Below in conjunction with embodiment and with reference to accompanying drawing, the invention will be further described。

Refer to Fig. 1。

The present invention adopts FPGA to constitute signal processing device, fast development due to FPGA technology, the disposal ability making the FPGA device with data processing function has been over DSP device, and a piece of FPGA device thus can be used to complete over just being completed by DSP and FPGA two panels device of task;And due to FPGA pin enrich, pin can flexible allocation function, so no matter increase data bit width or reduce data bit width, it is only necessary to redistributing the pin of FPGA, it is not necessary to carry out the change of total system。

The hardware configuration of a kind of section sonar based on FPGA, receives unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and controls the signal processing unit based on FPGA of above-mentioned each unit:

Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit;

Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively;

Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit。

In the present invention, described sonar communication unit is made up of a piece of network chip W5300。

In the present invention, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, and the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit。

In the present invention, after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form。

Realize a kind of multiple beam section sonar signal processor based on high speed FPGA, the logical TCP/IP network control FPGA of main frame waterborne produces pulse signal, FPGA is carried out power amplification by power amplifier after producing analog waveform according to the Wave data write D/A that the order of main frame waterborne will be launched and be simulated signal condition by filter amplification circuit again, thus promoting transmitting transducer to launch signal, sent by transmitting transducer after the amplified conditioning of this signal, target receives transducer acoustic reflection tieback, the output signal receiving transducer processes by being transferred to FPGA Parallel signal processing part after collection of simulant signal hop collection, then again by process result with main frame in conducting water on TCP/IP latticed form;This process is controlled by TCP/IP network in real time by main frame waterborne, produces to control the synchronizing signal of collection of simulant signal hop while launching signal;Collection of simulant signal hop gathers echo-signal under the control of FPGA, and the data parallel collected is transferred to FPGA and processes in real time, and result is transferred to main frame waterborne by network and displays and store。

The signal processor of the present invention is installed on sonar and receives in transducer housing, and sonar transmission signal is transferred to transmitting transducer by cable by receiving transducer。

The present invention powers on after entrance duty, first starts main frame waterborne and enters aobvious prosecutor formula, then passes through network and set up the connection novel with book。

After connection establishment is got up, signal processing device can be carried out parameter configuration by main frame waterborne, as arranged range, arranges signal transmitter unit and launches power level signal, arrange the pulse width launching signal, arrange transmitting signal-pulse repetition frequency。

Workflow is: signal processor is upon receipt of starting order, then according to the parameter set, launch ping with certain pulsewidth and frequency。The impulse waveform of different length is stored in FPGA program in the form of data, the FPGA order according to main frame waterborne, this waveform data is delivered on data/address bus, these data are converted into waveform and give power amplifier amplification and launch by D/A, after coupling transmitting in 35kHz-65kHz, sound source level reaches 206dB, fluctuating 3dB in band。FPGA Parallel signal processing device gathers and does low-pass filtering taking-up envelope after signal carries out related operation with the copy launching signal again。The data of the data after initial data, correlation computations and envelope are both passed through network interface and deliver to main frame waterborne by FPGA signal processing。

The above is only the preferred embodiment of the present invention, is not intended to limit;Should be understood that, although the present invention being described in detail with reference to the various embodiments described above, it will be understood by those within the art that, the technical scheme described in the various embodiments described above still can be modified by it, or wherein some or all of technical characteristic carries out equivalent replacement;And these amendments and replacement, do not make the essence of corresponding technical scheme depart from the scope of various embodiments of the present invention technical scheme。

Claims (4)

1. the hardware configuration based on the section sonar of FPGA, it is characterized in that, receive unit and sonar transducer array including sonar communication unit, sonar signal transmitter unit, sonar signal and control the signal processing unit based on FPGA of above-mentioned each unit:
Sonar communication unit is connected with signal processing unit, signal processing unit connects sonar signal transmitter unit, sonar signal transmitter unit connects sonar transducer battle array, and sonar transducer battle array connects sonar signal and receives unit, and sonar signal receives unit and connects signal processing unit;
Described sonar signal transmitter unit includes D/A change-over circuit and amplification driving circuit, and signal processing unit is connected to sonar transducer battle array through D/A change-over circuit, amplification driving circuit successively;
Described sonar signal receives unit and includes A/D change-over circuit and filtering and amplifying circuit, and sonar transducer battle array amplified filter circuit successively, A/D change-over circuit are connected to signal processing unit。
2. the hardware configuration of a kind of section sonar based on FPGA according to claim 1, it is characterised in that described sonar communication unit is made up of a piece of network chip W5300。
3. the hardware configuration of a kind of section sonar based on FPGA according to claim 2, it is characterized in that, the hardware configuration of described section sonar is received the control command of water surface unit by network chip W5300, the control information of W5300 is input to signal processing unit, and signal processing unit is operated according to the instruction of water surface unit。
4. the hardware configuration of a kind of section sonar based on FPGA according to claim 3, it is characterised in that after data process terminates, data result is uploaded to main frame waterborne by W5300 via TCP/IP latticed form。
CN201610152898.3A 2016-03-17 2016-03-17 Chirp sonar hardware structure CN105699956A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106802419A (en) * 2017-01-23 2017-06-06 中海石油环保服务(天津)有限公司 It is a kind of that oily recognition methods and system are sunk to the bottom based on sonar image feature

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201043997Y (en) * 2007-03-01 2008-04-02 中国海洋石油总公司 Multi-beam section plane sonar signal processing device
CN103472250A (en) * 2013-08-22 2013-12-25 浙江工业大学 Signal processing system based on FPGA (Field Programmable Gate Array) of acoustic Doppler current profiler
WO2014204236A1 (en) * 2013-06-20 2014-12-24 동명대학교 산학협력단 Sonar sensor and sonar system equipped with same
GB2516292A (en) * 2013-07-18 2015-01-21 Thales Holdings Uk Plc Navigation sonar
CN104808211A (en) * 2014-12-12 2015-07-29 南阳理工学院 Detector for measuring swimming path of fishes
CN205404798U (en) * 2016-03-17 2016-07-27 天津海之星海洋科技发展有限公司 Hardware architecture of section sonar

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201043997Y (en) * 2007-03-01 2008-04-02 中国海洋石油总公司 Multi-beam section plane sonar signal processing device
WO2014204236A1 (en) * 2013-06-20 2014-12-24 동명대학교 산학협력단 Sonar sensor and sonar system equipped with same
GB2516292A (en) * 2013-07-18 2015-01-21 Thales Holdings Uk Plc Navigation sonar
CN103472250A (en) * 2013-08-22 2013-12-25 浙江工业大学 Signal processing system based on FPGA (Field Programmable Gate Array) of acoustic Doppler current profiler
CN104808211A (en) * 2014-12-12 2015-07-29 南阳理工学院 Detector for measuring swimming path of fishes
CN205404798U (en) * 2016-03-17 2016-07-27 天津海之星海洋科技发展有限公司 Hardware architecture of section sonar

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106802419A (en) * 2017-01-23 2017-06-06 中海石油环保服务(天津)有限公司 It is a kind of that oily recognition methods and system are sunk to the bottom based on sonar image feature
CN106802419B (en) * 2017-01-23 2019-10-08 中海石油环保服务(天津)有限公司 It is a kind of that oily recognition methods and system are sunk to the bottom based on sonar image feature

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Application publication date: 20160622