CN205375063U - Programmable logic controler and control system thereof - Google Patents
Programmable logic controler and control system thereof Download PDFInfo
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- CN205375063U CN205375063U CN201620149361.7U CN201620149361U CN205375063U CN 205375063 U CN205375063 U CN 205375063U CN 201620149361 U CN201620149361 U CN 201620149361U CN 205375063 U CN205375063 U CN 205375063U
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Abstract
The utility model provides a programmable logic controler and control system thereof, wherein the controller is including the big dipper receiving antenna, frequency conversion amplifier, big dipper RDSS chip, "Data analysis" ware and the data processor that connect gradually, big dipper receiving antenna receives the big dipper satellite signal that comes from control terminal, the frequency conversion amplifier enlargies the frequency conversion to big dipper satellite signal to be handled, obtains big dipper baseband signal, big dipper RDSS chip carries out analog -to -digital conversion and demodulation processing to big dipper baseband signal, obtains the baseband signal data, the analytic baseband signal data of "Data analysis" ware are with analytic data transmission to the data processor who obtains, data processor carries out corresponding operation according to the analytic data that obtain. The utility model provides a PLC can need not to lay the circuit through wireless control's mode work as the controlled device, and can alleviate PLC has the line traffic control during operation as the controlled device, and line arrangement is complicated, the big defect of the degree of difficulty is implemented to the circuit.
Description
Technical field
This utility model relates to electronic devices and components field, particularly relates to a kind of programmable logic controller (PLC) and control system thereof.
Background technology
PLC (ProgrammableLogicController, programmable logic controller (PLC)) is as a kind of electronic device being specifically designed to industrial control field, owing to its programming is simple, powerful, strong adaptability, high reliability are used widely.
At present, existing PLC can only adopt the mode of line traffic control to work as controlled device, specifically: control equipment such as industrial control computer, higher level PLC etc. by Peripheral Interface and current PLC wired connection, send work order to current PLC, current PLC work is controlled.
PLC adopts as controlled device has the mode of line traffic control to work, it is necessary to lay special communication line, has line arrangement complexity, circuit implements the big defect of difficulty.
Utility model content
This utility model provides programmable logic controller (PLC) and control system thereof, PLC can be worked by the mode of controlled in wireless as controlled device, without laying circuit, it is possible to when alleviation PLC has line traffic control to work as controlled device, line arrangement is complicated, circuit implements the defect that difficulty is big.
First aspect, this utility model embodiment provides a kind of programmable logic controller (PLC), and described controller includes Big Dipper reception antenna, frequency conversion amplifier, Big Dipper RDSS chip, data parser and data processor；
The outfan of described Big Dipper reception antenna is connected with the input of described frequency conversion amplifier, for receiving from the Big Dipper satellite signal controlling terminal, and sends the described Big Dipper satellite signal received to described frequency conversion amplifier；
The outfan of described frequency conversion amplifier is connected with the input of described Big Dipper RDSS chip, for described Big Dipper satellite signal is amplified frequency-conversion processing, obtains Big Dipper baseband signal, and sends described Big Dipper baseband signal to described Big Dipper RDSS chip；
Described first outfan of Big Dipper RDSS chip is connected with the input of described data parser, for described Big Dipper baseband signal is carried out analog digital conversion and demodulation process, obtains baseband signal data, and sends described baseband signal data to described data parser；
The outfan of described data parser is connected with the input of described data processor, is used for resolving described baseband signal data, and sends resolving the data obtained to described data processor；
Described data processor operates accordingly for the data obtained according to described parsing.
In conjunction with first aspect, this utility model embodiment provides the first possible embodiment of first aspect, and wherein, described frequency conversion amplifier includes low-noise amplifier and low-converter；
The input of described low-noise amplifier is connected with the outfan of described Big Dipper reception antenna；The outfan of described low-noise amplifier is connected with the input of described low-converter；Described low-noise amplifier is used for amplifying described Big Dipper satellite signal, and sends the described Big Dipper satellite signal after amplifying to described low-converter；
The outfan of described low-converter is connected with the input of described Big Dipper RDSS chip, for the described Big Dipper satellite signal after amplifying is carried out down conversion process, obtains described Big Dipper baseband signal, and sends described Big Dipper baseband signal to described Big Dipper RDSS chip.
In conjunction with first aspect, this utility model embodiment provides the embodiment that first aspect the second is possible, and wherein, described Big Dipper RDSS chip includes analog-digital converter and RDSS signal processing chip；
The input of described analog-digital converter is connected with the outfan of described frequency conversion amplifier；The outfan of described analog-digital converter is connected with the input of described RDSS signal processing chip；Described analog-digital converter, for described Big Dipper baseband signal is carried out analog digital conversion, obtains digitized Big Dipper baseband signal；
The outfan of described RDSS signal processing chip is connected with the input of described data parser, for catching described digitized Big Dipper baseband signal, it is demodulated described digitized Big Dipper baseband signal processing, obtain described baseband signal data, and described baseband signal data is sent to described data parser.
In conjunction with first aspect, this utility model embodiment provides the third possible embodiment of first aspect, and wherein, described data parser includes instruction analysis chip and/or time service analysis chip；
The input of described instruction analysis chip is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described instruction analysis chip is connected with the input of described data processor；Described instruction analysis chip is used for resolving described baseband signal data, obtains control instruction, and sends described control instruction to described data processor；
The input of described time service analysis chip is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described time service analysis chip is connected with the input of described data processor；Described time service analysis chip is used for resolving described baseband signal data, obtains time service information, and sends described time service information to described data processor；
Described data processor is used for operating accordingly according to described control instruction, and/or, carry out time service process according to described time service information.
In conjunction with first aspect, this utility model embodiment provides the 4th kind of possible embodiment of first aspect, wherein, described controller also includes I/O interface, the input of described I/O interface is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described I/O interface is connected with the input of described data parser；
The described baseband signal data that Big Dipper RDSS chip described in described I/O interface sends, and described baseband signal data is forwarded to described data parser.
In conjunction with the 4th kind of possible embodiment of first aspect, this utility model embodiment provides the 5th kind of possible embodiment of first aspect, and wherein, described controller also includes spread spectrum amplifier and Big Dipper transmitting antenna；
Described I/O interface is from the RDSS message of user, and sends described RDSS message to described Big Dipper RDSS chip；
Second outfan of described Big Dipper RDSS chip is connected with the input of described spread spectrum amplifier, for described RDSS message is modulated and digital-to-analogue conversion process, generate the transmitting baseband signal for launching, and by described transmitting baseband signal transmission to described spread spectrum amplifier；
The outfan of described spread spectrum amplifier is connected with the input of described Big Dipper transmitting chip, for described transmitting baseband signal is carried out spread spectrum processing and amplifying, obtain Big Dipper signal to be sent, and described Big Dipper signal to be sent is launched by described Big Dipper transmitting antenna.
In conjunction with the 5th kind of possible embodiment of first aspect, this utility model embodiment provides the 6th kind of possible embodiment of first aspect, and wherein, described spread spectrum amplifier includes manipulator and power amplifier；
The input of described manipulator is connected with the second outfan of described Big Dipper RDSS chip, the outfan of described manipulator is connected with the input of described power amplifier, described manipulator for carrying out spread processing to described transmitting baseband signal, and sends the described transmitting baseband signal after spread spectrum to described power amplifier；
The outfan of described power amplifier is connected with the input of described Big Dipper transmitting antenna, for the described transmitting baseband signal after spread spectrum is carried out power amplification process, obtain described Big Dipper signal to be sent, and described Big Dipper signal to be sent is launched by described Big Dipper transmitting antenna.
In conjunction with the 5th kind of possible embodiment of first aspect, this utility model embodiment provides the 7th kind of possible embodiment of first aspect, and wherein, described controller also includes the RDSS Message Entry Device being connected with described I/O interface.
In conjunction with the 5th kind of possible embodiment of first aspect, this utility model embodiment provides the 8th kind of possible embodiment of first aspect, wherein, described I/O interface includes wireless communication interface, and described wireless communication interface is for receiving the described RDSS message from user.
Second aspect, this utility model embodiment provides a kind of PLC controls system, described system first aspect, first aspect the first to the controller in the 8th kind of possible embodiment, also include controlling terminal；Described control terminal sends Big Dipper satellite signal to described controller.
In this utility model embodiment, by arranging interconnective Big Dipper reception antenna, frequency conversion amplifier, Big Dipper RDSS chip, data parser and data processor inside programmable logic controller (PLC) PLC, make the PLC can wireless receiving Big Dipper satellite signal, and Big Dipper satellite signal is carried out the process such as frequency conversion amplification, analog digital conversion, demodulation, parsing, and operate accordingly according to resolving the data obtained.Therefore by the programmable logic controller (PLC) PLC in this utility model embodiment, can wireless receiving Big Dipper satellite signal, work under the control of Big Dipper satellite signal, without laying circuit, thus alleviating PLC when having line traffic control to work as controlled device, line arrangement is complicated, circuit implements the defect that difficulty is big.
Accompanying drawing explanation
In order to be illustrated more clearly that the technical scheme of this utility model embodiment, the accompanying drawing used required in embodiment will be briefly described below, it is to be understood that, the following drawings illustrate only some embodiment of the present utility model, therefore the restriction to scope it is not construed as, for those of ordinary skill in the art, under the premise not paying creative work, it is also possible to obtain other relevant accompanying drawings according to these accompanying drawings.
Fig. 1 illustrates the first structural representation of the programmable logic controller (PLC) that this utility model embodiment provides；
Fig. 2 illustrates the second structural representation of the programmable logic controller (PLC) that this utility model embodiment provides；
Fig. 3 illustrates the third structural representation of the programmable logic controller (PLC) that this utility model embodiment provides；
Fig. 4 illustrates the structural representation of the programmable logic control system that this utility model embodiment provides.
Detailed description of the invention
For making the purpose of this utility model embodiment, technical scheme and advantage clearly, below in conjunction with accompanying drawing in this utility model embodiment, technical scheme in this utility model embodiment is clearly and completely described, obviously, described embodiment is only a part of embodiment of this utility model, rather than whole embodiments.Generally can with various different configurations arrange and design with the assembly of this utility model embodiment that illustrate described in accompanying drawing herein.Therefore, below the detailed description of the embodiment of the present utility model provided in the accompanying drawings is not intended to limit claimed scope of the present utility model, but is merely representative of selected embodiment of the present utility model.Based on embodiment of the present utility model, the every other embodiment that those skilled in the art obtain under the premise not making creative work, broadly fall into the scope of this utility model protection.
Consider that existing PLC can only adopt the mode of line traffic control to work as controlled device, need to lay special communication line, there is line arrangement complexity, circuit implements the defect that difficulty is big, this utility model provides programmable logic controller (PLC) and control system thereof, PLC is internally provided with Big Dipper RDSS (RadioDeterminationSatelliteService, radiodetermination-satellite service) business module (being also called Big Dipper RDSS chip), PLC is as controlled device wireless receiving Big Dipper satellite signal, work under the control of Big Dipper satellite signal, without laying circuit, PLC can be alleviated when having line traffic control to work as controlled device, line arrangement is complicated, circuit implements the defect that difficulty is big.It is specifically described below in conjunction with embodiment and accompanying drawing, wherein, the input of all not shown each electronic device of each accompanying drawing and outfan.
With reference to programmable logic controller (PLC) as shown in Figure 1, this controller includes Big Dipper reception antenna 11, frequency conversion amplifier 12, Big Dipper RDSS chip 13, data parser 14 and data processor 15；
The outfan of Big Dipper reception antenna 11 is connected with the input of frequency conversion amplifier 12, for receiving from the Big Dipper satellite signal controlling terminal, and sends the Big Dipper satellite signal received to frequency conversion amplifier 12；
The outfan of frequency conversion amplifier 12 is connected with the input of Big Dipper RDSS chip 13, for Big Dipper satellite signal is amplified frequency-conversion processing, obtains Big Dipper baseband signal, and sends Big Dipper baseband signal to Big Dipper RDSS chip 13；
First outfan of Big Dipper RDSS chip 13 is connected with the input of data parser 14, for Big Dipper baseband signal is carried out analog digital conversion and demodulation process, obtains baseband signal data, and sends baseband signal data to data parser 14；
The outfan of data parser 14 is connected with the input of data processor 15, is used for resolving baseband signal data, and sends resolving the data obtained to data processor 15；
Data processor 15 operates accordingly for the data obtained according to parsing.
In this utility model embodiment, by arranging interconnective Big Dipper reception antenna 11, frequency conversion amplifier 12, Big Dipper RDSS chip 13, data parser 14 and data processor 15 inside programmable logic controller (PLC) PLC, make the PLC can wireless receiving Big Dipper satellite signal, and Big Dipper satellite signal is carried out the process such as frequency conversion amplification, analog digital conversion, demodulation, parsing, and operate accordingly according to resolving the data obtained.Therefore by the programmable logic controller (PLC) PLC in this utility model embodiment, can wireless receiving Big Dipper satellite signal, work under the control of Big Dipper satellite signal, without laying circuit, thus alleviating PLC when having line traffic control to work as controlled device, line arrangement is complicated, circuit implements the defect that difficulty is big.
In the present embodiment, Big Dipper reception antenna 11 can be 1, it is also possible to for multiple.When Big Dipper reception antenna is multiple, its arrangement mode can arrange for square array, it is also possible to arranges for circular array.Big-dipper satellite antenna 11 be able to receive that from control terminal Big Dipper satellite signal basis on, its quantity and arrangement mode are not specifically limited by the present embodiment, and its quantity and arrangement mode can determine according to actual condition demand.
With reference to the programmable logic controller (PLC) shown in Fig. 2, in this controller, frequency conversion amplifier 12 includes low-noise amplifier 121 and low-converter 122；The input of low-noise amplifier 121 is connected with the outfan of Big Dipper reception antenna 11；The outfan of low-noise amplifier 121 is connected with the input of low-converter 122；Low-noise amplifier 121 is used for amplifying Big Dipper satellite signal, and sends the Big Dipper satellite signal after amplifying to low-converter 122；The outfan of low-converter 122 is connected with the input of Big Dipper RDSS chip 13, for the Big Dipper satellite signal after amplifying is carried out down conversion process, obtains above-mentioned Big Dipper baseband signal, and sends above-mentioned Big Dipper baseband signal to Big Dipper RDSS chip 13.
Specifically, the Big Dipper satellite signal received due to Big Dipper reception antenna 11 is all fainter, directly to its analyzing and processing, therefore the connection of low-noise amplifier 121 and Big Dipper reception antenna 11 can not be set, amplifies faint Big Dipper satellite signal by low-noise amplifier 121.Owing to the Big Dipper satellite signal after amplifying also needs to carry out down conversion process, therefore arrange low-converter 122 to be connected with low-noise amplifier 121, by low-converter 122, the Big Dipper satellite signal after amplifying is carried out down conversion process, obtain the Big Dipper baseband signal that can be identified by Big Dipper RDSS chip 13.Big Dipper baseband signal is also sent to Big Dipper RDSS chip 13 by low-converter 122, to carry out follow-up demodulation process.In this utility model embodiment, by arranging interconnective low-noise amplifier 121 and low-converter 122, and low-noise amplifier 121 is set is connected with Big Dipper reception antenna 11, low-converter 122 is connected with Big Dipper RDSS chip 13, the Big Dipper satellite signal received can be sequentially carried out amplification and down conversion process, thus obtaining the Big Dipper baseband signal that can be identified by Big Dipper RDSS chip 13, and Big Dipper baseband signal is sent to Big Dipper RDSS chip 13, to carry out follow-up demodulation process.
With reference to the programmable logic controller (PLC) shown in Fig. 2, in this controller, Big Dipper RDSS chip 13 includes analog-digital converter 131 and RDSS signal processing chip 132；The input of analog-digital converter 131 is connected with the outfan of frequency conversion amplifier 12；The outfan of analog-digital converter 131 is connected with the input of RDSS signal processing chip 132；Analog-digital converter 131, for Big Dipper baseband signal is carried out analog digital conversion, obtains digitized Big Dipper baseband signal；The outfan of RDSS signal processing chip 132 is connected with the input of data parser 14, for catching above-mentioned digitized Big Dipper baseband signal, it is demodulated digitized Big Dipper baseband signal processing, obtain above-mentioned baseband signal data, and above-mentioned baseband signal data is sent to data parser 14.
Specifically, owing to RDSS signal processing chip 132 can only process digital electric signal, and the Big Dipper baseband signal of frequency conversion amplifier 12 output is analog electrical signal, therefore arrange analog-digital converter 131 to be connected with frequency conversion amplifier 12, by analog-digital converter 131, Big Dipper baseband signal is carried out analog digital conversion, obtain digitized Big Dipper baseband signal.Owing to digitized Big Dipper baseband signal cannot be directly used to resolve, need demodulated, therefore arrange RDSS signal processing chip 132 to be connected with analog-digital converter 131, above-mentioned digitized Big Dipper baseband signal is obtained by RDSS signal processing chip 132, it is demodulated digitized Big Dipper baseband signal processing, obtain above-mentioned baseband signal data, and above-mentioned baseband signal data is sent to data parser 14, so that data parser 14 resolves baseband signal data.In the present embodiment, by arranging interconnective analog-digital converter 131 and RDSS signal processing chip 132, and analog-digital converter 131 is set is connected with frequency conversion amplifier 12, the connection of RDSS signal processing chip 132 and data parser 14, Big Dipper baseband signal can be demodulated, obtain baseband signal data, it is simple to launch follow-up data parsing work.
In the present embodiment, data parser 14 includes instruction analysis chip and/or time service analysis chip；The input of instruction analysis chip is connected with the first outfan of Big Dipper RDSS chip 13, and the outfan of instruction analysis chip is connected with the input of data processor 15；Instruction analysis chip is used for resolving above-mentioned baseband signal data, obtains control instruction, and sends control instruction to data processor 15；The input of time service analysis chip is connected with the first outfan of Big Dipper RDSS chip 13, and the outfan of time service analysis chip is connected with the input of data processor 15；Time service analysis chip is used for resolving baseband signal data, obtains time service information, and sends time service information to data processor 15；Data processor 15 is used for operating accordingly according to control instruction, and/or, carry out time service process according to time service information.
Specifically, control the Big Dipper satellite signal of terminal transmission carries in control instruction and time service information one or more.In a kind of situation, data parser 14 includes above-mentioned instruction analysis chip, above-mentioned baseband signal data can be resolved by above-mentioned instruction analysis chip, obtain control instruction, and control instruction is sent to data processor 15, data processor 15 operates accordingly according to control instruction, so that PLC works under the control controlling terminal.In another kind of situation, data parser 14 includes above-mentioned time service analysis chip, above-mentioned baseband signal data can be resolved by above-mentioned time service analysis chip, obtain time service information, and time service information is sent to data processor 15, data processor 15 carries out time service process according to time service information, so that PLC unified time service under the control controlling terminal.
With reference to the programmable logic controller (PLC) shown in Fig. 2, in this controller, data parser 14 includes above-mentioned instruction analysis chip and above-mentioned time service analysis chip simultaneously, i.e. instruction analysis chip 141 and time service analysis chip 142, instruction analysis chip 141 is connected with Big Dipper RDSS core 13 and data processor 15 respectively, and time service analysis chip 142 is connected with Big Dipper RDSS chip 13 and data processor 15 respectively.In this utility model embodiment, by arranging instruction analysis chip 141 and time service analysis chip 142, and instruction analysis chip 141 is set is connected with Big Dipper RDSS core 13 and data processor 15 respectively, time service analysis chip 142 is connected with Big Dipper RDSS chip 13 and data processor 15 respectively, can resolve and obtain control instruction and time service information, and control instruction and time service information are sent to data processor 15, so that PLC works under the control controlling terminal, and unified time service under the control controlling terminal.
With reference to the programmable logic controller (PLC) shown in Fig. 2, in this controller, the first outfan of the input and Big Dipper RDSS chip 13 that also include I/O interface 16, I/O interface 16 is connected, and the outfan of I/O interface 16 is connected with the input of data parser 14；I/O interface 16 receives the baseband signal data that Big Dipper RDSS chip 13 sends, and baseband signal data is forwarded to data parser 14.In the present embodiment, by arranging I/O interface 16 between Big Dipper RDSS chip 13 and data parser 14, utilize I/O interface 16 can facilitate transmission baseband signal data between Big Dipper RDSS chip 13 and data parser 14.
Considering that user sends message possibly through PLC device to controlling terminal, with reference to programmable logic controller (PLC) as shown in Figure 2, this controller also includes spread spectrum amplifier 17 and Big Dipper transmitting antenna 18；I/O interface 16 receives the RDSS message from user, and sends RDSS message to Big Dipper RDSS chip 13；Second outfan of Big Dipper RDSS chip 13 is connected with the input of spread spectrum amplifier 17, for RDSS message is modulated and digital-to-analogue conversion process, generates the transmitting baseband signal for launching, and by transmitting baseband signal transmission to spread spectrum amplifier 17；The outfan of spread spectrum amplifier 17 is connected with the input of Big Dipper transmitting chip 18, for transmitting baseband signal is carried out spread spectrum processing and amplifying, obtains Big Dipper signal to be sent, and is launched by Big Dipper transmitting antenna 18 by Big Dipper signal to be sent.
Specifically, RDSS message is sent to I/O interface 16 by user, RDSS message is forwarded to Big Dipper RDSS chip 13 by I/O interface 16, Big Dipper RDSS chip 13 includes RDSS signal processing chip 132 and digital to analog converter 133, and digital to analog converter 133 is connected with RDSS signal processing chip 132 and spread spectrum amplifier 17 respectively.RDSS signal processing chip 132 is for being modulated message, and sends the message after modulation to digital to analog converter 133, and digital to analog converter 133 is for changing into digital signal by the message after modulation, thus obtaining transmitting baseband signal.Digital to analog converter 133 is also by transmitting baseband signal transmission to spread spectrum amplifier 17.Transmitting baseband signal is carried out spread spectrum processing and amplifying by spread spectrum amplifier 17, obtain Big Dipper signal to be sent, and Big Dipper signal to be sent is sent to Big Dipper transmitting antenna 18, Big Dipper signal to be sent is sent to controlling terminal by Big Dipper transmitting antenna 18, thus reaching to send the purpose of user-defined message.In this utility model embodiment, by arranging spread spectrum amplifier 17 and Big Dipper transmitting antenna 18, it is possible to be easy to user and outwardly send self-defining message content.
With reference to programmable logic controller (PLC) as shown in Figure 2, in this controller, spread spectrum amplifier 17 includes manipulator 171 and power amplifier 172；The input of manipulator 171 is connected with the second outfan of Big Dipper RDSS chip 13, the outfan of manipulator 171 is connected with the input of power amplifier 172, manipulator 171 for carrying out spread processing to transmitting baseband signal, and sends the transmitting baseband signal after spread spectrum to power amplifier 172；The outfan of power amplifier 172 is connected with the input of Big Dipper transmitting antenna 18, for the transmitting baseband signal after spread spectrum is carried out power amplification process, obtain above-mentioned Big Dipper signal to be sent, and above-mentioned Big Dipper signal to be sent is launched by Big Dipper transmitting antenna 18.
Specifically, message owing to launching needs through first passing through spread processing then through processing and amplifying, therefore interconnective manipulator 171 and power amplifier 172 are set, manipulator 171 receives the transmitting baseband signal of Big Dipper RDSS chip 13 output, transmitting baseband signal is carried out spread processing, and the transmitting baseband signal after spread spectrum is sent to power amplifier 172.Power amplifier 172 amplifies the transmitting baseband signal after spread spectrum, obtains above-mentioned Big Dipper signal to be sent, and sends Big Dipper signal to be sent to Big Dipper transmitting antenna 18, is launched by Big Dipper transmitting antenna 18.In the present embodiment, by arranging manipulator 171 and power amplifier 172, it is possible to transmitting baseband signal is carried out spread spectrum processing and amplifying, thus obtaining Big Dipper signal to be sent.
Consider that user needs incoming message, therefore the programmable logic controller (PLC) in the present embodiment also includes the RDSS Message Entry Device that is connected with I/O interface 16, RDSS Message Entry Device can be keyboard or contact panel, and user uses the RDSS Message Entry Device can incoming message content.
Considering the extensive use of radio communication, the I/O interface 16 in the present embodiment includes wireless communication interface, and this wireless communication interface is for receiving the RDSS message from user.Such as, user edits after message content on personal terminal, it is possible to by the mode of wireless transmission, message being sent the wireless communication interface to I/O interface 16, it is convenient flexibly that employing wirelessly sends message.
As in figure 2 it is shown, in programmable logic controller (PLC) in this enforcement, Big Dipper RDSS chip 13 also includes Big Dipper card 134.Programmable logic controller (PLC) in this enforcement also includes the configuration interface 19 being connected with I/O interface, and user can configure original state and the operating parameter information of Big Dipper RDSS chip 13 by configuring interface 19.
In practical application, above-mentioned data processor 15 can replace with existing programmable logic controller (PLC), with reference to programmable logic controller (PLC) as shown in Figure 3, wherein data processor 15 includes CPU (CentralProcessingUnit, central processing unit) 151, input block 152, output unit 153, power supply 154, Peripheral Interface 155, memorizer 156 and I/O expansion interface 157.Wherein, CPU151 is connected with input block 152, output unit 153, power supply 154, Peripheral Interface 155, memorizer 156 and I/O expansion interface 157 respectively, and power supply 154 is for powering for programmable logic controller (PLC).
In Fig. 3, CPU151 is as the core of whole PLC.The function of CPU151 has: diagnose the duty of power supply, PLC internal circuit, checks the syntax error of programming, reads user program and explains and perform, execution result is delivered to outfan.Memorizer 156 mainly includes two kinds: one is readable and writable memory, and another kind is static memory.In PLC, memorizer is mainly used in storage system program, user program and operational data, and wherein operational data is stored in readable and writable memory, and system program, user program leave in static memory.Input block 152, output unit 153, generally also referred to as I/O unit or I/O module, are the connection members between PLC and industrial site.PLC can detect the various data of controlled device by input block 152, using these data as the PLC foundation that control target is controlled.Result is given control target by output unit 153 by PLC, to realize controlling purpose.PLC is furnished with multiple Peripheral Interface 155, and Peripheral Interface 155 is general all with communication processor.PLC can realize communicating with monitor, printer, other equipment such as PLC, computer by these Peripheral Interfaces 155.
The work process of the programmable logic controller (PLC) in Fig. 3 includes following components.
Part I is a powering up processing.System is once initialized after powering on by PLC, including hardware initialization and software initialization, has a power failure and keeps range set and other initialization process etc..
Part II is that self diagnosis processes.The every run-down of PLC, performs time self diagnosis inspection, it is determined that whether the action of PLC self is normal.Such as the whether exception such as CPU, cell voltage, program storage, I/O and communication or make mistakes, during as checked abnormal, LED and abnormal relay on CPU panel can be connected, and can be stored in error codes in specified register.When there is fatal error, CPU is forced STOP mode, and all of scanning just stops.
Part III is Communications service.PLC self diagnosis has processed and has subsequently entered Communications service process.First check for, with or without communication task, if any then receiving the Big Dipper satellite signal that dipper system sends, and calling corresponding process, completing the Communication processing with other equipment, and communication data is handled accordingly, then carry out the work such as clock, specified register renewal process.
Part IV is program scanning process.PLC is after upper electric treatment, self diagnosis and Communications service complete, if working selecting switch is in RUN position, then enters people's program scanning working stage.First complete input processing, namely the state of input terminal is read in input image register, then perform user program, finally output processing result is flushed in output latch.
Based on programmable logic controller (PLC) described above, this enforcement additionally provides a kind of PLC controls system, and as shown in Figure 4, this system includes above-mentioned programmable logic controller (PLC), also includes controlling terminal 41；Control terminal 41 for sending Big Dipper satellite signal to programmable logic controller (PLC).
By the PLC controls system in this utility model embodiment, Big Dipper satellite signal can be sent to programmable logic controller (PLC), Big Dipper satellite signal carries control instruction and time service information, thus the work of remote wireless control programmable logic controller (PLC), and carry out unifying time service for it.
To sum up, by the programmable logic controller (PLC) in this utility model embodiment and control system thereof, can wireless receiving Big Dipper satellite signal, work under the control of Big Dipper satellite signal, without laying circuit, thus alleviating PLC when having line traffic control to work as controlled device, line arrangement is complicated, circuit implements the defect that difficulty is big.
It should also be noted that similar label and letter below figure represent similar terms, therefore, once a certain Xiang Yi accompanying drawing is defined, then it need not be carried out definition further and explain in accompanying drawing subsequently, in addition, term " first ", " second ", " the 3rd " etc. are only used for distinguishing description, and it is not intended that indicate or hint relative importance.
Last it is noted that embodiment described above, it is only detailed description of the invention of the present utility model, in order to the technical solution of the utility model to be described, it is not intended to limit, protection domain of the present utility model is not limited thereto, although this utility model being described in detail with reference to previous embodiment, it will be understood by those within the art that: any those familiar with the art is in the technical scope that this utility model discloses, technical scheme described in previous embodiment still can be modified by it maybe can readily occur in change, or wherein portion of techniques feature is carried out equivalent replacement；And these amendments, change or replacement, do not make the essence of appropriate technical solution depart from the spirit and scope of this utility model embodiment technical scheme.All should be encompassed within protection domain of the present utility model.Therefore, protection domain of the present utility model should described be as the criterion with scope of the claims.
Claims (10)
1. a programmable logic controller (PLC), it is characterised in that described controller includes Big Dipper reception antenna, frequency conversion amplifier, Big Dipper RDSS chip, data parser and data processor；
The outfan of described Big Dipper reception antenna is connected with the input of described frequency conversion amplifier, for receiving from the Big Dipper satellite signal controlling terminal, and sends the described Big Dipper satellite signal received to described frequency conversion amplifier；
The outfan of described frequency conversion amplifier is connected with the input of described Big Dipper RDSS chip, for described Big Dipper satellite signal is amplified frequency-conversion processing, obtains Big Dipper baseband signal, and sends described Big Dipper baseband signal to described Big Dipper RDSS chip；
Described first outfan of Big Dipper RDSS chip is connected with the input of described data parser, for described Big Dipper baseband signal is carried out analog digital conversion and demodulation process, obtains baseband signal data, and sends described baseband signal data to described data parser；
The outfan of described data parser is connected with the input of described data processor, is used for resolving described baseband signal data, and sends resolving the data obtained to described data processor；
Described data processor operates accordingly for the data obtained according to described parsing.
2. controller according to claim 1, it is characterised in that described frequency conversion amplifier includes low-noise amplifier and low-converter；
The input of described low-noise amplifier is connected with the outfan of described Big Dipper reception antenna；The outfan of described low-noise amplifier is connected with the input of described low-converter；Described low-noise amplifier is used for amplifying described Big Dipper satellite signal, and sends the described Big Dipper satellite signal after amplifying to described low-converter；
The outfan of described low-converter is connected with the input of described Big Dipper RDSS chip, for the described Big Dipper satellite signal after amplifying is carried out down conversion process, obtains described Big Dipper baseband signal, and sends described Big Dipper baseband signal to described Big Dipper RDSS chip.
3. controller according to claim 1, it is characterised in that described Big Dipper RDSS chip includes analog-digital converter and RDSS signal processing chip；
The input of described analog-digital converter is connected with the outfan of described frequency conversion amplifier；The outfan of described analog-digital converter is connected with the input of described RDSS signal processing chip；Described analog-digital converter, for described Big Dipper baseband signal is carried out analog digital conversion, obtains digitized Big Dipper baseband signal；
The outfan of described RDSS signal processing chip is connected with the input of described data parser, for catching described digitized Big Dipper baseband signal, it is demodulated described digitized Big Dipper baseband signal processing, obtain described baseband signal data, and described baseband signal data is sent to described data parser.
4. controller according to claim 1, it is characterised in that described data parser includes instruction analysis chip and/or time service analysis chip；
The input of described instruction analysis chip is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described instruction analysis chip is connected with the input of described data processor；Described instruction analysis chip is used for resolving described baseband signal data, obtains control instruction, and sends described control instruction to described data processor；
The input of described time service analysis chip is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described time service analysis chip is connected with the input of described data processor；Described time service analysis chip is used for resolving described baseband signal data, obtains time service information, and sends described time service information to described data processor；
Described data processor is used for operating accordingly according to described control instruction, and/or, carry out time service process according to described time service information.
5. controller according to claim 1, it is characterized in that, described controller also includes I/O interface, and the input of described I/O interface is connected with the first outfan of described Big Dipper RDSS chip, and the outfan of described I/O interface is connected with the input of described data parser；
The described baseband signal data that Big Dipper RDSS chip described in described I/O interface sends, and described baseband signal data is forwarded to described data parser.
6. controller according to claim 5, it is characterised in that described controller also includes spread spectrum amplifier and Big Dipper transmitting antenna；
Described I/O interface is from the RDSS message of user, and sends described RDSS message to described Big Dipper RDSS chip；
Second outfan of described Big Dipper RDSS chip is connected with the input of described spread spectrum amplifier, for described RDSS message is modulated and digital-to-analogue conversion process, generate the transmitting baseband signal for launching, and by described transmitting baseband signal transmission to described spread spectrum amplifier；
The outfan of described spread spectrum amplifier is connected with the input of described Big Dipper transmitting chip, for described transmitting baseband signal is carried out spread spectrum processing and amplifying, obtain Big Dipper signal to be sent, and described Big Dipper signal to be sent is launched by described Big Dipper transmitting antenna.
7. controller according to claim 6, it is characterised in that described spread spectrum amplifier includes manipulator and power amplifier；
The input of described manipulator is connected with the second outfan of described Big Dipper RDSS chip, the outfan of described manipulator is connected with the input of described power amplifier, described manipulator for carrying out spread processing to described transmitting baseband signal, and sends the described transmitting baseband signal after spread spectrum to described power amplifier；
The outfan of described power amplifier is connected with the input of described Big Dipper transmitting antenna, for the described transmitting baseband signal after spread spectrum is carried out power amplification process, obtain described Big Dipper signal to be sent, and described Big Dipper signal to be sent is launched by described Big Dipper transmitting antenna.
8. controller according to claim 6, it is characterised in that described controller also includes the RDSS Message Entry Device being connected with described I/O interface.
9. controller according to claim 6, it is characterised in that described I/O interface includes wireless communication interface, described wireless communication interface is for receiving the described RDSS message from user.
10. a PLC controls system, it is characterised in that described system includes the controller described in any one of claim 1 to 9, also includes controlling terminal；Described control terminal sends Big Dipper satellite signal to described controller.
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