CN219285624U - Analog output circuit and clamping piece - Google Patents
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- CN219285624U CN219285624U CN202222686272.4U CN202222686272U CN219285624U CN 219285624 U CN219285624 U CN 219285624U CN 202222686272 U CN202222686272 U CN 202222686272U CN 219285624 U CN219285624 U CN 219285624U
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Abstract
The embodiment of the utility model discloses an analog output circuit and a clamping piece, wherein the circuit comprises a micro control unit MCU which is arranged to send an instruction and receive feedback information about the instruction; the instruction and the feedback information are digital signals; a digital-to-analog converter DAC chip configured to convert the digital signal transmitted from the MCU into an analog signal and transmit the analog signal to the connected external HART device; the HART modem is arranged to perform HART communication with the HART equipment, acquire HART signals returned by the HART equipment, perform modem on the HART signals, acquire feedback information and send the feedback information to the MCU. By the embodiment scheme, the complexity of circuits and software is reduced, and the reliability of the circuits is improved.
Description
Technical Field
The utility model relates to a DCS design technology, in particular to an analog output circuit and a clamping piece.
Background
In EDPF-NT series DCS (Distributed Control System, english abbreviation of distributed control system), analog output structure with HART function: the current output circuit built by the first operational amplifier is used for current amplification after filtering, then the second operational amplifier circuit is used for current amplification, then the Field device is driven, the HART signal is demodulated and modulated by using the FPGA ((Field-Programmable Gate Array, field programmable gate array) together with software logic, and the requirements on software are high and the circuit is complex.
Disclosure of Invention
The embodiment of the utility model provides an analog output circuit and a clamping piece, which can reduce the complexity of the circuit and improve the reliability of the circuit.
The embodiment of the utility model provides an analog output circuit, which can comprise: the micro control unit MCU, the digital-to-analog converter DAC chip and the HART modem;
the instruction output end of the MCU is connected with the instruction input end of the DAC chip;
the analog signal output end of the DAC chip is connected with the analog signal input end of the external HART equipment;
the HART signal input end of the HART modem is connected with the HART signal output end of the HART equipment;
the feedback signal input end of the HART modem is connected with the feedback signal input end of the MCU.
In an exemplary embodiment of the utility model, the MCU is arranged to send instructions to the DAC chip;
the DAC chip is arranged to convert the instruction in the form of a digital signal sent by the MCU into an analog signal;
the HART modem is arranged to perform HART communication with the HART equipment to acquire a HART signal returned by the HART equipment; and modulating and demodulating the HART signal to obtain feedback information and sending the feedback information to the MCU.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: a first decoder; the number of the DAC chips is multiple, and each DAC chip is respectively connected with one HART device;
the serial peripheral interface SPI of the MCU is connected with the signal input end of the first decoder; the signal output end of the first decoder is connected with the instruction input ends of the DAC chips;
the first decoder is configured to implement a chip selection function on a plurality of DAC chips according to a chip selection signal included in the SPI signal;
and the DAC chip is arranged to receive the instruction sent by the MCU after being selected, and couple the converted analog signal to a current loop to be output to the connected HART device.
In an exemplary embodiment of the present utility model, the command input terminal of the HART modem is connected to the UART output interface of the universal asynchronous receiver transmitter of the MCU; the HART signal output end of the HART modem is connected with the HART signal input end of the HART equipment;
the HART modem is configured to modulate an instruction in the form of a UART serial signal sent by the MCU, obtain a corresponding HART signal, and send the HART signal to the HART device.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: a second decoder and an analog switch; the HART modem is one; a HART modem corresponds to the plurality of analog switches through a second decoder;
the MCU is connected with the signal input end of the second decoder through an input/output I/O interface;
the signal output end of the second decoder is connected with the controlled end of the analog switch;
the first end of the analog switch is connected with the HART signal input end of the corresponding HART modem, and the second end of the analog switch is connected with the HART signal output end of the corresponding HART modem;
the second decoder is configured to control on-off of the analog switch, so that signals of a plurality of HART devices are scanned sequentially into the HART modem to be demodulated, and the HART modem receives the signals of the plurality of HART devices;
the analog switch is used for controlling the on-off of the HART signal input end and the HART signal output end of the corresponding HART equipment through the on-off control of the analog switch, so that the on-off between the HART modem and the HART equipment is controlled.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: a protection circuit; each DAC chip corresponds to one protection circuit respectively;
the DAC chip is further arranged to be connected with the HART device through the protection circuit.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: an isolation circuit; each DAC chip and each HART modem are respectively corresponding to an isolation circuit;
the DAC chip is connected with the MCU and the first decoder through the isolation circuit;
the HART modem is connected with the MCU through the isolation circuit.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: isolating the power module; each DAC chip corresponds to one isolation power supply module respectively;
the DAC chip is connected with the HART equipment through the isolated power module;
the isolated power supply module supplies power to the HART modem and the MCU respectively.
In an exemplary embodiment of the utility model, the DAC chip is a power DAC chip;
the DAC chip is realized by an SD2421 chip;
the HART modem is implemented using an SD2057 chip.
The embodiment of the utility model also provides an analog output clamping piece, which can comprise: the analog output circuit.
The analog output circuit of the embodiment of the utility model can comprise: the micro control unit MCU, the digital-to-analog converter DAC chip and the HART modem; the instruction output end of the MCU is connected with the instruction input end of the DAC chip; the analog signal output end of the DAC chip is connected with the analog signal input end of the external HART equipment; the HART signal input end of the HART modem is connected with the HART signal output end of the HART equipment; the feedback signal input end of the HART modem is connected with the feedback signal input end of the MCU. By the embodiment scheme, the complexity of the circuit is reduced, and the reliability of the circuit is improved.
Additional features and advantages of the utility model will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the utility model. The objectives and other advantages of the utility model may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the technical aspects of embodiments of the utility model, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the utility model and together with the embodiments of the utility model, not to limit the technical aspects of the utility model.
FIG. 1 is a block diagram of an analog output circuit according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of an SD2421 chip according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of an SD2057 chip according to an embodiment of the present utility model;
FIG. 4 is a schematic diagram illustrating connection between a first decoder and a second decoder according to an embodiment of the present utility model;
FIG. 5 is a schematic diagram showing connection of an analog output circuit according to an embodiment of the present utility model;
fig. 6 is a block diagram of an analog output card according to an embodiment of the present utility model.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present utility model more apparent, embodiments of the present utility model will be described in detail hereinafter with reference to the accompanying drawings. It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be arbitrarily combined with each other.
The embodiment of the utility model provides an analog output circuit A, as shown in FIG. 1, which can comprise: the micro control unit MCU1, the digital-analog converter DAC chip 2 and the HART modem 3;
the instruction output end of the MCU1 is connected with the instruction input end of the DAC chip 2;
the analog signal output end of the DAC chip 2 is connected with the analog signal input end of the external HART equipment 4;
the HART signal input end of the HART modem 3 is connected with the HART signal output end of the HART device 4;
the feedback signal input end of the HART modem 3 is connected with the feedback signal input end of the MCU1.
In an exemplary embodiment of the present utility model, the MCU1 may be configured to transmit an instruction and receive feedback information about the instruction; the instruction and the feedback information are digital signals;
a digital-to-analog converter DAC chip 2, which may be configured to convert a digital signal transmitted from the MCU1 into an analog signal and transmit the analog signal to the connected external HART device 4;
the HART modem 3 may be configured to perform HART communication with the HART device 4, obtain a HART signal returned by the HART device 4, perform modem on the HART signal, obtain the feedback information, and send the feedback information to the MCU1.
In an exemplary embodiment of the present utility model, the following disadvantages are found by analyzing the analog output structure with HART function in the DCS system of the EDPF-NT series:
1. the cabinet is many, and area is big: according to engineering statistics, the number of special relay cabinets required by a system of 300mw is 6 and 7, and the number of special relay cabinets required by a system of 600mw is more than ten except for the cabinet in which the controller is positioned;
for example, taking a 2×660MW engineering DCS system boiler electronic equipment room as an example, a #1 machine furnace side electronic room needs 25 main cabinets, 7 expansion cabinets and 6 relay cabinets; the #2 machine furnace side electronic room needs 20 main cabinets, 5 expansion cabinets and 5 relay cabinets.
2. The prefabricated cable is long, the connectors are more, and the reliability is lower.
3. The measuring points are unevenly distributed, and the relay cabinet is dense in cables.
4. The wiring is more, the cost is high, and the electric installation workload is large.
In the exemplary embodiment of the present utility model, the dedicated HART modem 3 is used to replace the original HART signal processing circuit (composed of the current output circuit, the current filtering circuit and the second operational amplifier built by the first operational amplifier), so that the complexity of the circuit and the software is reduced; the special DAC chip 2 is used for replacing the original current source circuit, so that the complexity of the circuit and software is reduced, and the current source circuit can be adapted to the existing project.
In the exemplary embodiment of the present utility model, DAC chip 2 is mainly responsible for the current output function of the analog output circuit, and is used for sending an analog current signal to external HART device 4; the HART modem 3 is mainly responsible for the modulation and demodulation of HART signals.
In the exemplary embodiment of the present utility model, the circuits originally built through a plurality of operational amplifiers and resistors and capacitors are integrated into the DAC chip, the HART modem logic originally implemented with the FPGA (Field-Programmable Gate Array, field programmable gate array) chip is replaced with the HART modem 3, and the HART modem 3 can convert the HART signal into a standard UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) signal for communication with the MCU, so that the FPGA chip is removed, and the software code is simplified.
In an exemplary embodiment of the present utility model, as shown in fig. 2, the DAC chip 2 may be a power-supplied DAC chip;
the DAC chip 2 may be implemented by an SD2421 chip and its peripheral circuits.
In the exemplary embodiment of the present utility model, the DAC chip 2 is powered by 24V, the power-supply DAC chip SD2421 can convert the command sent by the MCU through the SPI (Serial Peripheral Interface ) into a corresponding current value, and the current output range can be 4-20mA (in normal operation mode) at the loortn pin output.
In an exemplary embodiment of the present utility model, as shown in fig. 3, the HART modem 3 may be implemented using an SD2057 chip and its peripheral circuits.
In an exemplary embodiment of the present utility model, the HART modem 3 may convert the TTL (transistor transistor logic, transistor-transistor logic) level into a HART signal and output through a pin of a HART signal output terminal (HART-OUT); meanwhile, the HART signal input by a pin of an HART signal input terminal (HART-IN) can be converted into TTL level and sent to the MCU through TXD (Transmit Data); i.e. the physical layer implementation of the HART protocol. The HART modem logic which is built by the FPGA is integrated into the SD2057 chip, and the software only needs the MCU to send and receive the conventional UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter) signals to the SD2057 chip to realize communication, so that the complexity of software writing is greatly reduced.
In an exemplary embodiment of the present utility model, as shown in fig. 1, the MCU1 may transmit an instruction to the DAC chip 2, and the DAC chip 2 converts a digital signal transmitted from the MCU1 into an analog signal (HART signal) and transmits the analog signal to the connected external HART device 4; HART modem 3 communicates with HART device 4 to obtain HART signals transmitted back by HART device 4, and demodulates the HART signals to obtain feedback information (digital signals) and send the feedback information to MCU1.
In an exemplary embodiment of the present utility model, the MCU1 may include, but is not limited to, a single chip microcomputer.
In an exemplary embodiment of the present utility model, as shown in fig. 4 and 5, the analog output circuit may further include: a first decoder 51; the number of the DAC chips 2 is multiple, and each DAC chip 2 is respectively connected with one HART device 4;
the chip selection interface of the serial peripheral interface SPI interface of the MCU1 is connected with the signal input end of the first decoder 51; the signal output end of the first decoder 51 is connected with the instruction input ends of the DAC chips 2;
the MCU1 may be further configured to communicate with the DAC chip 2 through an SPI signal, implement a chip selection function for a plurality of the DAC chips 2 through the first decoder 51, and send the instruction to the selected DAC chip 2;
the first decoder 51 is configured to implement a chip selection function for the plurality of DAC chips 2 according to a chip selection signal included in the SPI signal;
the DAC chip 2 is configured to receive the instruction sent by the MCU after being selected, and couple the converted analog signal to the current loop and output the analog signal to the connected HART device 4.
In an exemplary embodiment of the present utility model, the DAC chip 2 may be an 8-way, i.e. an 8-way SD2421 chip, and each DAC chip 2 may be connected to an external HART device 4.
In an exemplary embodiment of the present utility model, the first decoder 51 may be a 3-8 decoder, and the first decoder 51 may be configured to implement a chip selection function according to a chip selection signal sent by the MCU1, so as to control on/off of DAC chips 2 of different paths, so that the 8-path DAC chips 2 are periodically and continuously switched.
In the exemplary embodiment of the present utility model, 3I/O ports are given by the MCU1 and input to the 3-8 decoder, 8 channels are selected by binary, for example, 3I/O ports give low and high levels, that is, 001, are binary 1, that is, the second channel is selected, and if high and low levels are given, that is, 101, that is, binary 5, that is, the 6 th channel is selected, so that 000-111, that is, binary 0-7, channels are selected by three I/O ports. In the exemplary embodiment of the present utility model, compared with the original HART circuit, the current output circuit built by the original first operational amplifier adopts a multi-module scheme of filtering by the filter circuit and amplifying the current by using the second operational amplifier circuit, integrates into the DAC chip SD2421, performs communication by using the universal communication mode SPI and realizes the chip selection function, thereby realizing the HART signal communication and AO (analog signal output) functions of 8 channels.
In the exemplary embodiment of the present utility model, when the MCU1 controls the 8-channel power DAC chip 2 through SPI communication, the 8-channel SPI shares SCK (synchronous clock line) and SDA (data line) for data transmission, and a CS (chip select) pin is used separately for each channel for enabling the communication function of each channel power DAC chip 2.
In an exemplary embodiment of the present utility model, the SPI signal of the MCU1 may send instructions to the 8 paths of SD2421 chips through a 3-8 decoder (the first decoder 51), respectively, the channels of 1-8 paths may be periodically and continuously switched, the SD2421 converts the digital signal sent by the MCU1 into a 4-20mA analog signal, and sends the 4-20mA analog signal to the HART device receiving the AO signal, the HART device 4 receives the analog signal and then returns data through HART communication, and the returned data is converted into a UART standard serial port communication signal that can be identified by the MCU1 and then sent to the MCU1 through the modulation and demodulation of the HART signal by the SD2057 chip.
In the exemplary embodiment of the present utility model, fig. 1 is a case of only 1 path, fig. 4 is a case of 8 paths, and a 3-8 decoder and an analog switch are added in the case of 8 paths, so that the MCU can scan 8 paths, and one MCU can control the input and output of the 8 paths of HART circuits.
In an exemplary embodiment of the present utility model, the command input terminal of the HART modem is connected to the UART output interface of the universal asynchronous receiver transmitter of the MCU; the HART signal output of the HART modem is connected to the HART signal input of the HART device.
In an exemplary embodiment of the present utility model, as shown in fig. 5, the HART modem 3 may be further configured to receive an instruction sent by the MCU1 through UART communication, modulate a UART (universal asynchronous receiver transmitter) serial port signal of the instruction, obtain a corresponding HART signal, and send the HART signal to the external HART device 4.
In an exemplary embodiment of the utility model, the analog signal may be a 4-20mA current signal and the HART signal is another form of digital signal.
In an exemplary embodiment of the present utility model, MCU1 is connected to a HART modem SD2057 via UART communication, SD2057 converts the modulated signals into HART signals which are transmitted to HART device 4 via wires.
In an exemplary embodiment of the present utility model, the HART modem 3 may be further configured to acquire a HART signal sent by the external HART device 4, and perform modem on the HART signal, so as to acquire the feedback information and send the feedback information to the MCU1.
In an exemplary embodiment of the present utility model, the HART modem 3 may convert an instruction (TTL level) sent by the MCU1 into a HART signal, and output the command after modulation and demodulation to the external HART device 4 through a HART-OUT pin; IN addition, the HART signal input from the HART-IN pin may be converted to TTL level and transmitted to the MCU1 through TXD.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: a second decoder 52 and an analog switch 6; the HART modems 3 are plural; a HART modem 3 corresponds to an analog switch 6;
the MCU1 is connected with the signal input end of the second decoder through input/output I/O interfaces (for example, 3);
the signal output end of the second decoder is connected with the controlled end of the analog switch;
the first end of the analog switch 6 is connected with the corresponding HART signal input end of the HART modem 3, and the second end of the analog switch 6 is connected with the corresponding HART signal output end of the HART modem 3;
the second decoder 52 is configured to control on/off of the analog switch 6 to select one HART modem 3 from the plurality of HART modems 3;
the analog switch 6 is configured to control on-off of the HART signal input end and the HART signal output end of the HART modem 3 according to on-off control of the analog switch, so as to control on-off between the HART modem 3 and the HART device 4.
In an exemplary embodiment of the present utility model, the second decoder 52 may be a 3-8 decoder, and the second decoder 52 may be configured to implement a channel selection function according to a channel selection signal sent by the MCU1, so as to control on/off of analog switches 6 corresponding to HART devices 4 in different ways, so that the HART devices 4 in 8 ways are mutually switched to be connected to a HART signal output end and a HART signal input end of the HART modem 3, and implement a HART signal transmission function.
In an exemplary embodiment of the present utility model, the first 3-8 decoder may be responsible for selecting an 8-way DAC chip and the second 3-8 decoder may be responsible for selecting a connection of an 8-way HART device to a HART modem.
In the exemplary embodiment of the present utility model, 8 DAC chips 2 are controlled by a first decoder (3-8 decoders), and 8 analog switches 6 connected to HART devices are controlled by a second decoder; the MCU controls the HART modem 3 and the DAC chip 2 respectively, and the HART modem 3 is not connected with the DAC chip 2.
In the exemplary embodiment of the present utility model, the SPI signal is used to communicate with the DAC chip 2, the chip select signal of the SPI is connected to the first 3-8 decoder to achieve communication with the 8-channel DAC chip, the HART signal output from the HART modem is connected to the external HART device 4 through an analog switch, the analog switch is connected to the MCU1 through the second 3-8 decoder, and the MCU1 can control the 8-channel analog switch only by using three general I/O pins.
In the exemplary embodiment of the present utility model, an analog switch 6 corresponds to an analog signal converted by a HART device 4,8 DACs, which is switched by the SPI signal of the MCU and the first 3-8 decoder, and an 8 HART signal is switched by the second 3-8 decoder in series with a plurality of analog switches.
In an exemplary embodiment of the present utility model, the MCU communicates with one HART chip (i.e., HART modem 3) through UART signals, converts the HART signals into HART signals through the HART chip, and then performs 8-way switching through a second 3-8 decoder and an analog switch, wherein the number of DAC chips is 8 in total, the number of HART chips is 1 in total, and the HART devices communicate with analog signals and HART signals.
In an exemplary embodiment of the present utility model, as shown in fig. 5, the HART chip converts the UART into a HART signal and then connects to the analog switch 6 (e.g., analog switches 61, … …, 68), and the MCU communicates the HART modem 3 with 8 different HART devices 4 by controlling the switching states of the 8 analog switches.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: protection circuits (e.g., protection circuits 71, … …, protection circuit 78); each DAC chip 2 corresponds to one protection circuit 7;
the DAC chip 2 may also be arranged to be connected to the HART device 4 via the protection circuit.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: isolation circuitry (e.g., isolation circuitry 81, … …, isolation circuitry 88, isolation circuitry 89); each DAC chip 2 and the HART modem 3 corresponds to an isolation circuit;
the DAC chip 2 may be further configured to be connected to the MCU1 and the first decoder 51 through the isolation circuit;
the HART modem 3 may also be arranged to be connected to the MCU1 via the isolation circuit.
In an exemplary embodiment of the present utility model, the analog output circuit may further include: isolated power supply modules (e.g., isolated power supply modules 91, … …, isolated power supply module 98) and direct current DC-DC power supply module 10; each DAC chip 2 corresponds to an isolated power supply module;
the DAC chip 2 may be further configured to be connected to the HART device 4 through the isolated power module;
the HART modem may also be arranged to be connected to the MCU1 via the DC-DC power module 10.
In an exemplary embodiment of the utility model, at least the following advantages are included:
1. system reliability is improved: the AO card of the original design uses a large number of discrete devices, the number of the components is large, and the new scheme is adopted, so that the number of electronic components in each channel is greatly reduced, and the reliability of the system is greatly improved.
2. The original electronic component scheme is simplified, the cost is reduced, the productivity is improved, and the configuration is simple.
3. The circuit is carefully and optimally designed, is identical to the common AO configuration, and the signals of the AO card of the embodiment of the utility model have no influence on other card parts, and can be used as the common AO card.
4. High anti-interference performance: the high standard design ensures that the EMC (electromagnetic compatibility) anti-interference performance meets the 3-level requirement.
The embodiment of the utility model provides an analog output clamping piece B, as shown in fig. 6, which can comprise: the analog output circuit A.
In the exemplary embodiment of the present utility model, any embodiment of the foregoing analog output circuit is applicable to the analog output card, and will not be described herein.
In the description of the present utility model, it should be noted that, directions or positional relationships indicated by terms "upper", "lower", "one side", "the other side", "one end", "the other end", "the side", "the opposite", "four corners", "the periphery", "the" mouth "character structure", etc., are directions or positional relationships based on the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the structures referred to have a specific direction, are configured and operated in a specific direction, and thus are not to be construed as limiting the present utility model.
In the description of embodiments of the present utility model, unless explicitly stated and limited otherwise, the terms "connected," "directly connected," "indirectly connected," "fixedly connected," "mounted," "assembled" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; the terms "mounted," "connected," and "fixedly connected" may be directly connected or indirectly connected through intervening media, and may also be in communication between two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.
Although the embodiments of the present utility model are described above, the embodiments are only used for facilitating understanding of the present utility model, and are not intended to limit the present utility model. Any person skilled in the art can make any modification and variation in form and detail without departing from the spirit and scope of the present disclosure, but the scope of the present disclosure is defined by the appended claims.
Claims (10)
1. An analog quantity output circuit, comprising: the micro control unit MCU, the digital-to-analog converter DAC chip and the HART modem;
the instruction output end of the MCU is connected with the instruction input end of the DAC chip;
the analog signal output end of the DAC chip is connected with the analog signal input end of the external HART equipment;
the HART signal input end of the HART modem is connected with the HART signal output end of the HART equipment;
the feedback signal input end of the HART modem is connected with the feedback signal input end of the MCU.
2. The analog output circuit of claim 1, wherein,
the MCU is arranged to send an instruction to the DAC chip;
the DAC chip is arranged to convert the instruction in the form of a digital signal sent by the MCU into an analog signal;
the HART modem is arranged to perform HART communication with the HART equipment to acquire a HART signal returned by the HART equipment; and modulating and demodulating the HART signal to obtain feedback information and sending the feedback information to the MCU.
3. The analog output circuit of claim 1, further comprising: a first decoder; the number of the DAC chips is multiple, and each DAC chip is respectively connected with one HART device;
the serial peripheral interface SPI of the MCU is connected with the signal input end of the first decoder; the signal output end of the first decoder is connected with the instruction input ends of the DAC chips;
the first decoder is configured to implement a chip selection function on a plurality of DAC chips according to a chip selection signal included in the SPI signal;
and the DAC chip is arranged to receive the instruction sent by the MCU after being selected, and couple the converted analog signal to a current loop to be output to the connected HART device.
4. The analog output circuit of claim 1, wherein,
the instruction input end of the HART modem is connected with a Universal Asynchronous Receiver Transmitter (UART) output interface of the MCU; the HART signal output end of the HART modem is connected with the HART signal input end of the HART equipment;
the HART modem is configured to modulate an instruction in the form of a UART serial signal sent by the MCU, obtain a corresponding HART signal, and send the HART signal to the HART device.
5. The analog output circuit of claim 4, further comprising: a second decoder and an analog switch; the HART modem is one; a HART modem corresponds to the plurality of analog switches through a second decoder;
the MCU is connected with the signal input end of the second decoder through an input/output I/O interface;
the signal output end of the second decoder is connected with the controlled end of the analog switch;
the first end of the analog switch is connected with the HART signal input end of the corresponding HART modem, and the second end of the analog switch is connected with the HART signal output end of the corresponding HART modem;
the second decoder is configured to control on-off of the analog switch, so that signals of a plurality of HART devices are scanned sequentially into the HART modem to be demodulated, and the HART modem receives the signals of the plurality of HART devices;
the analog switch is used for controlling the on-off of the HART signal input end and the HART signal output end of the corresponding HART equipment through the on-off control of the analog switch, so that the on-off between the HART modem and the HART equipment is controlled.
6. The analog output circuit according to any one of claims 1 to 4, further comprising: a protection circuit; each DAC chip corresponds to one protection circuit respectively;
the DAC chip is further arranged to be connected with the HART device through the protection circuit.
7. An analog output circuit according to claim 3, further comprising: an isolation circuit; each DAC chip and each HART modem are respectively corresponding to an isolation circuit;
the DAC chip is connected with the MCU and the first decoder through the isolation circuit;
the HART modem is connected with the MCU through the isolation circuit.
8. The analog output circuit according to any one of claims 1 to 4, further comprising: isolating the power module; each DAC chip corresponds to one isolation power supply module respectively;
the DAC chip is connected with the HART equipment through the isolated power module;
the isolated power supply module supplies power to the HART modem and the MCU respectively.
9. An analog output circuit according to any one of claims 1 to 4, wherein,
the DAC chip is a power supply type DAC chip;
the DAC chip is realized by an SD2421 chip;
the HART modem is implemented using an SD2057 chip.
10. An analog output card, comprising: an analog output circuit as claimed in any one of claims 1 to 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202222686272.4U CN219285624U (en) | 2022-10-12 | 2022-10-12 | Analog output circuit and clamping piece |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222686272.4U CN219285624U (en) | 2022-10-12 | 2022-10-12 | Analog output circuit and clamping piece |
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| CN219285624U true CN219285624U (en) | 2023-06-30 |
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| CN202222686272.4U Active CN219285624U (en) | 2022-10-12 | 2022-10-12 | Analog output circuit and clamping piece |
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| CN (1) | CN219285624U (en) |
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