CN205366545U - Modified silicon chip transport package box - Google Patents

Modified silicon chip transport package box Download PDF

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Publication number
CN205366545U
CN205366545U CN201520941085.3U CN201520941085U CN205366545U CN 205366545 U CN205366545 U CN 205366545U CN 201520941085 U CN201520941085 U CN 201520941085U CN 205366545 U CN205366545 U CN 205366545U
Authority
CN
China
Prior art keywords
layer
silicon chip
box body
storage layer
utility
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN201520941085.3U
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Chinese (zh)
Inventor
杨国兴
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WUXI PRITEN TRANSMISSION MACHINERY Co Ltd
Original Assignee
WUXI PRITEN TRANSMISSION MACHINERY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WUXI PRITEN TRANSMISSION MACHINERY Co Ltd filed Critical WUXI PRITEN TRANSMISSION MACHINERY Co Ltd
Priority to CN201520941085.3U priority Critical patent/CN205366545U/en
Application granted granted Critical
Publication of CN205366545U publication Critical patent/CN205366545U/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Abstract

The utility model discloses a modified silicon chip transport package box, including box body (1), storage layer (2), the layer (3) and encapsulant inlet (4) of shocking resistance, the inside distribution of box body (1) has 4~9 to store layer (2), and the surface distribution one deck of storing layer (2) the layer (3) of shocking resistance is with 4~9 side wall mountings encapsulant inlet (4) of storing box body (1) connected on layer (2), the size of storing layer (2) is the same with the upper and lower bottom surface of box body (1). The utility model discloses an it is more that's modified silicon chip transport package box, the setting up of layer of shocking resistance can effectively be avoided storing the collision between layer and the silicon chip, effectively reduces the piece rate of silicon chip among the handling, can save the silicon chip in the effective space is provided. It has great spreading value to make technical field at the silicon chip container.

Description

A kind of silicon chip transportation packaging box of improvement
Technical field
This utility model relates to silicon wafer container manufacturing technology field, is specifically related to the silicon chip transportation packaging box of a kind of improvement.
Background technology
The chip that silicon chip is made is famous " miraculous foresight ", has surprising operational capability.No matter how complicated mathematical problem, physical problem and engineering problem, also the workload no matter calculated has much, as long as staff tells it by computer keyboard problem, and assigning the thinking and instruction solved a problem, computer just can tell you answer within the extremely short time.So, those manually calculate the problem needing cost several years, many decades time, and computer is likely to have only to a few minutes and just can solve.Even some manpower cannot calculate the problem of result, and computer also can quickly tell you answer.
In silicon chip of solar cell production process, silicon chip needs packed and transported, conventional packing box adopts up and down to opening structure, first puts liner in cassette bottom, then sets level silicon chip, finally puts liner again, then lid cap seal case.This manner of packing is simple, but stacks and can produce a large amount of fragment in handling process, increases production cost.
Utility model content
This utility model overcomes above-mentioned shortcoming, and provides the silicon chip transportation packaging box of a kind of improvement.
To achieve these goals, this utility model is to realize by the following technical solutions: the silicon chip transportation packaging box of this improvement includes box body, storage layer, anti-impacting layer and encapsulation mouth, the inside distribution of described box body has 4 ~ 9 storage layer, one layer of anti-impacting layer of the surface distributed of storage layer, the sidewall of the box body linked with storage layer is installed 4 ~ 9 encapsulation mouths;The size of described storage layer is identical with the upper bottom surface of box body.
Described box body is cuboid.
Preferably, the thickness of described storage layer is the 1/19 ~ 1/12 of box body height.
Preferably, described storage layer is identical with the size of anti-impacting layer.
Preferably, described encapsulation mouth is rectangle.
The beneficial effects of the utility model are: scheme is complete, make simple, easy to use;Anti-impacting layer the collision being prevented effectively between storage layer and silicon chip is set, effectively reduce the fragment rate of silicon chip in handling process;The more of silicon chip can be stored in the useful space;For ease of maintenaince and maintenance.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
The implication of accompanying drawing labelling in figure, 1, box body, 2, storage layer, 3, anti-impacting layer, 4, encapsulation mouth.
Detailed description of the invention
For the technological means making this utility model realize, creation characteristic, reach purpose and effect and be easy to understand, below in conjunction with detailed description of the invention, this utility model is expanded on further.
The silicon chip transportation packaging box of this improvement is to achieve these goals, this utility model is to realize by the following technical solutions: the silicon chip transportation packaging box of this improvement includes box body 1, storage layer 2, anti-impacting layer 3 and encapsulation mouth 4, the inside distribution of described box body 1 has 4 ~ 9 storage layer 2, one layer of anti-impacting layer 3 of the surface distributed of storage layer 2, the sidewall of the box body 1 linked with storage layer 2 is installed 4 ~ 9 encapsulation mouths 4;The size of described storage layer 2 is identical with the upper bottom surface of box body 1;Box body 1 is cuboid;The thickness of storage layer 2 is the 1/19 ~ 1/12 of box body 1 height;Storage layer 2 is identical with the size of anti-impacting layer 3;Encapsulation mouth 4 is rectangle.
Of the present utility model ultimate principle and principal character and of the present utility model advantage have more than been shown and described.Skilled person will appreciate that of the industry; this utility model is not restricted to the described embodiments; described in above-described embodiment and description is that principle of the present utility model is described; under the premise without departing from this utility model spirit and scope; this utility model also has various changes and modifications, and these changes and improvements both fall within the scope of claimed this utility model.This utility model claims scope and is defined by appending claims and equivalent thereof.

Claims (5)

1. the silicon chip transportation packaging box improved, it is characterized in that, including box body (1), storage layer (2), anti-impacting layer (3) and encapsulation mouth (4), the inside distribution of described box body (1) has 4 ~ 9 storage layer (2), one layer of anti-impacting layer (3) of the surface distributed of storage layer (2), the sidewall of the box body (1) linked with storage layer (2) is installed 4 ~ 9 encapsulation mouth (4);The size of described storage layer (2) is identical with the upper bottom surface of box body (1).
2. the silicon chip transportation packaging box of improvement according to claim 1, it is characterised in that described box body (1) is cuboid.
3. the silicon chip transportation packaging box of improvement according to claim 1, it is characterised in that the thickness of described storage layer (2) is the 1/19 ~ 1/12 of box body (1) height.
4. the silicon chip transportation packaging box of improvement according to claim 1, it is characterised in that described storage layer (2) is identical with the size of anti-impacting layer (3).
5. the silicon chip transportation packaging box of improvement according to claim 1, it is characterised in that described encapsulation mouth (4) is rectangle.
CN201520941085.3U 2015-11-24 2015-11-24 Modified silicon chip transport package box Expired - Fee Related CN205366545U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201520941085.3U CN205366545U (en) 2015-11-24 2015-11-24 Modified silicon chip transport package box

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201520941085.3U CN205366545U (en) 2015-11-24 2015-11-24 Modified silicon chip transport package box

Publications (1)

Publication Number Publication Date
CN205366545U true CN205366545U (en) 2016-07-06

Family

ID=56261562

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201520941085.3U Expired - Fee Related CN205366545U (en) 2015-11-24 2015-11-24 Modified silicon chip transport package box

Country Status (1)

Country Link
CN (1) CN205366545U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105438645A (en) * 2015-11-24 2016-03-30 无锡普瑞腾传动机械有限公司 Improved silicon wafer transportation packaging box

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105438645A (en) * 2015-11-24 2016-03-30 无锡普瑞腾传动机械有限公司 Improved silicon wafer transportation packaging box

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Legal Events

Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20160706

Termination date: 20161124

CF01 Termination of patent right due to non-payment of annual fee