CN205355050U - Semiconductor electric capacity structure - Google Patents
Semiconductor electric capacity structure Download PDFInfo
- Publication number
- CN205355050U CN205355050U CN201620100332.1U CN201620100332U CN205355050U CN 205355050 U CN205355050 U CN 205355050U CN 201620100332 U CN201620100332 U CN 201620100332U CN 205355050 U CN205355050 U CN 205355050U
- Authority
- CN
- China
- Prior art keywords
- layer
- micron
- utility
- model
- capacitance structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses a semiconductor electric capacity structure, it includes and base plate (1) is equipped with slot (10) on base plate (1), the base plate upper surface covers bottom electrode board (2), and bottom electrode board (2) upper surface covers dielectric layer (3), and the upper surface of dielectric layer (3) covers goes up plate electrode (4), its characterized in that: slot (10) length be the 100 -400 micron, the width is the 5 -20 micron, the degree of depth is the 1 -10 micron, the slot separates the 1 -10 micron each other. The utility model discloses the MIM area is showing and is reducing, and the area of whole circuit is also showing and reduces, reduces the cost, the increasing returns.
Description
Technical field
This utility model relates to a kind of semiconductor structure, more particularly to a kind of mim capacitor structure.
Background technology
III-V, is the compound of N, P, As, the Sb formation of B, Al, Ga, In and the V race of III in the periodic table of elements, mainly includes gallium arsenic (GaAs), indium phosphide (InP) and gallium nitride etc..The expression of III-V is A (III) B (V), such as BN, BP, BAs, BSb, AlN, AlP, AlAs, AlSb, GaN, GaP, GaAs, GaSb, InAs, InN, InP and InSb.In the n-type semiconductor of GaAs material, (((mn～1450), therefore movement velocity is fast, and the application on high-speed digital integrated circuit is more superior than Si quasiconductor for (mn～8500) electron mobility much larger than Si for electron mobility.
Metal-insulator-metal type (MIM, metalinsulatormetal) electric capacity is in semiconductor applications, the fixed capacity element that submicron order semiconductor applications is generally used.But existing MIM capacitor is limit due to technique and material, its shared area is very big, makes whole circuit area big, and cost is high.
Utility model content
The purpose of this utility model is in that to provide a kind of semiconductor capacitance structure, to solve the above-mentioned problems in the prior art.
The technical scheme that this utility model provides is as follows:
A kind of semiconductor capacitance structure, including substrate (1), substrate (1) is provided with groove (10)；Upper surface of base plate covers lower electrode plate (2), lower electrode plate (2) upper surface dielectric layer (3), the upper surface of dielectric layer (3) covers electric pole plate (4), it is characterized in that: described groove (10) length is 100-400 micron, width is 5-20 micron, and the degree of depth is 1-10 micron；Groove is spaced 1-10 micron.
In this utility model, substrate (1) is the substrate that III V compounds of group is made.It is preferably GaAs substrate.
In a preferred embodiment of the present utility model, groove totally 9.
In a preferred embodiment of the present utility model, lower electrode plate (2) is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively.
In a preferred embodiment of the present utility model, the thickness of four layers of metal respectively Ti layer 200-400 micron/Pt layer 300-500 micron/Au layer 8000-1200 micron/Ti layer 20-40 micron.
In a preferred embodiment of the present utility model, dielectric layer (3) is SiN layer or SiON layer.
In a preferred embodiment of the present utility model, dielectric layer (3) thickness is 800-1200A.
In a preferred embodiment of the present utility model, electric pole plate (4) is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively.
In a preferred embodiment of the present utility model, the thickness of four layers of metal respectively Ti layer 200-400 micron/Pt layer 300-500 micron/Au layer 15000-25000 micron/Ti layer 20-40 micron.
Seen from the above description, this utility model provides a kind of semiconductor capacitance structure, and owing to groove (10) length is 100-400 micron, width is 5-20 micron, and the degree of depth is 1-10 micron, and its MIM area significantly reduces.So, the area of integrated circuit also significantly reduces, and reduces cost, increases enterprise profit.
Accompanying drawing explanation
Fig. 1 is underlying structure schematic diagram of the present utility model；
Fig. 2 is the structural representation of substrate+lower electrode plate of the present utility model；
Fig. 3 is the structural representation of this utility model substrate+lower electrode plate+dielectric layer；
Fig. 4 is the structural representation of this utility model substrate+lower electrode plate+dielectric layer+electric pole plate.
In figure, 1-substrate 10-groove 2-lower electrode plate 3-dielectric layer 4-electric pole plate
Detailed description of the invention
Specific embodiment of the utility model, referring to figs. 1 through Fig. 4, a kind of III V race semiconductor capacitance structure, it includes substrate 1, and substrate 1 is provided with groove 10.In the present embodiment, substrate 1 material is GaAs, and in other embodiments, substrate can be other III V compound material plate.In the present embodiment, the length of groove 10 is 200 microns, and width is 10 microns, and the degree of depth is 5 microns.Groove totally 9, is spaced 10 microns.Groove 10 can use RIE (reactive ion etching) or ICP (inductively coupled plasma) method etching to obtain.
Upper surface of base plate (includes groove) and covers lower electrode plate 2, and this lower electrode plate 2 is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively, the thickness of four layers of metal respectively 300 microns/400 microns/10000 microns/30 microns.These four layers of metals can be deposited by the mode of evaporation or sputter and obtain.
Lower electrode plate 2 upper surface dielectric layer 3, dielectric layer 3 is SiN or SiON, and its thickness is 1000A.Dielectric layer 3 can deposit by PECVD mode.
The upper surface of dielectric layer 3 covers electric pole plate 4, and this electric pole plate 4 is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively, the thickness of four layers of metal respectively 300 microns/400 microns/20000 microns/30 microns.These four layers of metals can be deposited by the mode of evaporation or sputter and obtain.
Above are only a specific embodiment of the present utility model, but design concept of the present utility model is not limited thereto, all changes utilizing this design that this utility model carries out unsubstantiality, the behavior invading this utility model protection domain all should be belonged to.
Claims (9)
1. a semiconductor capacitance structure, including substrate (1), substrate (1) is provided with groove (10)；Upper surface of base plate covers lower electrode plate (2), lower electrode plate (2) upper surface dielectric layer (3), the upper surface of dielectric layer (3) covers electric pole plate (4), it is characterized in that: described groove (10) length is 100-400 micron, width is 5-20 micron, and the degree of depth is 1-10 micron；Groove is spaced 1-10 micron.
2. a kind of semiconductor capacitance structure as claimed in claim 1, it is characterised in that: substrate (1) is the substrate that III V compounds of group is made.
3. a kind of semiconductor capacitance structure as claimed in claim 1, it is characterised in that: groove totally 9.
4. a kind of semiconductor capacitance structure as claimed in claim 1, it is characterised in that: lower electrode plate (2) is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively.
5. a kind of semiconductor capacitance structure as claimed in claim 4, it is characterised in that: the thickness of four layers of metal respectively Ti layer 200-400 micron/Pt layer 300-500 micron/Au layer 8000-1200 micron/Ti layer 20-40 micron.
6. a kind of semiconductor capacitance structure as claimed in claim 1, it is characterised in that: dielectric layer (3) is SiN layer or SiON layer.
7. a kind of semiconductor capacitance structure as claimed in claim 6, it is characterised in that: dielectric layer (3) thickness is 800-1200A.
8. a kind of semiconductor capacitance structure as claimed in claim 1, it is characterised in that: electric pole plate (4) is four layers of metal structure, is Ti layer/Pt layer/Au layer/Ti layer from the bottom to top successively.
9. a kind of semiconductor capacitance structure as claimed in claim 8, it is characterised in that: the thickness of four layers of metal respectively Ti layer 200-400 micron/Pt layer 300-500 micron/Au layer 15000-25000 micron/Ti layer 20-40 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620100332.1U CN205355050U (en) | 2016-02-01 | 2016-02-01 | Semiconductor electric capacity structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201620100332.1U CN205355050U (en) | 2016-02-01 | 2016-02-01 | Semiconductor electric capacity structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205355050U true CN205355050U (en) | 2016-06-29 |
Family
ID=56182712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201620100332.1U Active CN205355050U (en) | 2016-02-01 | 2016-02-01 | Semiconductor electric capacity structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205355050U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534505A (en) * | 2019-08-29 | 2019-12-03 | 华中科技大学 | A kind of three-dimensional ferroelectric capacitor device, preparation method and ferroelectric memory |
-
2016
- 2016-02-01 CN CN201620100332.1U patent/CN205355050U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110534505A (en) * | 2019-08-29 | 2019-12-03 | 华中科技大学 | A kind of three-dimensional ferroelectric capacitor device, preparation method and ferroelectric memory |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Lee et al. | Low turn-on voltage AlGaN/GaN-on-Si rectifier with gated ohmic anode | |
| CN108807527B (en) | Group IIIA nitride HEMT with tunnel diode in gate stack | |
| Liu et al. | Enhanced tunneling electroresistance in ferroelectric tunnel junctions due to the reversible metallization of the barrier | |
| CN103098189B (en) | Semiconductor device | |
| CN105280695A (en) | Semiconductor device and manufacturing method thereof | |
| CN104798206B (en) | III-nitride transistor with engineered substrates | |
| TW201001736A (en) | A high-speed avalanche photodiode | |
| CN102881718A (en) | Nitride-based semiconductor device having excellent stability | |
| Hwang et al. | Balanced MSM-2DEG varactors based on AlGaN/GaN heterostructure with cutoff frequency of 1.54 THz | |
| CN205355050U (en) | Semiconductor electric capacity structure | |
| Lee et al. | Schottky barrier heights of metal contacts to n-type gallium nitride with low-temperature-grown cap layer | |
| CN103474478A (en) | Silicon carbide SBD device | |
| Razzak et al. | RF operation in graded AlxGa1− xN (x= 0.65 to 0.82) channel transistors | |
| CN105322006A (en) | Semiconductor heterojunction device | |
| CN105321994B (en) | A kind of gallium nitride diode and preparation method thereof | |
| Guo et al. | Barrier height of Pt–InxGa1− xN (≤ x≤ 0.5) nanowire Schottky diodes | |
| CN108292678A (en) | With two grid group III-nitride field-effect transistor | |
| CN112470289B (en) | Semiconductor device and method for manufacturing the same | |
| CN104321880B (en) | Current apertures diode and preparation method thereof | |
| CN108695157A (en) | A kind of gallium nitride transistor and production method of the composite passivated medium of air gap type | |
| CN110085674B (en) | Vertical power device and manufacturing method thereof | |
| CN105849868B (en) | Nitride semiconductor layer stack and its manufacturing method and nitride compound semiconductor device | |
| JP2013041914A (en) | Semiconductor element and semiconductor element manufacturing method | |
| US11038048B2 (en) | Gallium nitride-on-silicon devices | |
| CN105845743A (en) | Resonant tunneling diode based on InGaAs/AlAs material |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |