CN205334122U - A low level control system of digit for accelerator power source - Google Patents
A low level control system of digit for accelerator power source Download PDFInfo
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- CN205334122U CN205334122U CN201620072613.0U CN201620072613U CN205334122U CN 205334122 U CN205334122 U CN 205334122U CN 201620072613 U CN201620072613 U CN 201620072613U CN 205334122 U CN205334122 U CN 205334122U
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Abstract
The utility model relates to a low level control system of digit for accelerator power source, including data acquisition end, treater, output and simulation frequency conversion subassembly, data acquisition end is connected with treater and simulation frequency conversion subassembly for gather the signal of simulation frequency conversion subassembly output, the treater is including FPGA for it handles to carry out the control of digital PI to the signal of gathering, the output is connected with treater and simulation frequency conversion subassembly for the signal output who handles the treater gives simulation frequency conversion subassembly, simulation frequency conversion subassembly is with the power source headtotail for send the RF power signal process frequency conversion of power source system output for data acquisition end, or export the signal of output for the power source system through the frequency conversion. The utility model relates to a low level control system of digit for accelerator power source has solved the power source system output radiofrequency signal's of existence range among the prior art, phase place, the unstable defect of frequency.
Description
Technical field
The present invention relates to Accelerator control technical field, be specifically related to a kind of digital low for accelerator power source and control system。
Background technology
Digital low controls the control device that system (LLRF, LOWLEVELRFSYSTEM) is a kind of digital low level pulse signal amptitude-phase stability。It adopts the digitized of the intermediate-freuqncy signal in radar, communications field and I/Q complex demodulation and Digital Signal Processing, overcome traditional analog radio frequency control technology performance rigors to device, and the precision and stability of system is affected the shortcomings such as big by the factor such as temperature and components and parts individual variation, thus substantially increasing the stability of system, motility and concordance。It achieving the fast digital width phase feedback compensation of (mS level pulsewidth) closed loop in arteries and veins, the closed loop response time is less than 1 μ S。The power source that digital low controls the system that system (LLRF) can realize different qualities is stable mutually with the width of load cavity, adapts to the power source interface of the systems such as all solid state, electron tube, klystron。
In recent years, continuous lifting along with china's overall national strength, intense beam flow accelerator (is made up of four accelerator centres: 1 spallation neutron target accelerates center, 2ADS clean nuclear power accelerator centre, 3 nuclear waste disposal accelerator centres, 4 treatment of cancer accelerator centres), proton precessional magnetometer, the high energy physical field such as artificial minisun high frequency power source are large quantities of has the world and first intake, and have far-reaching project all initially entering implementation phase with China's scientific and technological progress and the national economic development。Requisite in these accelerator systems is exactly power source system, and existing power source system all exists the defect of the output amplitude of radiofrequency signal, phase place, frequency instability。
Utility model content
This utility model provides a kind of digital low for accelerator power source to control system, solves the power source system existed in prior art and exports the defect of the amplitude of radiofrequency signal, phase place, frequency instability。
The technical scheme that this utility model solves above-mentioned technical problem is as follows: a kind of digital low for accelerator power source controls system, including data acquisition end, processor, outfan and simulated frequency conversion assembly；
Described data acquisition end, is connected with described processor and simulated frequency conversion assembly, for gathering the signal of simulated frequency conversion assembly output；
Described processor, including FPGA, processes for the signal gathered carries out numeral PI control；
Described outfan, is connected with described processor and described simulated frequency conversion assembly, for exporting the signal that processor processes to simulated frequency conversion assembly；
Described simulated frequency conversion assembly, is connected with power source system, is sent to data acquisition end for rf power signal power source system exported through frequency conversion, or is exported to power source system through frequency conversion by the signal that outfan exports。
The beneficial effects of the utility model are: by adopting FPGA to carry out signal processing, it is possible to adjust the amplitude of radiofrequency signal, the phase and frequency that obtain needing, reach the purpose of amplitude and phase stabilization, thus promoting solid-state amplifier excitation transmitter to make power invariability。
On the basis of technique scheme, this utility model can also do following improvement。
Further, described data acquisition end includes cavity pick_up signals collecting port, waveguide forward signal gathers port, waveguide reverse signal gathers at least one in port and neighboring chambers pick_up signals collecting port。
Further, described processor includes FPGA, processes for the signal gathered carries out numeral PI control。
Further, processor also includes DSP, and described DSP is connected with described FPGA, for FPGA is carried out auxiliary operation process。
Above-mentioned further scheme is adopted to provide the benefit that: by adopting DSP that FPGA is carried out auxiliary operation process, the floating-point operation ability of DSP and the advantage of FPGA Fast Fixed-point process can be given full play to, improve the precision that data process, obtain amplitude and the more stable rf power signal of phase place。
Further, described simulated frequency conversion assembly includes simulation up-converter, analog down assembly and power splitter, and the input of described power splitter, from the local oscillation signal of outside local oscillator assembly, is divided into two-way, one tunnel flows to simulation up-converter, and another road flows to analog down assembly；Described simulation up-converter is connected with the output port of described outfan, and described analog down assembly is connected with the input port of described data acquisition end。
Further, described cavity pick_up signals collecting port, waveguide forward signal gather port, waveguide reverse signal collection port and neighboring chambers pick_up signals collecting port and are 16 A/D changers。
Further, described outfan is 16 D/A changers。
Further, described simulation up-converter includes the first branch road, and described first branch road includes the first attenuator, the first amplifier, the first multiplier, the first band filter, the second amplifier, the first switch, second switch and the bonder that are sequentially connected with；Also including the second band filter, described second band filter is also connected with the first multiplier；Described first switch and described second switch all have the clock signal from outside to control its switch, and the quantity of described first branch road is identical with the output port quantity of described outfan。
Further, described analog down assembly includes at least two the second branch road, and described second branch road includes the second attenuator, the 3rd amplifier, the second multiplier, the 3rd band filter and the 4th amplifier that are sequentially connected with；Also include the 4th band filter, described 4th band filter and the second multiplier to connect；The quantity of described second branch road is more than the input port quantity of described data acquisition end。
Further, also including clock circuit, described clock circuit includes the second branch road, also including doubler, the signal of described second branch road output processes through doubler, forms sampled clock signal, the signal of data collection terminal input is sampled, is then sent to described processor。
Accompanying drawing explanation
Fig. 1 is the structural representation that a kind of digital low for accelerator power source of this utility model controls system；
Fig. 2 is the structural representation of data acquisition end in this utility model；
Fig. 3 is the structural representation of simulated assembly in this utility model；
Fig. 4 is the structural representation of local oscillator assembly in this utility model；
Fig. 5 is the structural representation of doubler in this utility model。
In accompanying drawing, the list of parts representated by each label is as follows:
1, data acquisition end, 11, cavity pick_up signals collecting port, 12, waveguide forward signal gather port, 13, waveguide reverse signal gather port, 14, neighboring chambers pick_up signals collecting port, 2, processor, 21, FPGA, 22, DSP, 3, outfan, 4, simulated frequency conversion assembly, 41, simulation up-converter, 42, analog down assembly, 43, power splitter。
Detailed description of the invention
Below in conjunction with accompanying drawing, principle of the present utility model and feature being described, example is served only for explaining this utility model, is not intended to limit scope of the present utility model。
In this utility model, BF1, BF2, BF3, BF4 represent the first band filter, the second band filter, the 3rd band filter, the 4th band filter respectively。DSP is digital signal processor。
As shown in Figure 1, Figure 2 and Figure 3, a kind of digital low for accelerator power source controls system, including data acquisition end 1, processor 2, outfan 3 and simulated frequency conversion assembly 4；
Described data acquisition end 1, is connected with described processor 2 and simulated frequency conversion assembly 4, for gathering the signal of simulated frequency conversion assembly 4 output；
Described processor 2, for processing the signal gathered；Process herein and existing numeral PI control method can be adopted to process；
Described outfan 3, is connected with described processor 2 and described simulated frequency conversion assembly 4, for exporting the signal that processor 2 processes to simulated frequency conversion assembly 4；
Described simulated frequency conversion assembly 4, is connected with power source system, and for the rf power signal that power source system exports is sent to data acquisition end 1 through frequency conversion, or the signal exported by outfan 3 exports to power source system through frequency conversion。Described outfan 3 is 16 D/A changers。
Simulated frequency conversion assembly is connected with power source system, and through frequency-conversion processing, the radiofrequency signal that power source system exports is sent to data acquisition end 1, is exported by outfan 3 again and carry out mixing to simulated frequency conversion assembly 4 and be sent to power source system after processor 2 processes。
Processor 2 includes FPGA21, processes for the signal gathered carries out numeral PI control。Processor 2 also includes DSP22, DSP22 and FPGA21 and connects, for FPGA is carried out auxiliary operation process。
First the radiofrequency signal of accelerator power source system output is processed by analog down assembly, obtain low frequency signal, it is then forwarded to data acquisition end, and completed 4 samplings by clock circuit, carry out analog digital conversion again and be sent to processor, within a processor by FPGA21 process, DSP22 carries out auxiliary operation, radiofrequency signal after being processed, export then through outfan and be mixed to simulation up-converter, signal frequency needed for obtaining accelerator power source system flows to accelerator power source system again, solid-state amplifier excitation transmitter is promoted to make power invariability。
Data acquisition end 1 includes cavity pick_up signals collecting port 11, waveguide forward signal gathers port 12, waveguide reverse signal gathers at least one in port 13 and neighboring chambers pick_up signals collecting port 14。Described cavity pick_up signals collecting port 11, waveguide forward signal gather port 12, waveguide reverse signal gathers port 13 and neighboring chambers pick_up signals collecting port 14 is 16 A/D changers。Cavity pick_up signals collecting port 11 gathers the cavity pick_up signal of power source system；Waveguide forward signal gathers port 12 and gathers the waveguide forward signal of power source system；Waveguide reverse signal gathers port 13 and gathers the waveguide reverse signal of power source system；Neighboring chambers pick_up signals collecting port 14 gathers neighboring chambers pick_up signal, refers to that the cavity corresponding with cavity pick_up signals collecting port 11 is adjacent。
Described simulated frequency conversion assembly 4 includes simulation up-converter 41, analog down assembly 42 and power splitter 43, described power splitter 43 inputs the local oscillation signal from local oscillator assembly, being divided into two-way, a road flows to simulation up-converter 41, and another road flows to analog down assembly 42；The concrete structure of local oscillator assembly is as shown in Figure 4, including a power splitter and a local oscillator LO (locoloscillator, local oscillator) form module, power splitter input signal is from signal source generator, power splitter output can be directly over, it is also possible to form resume module through local oscillator LO and form desired signal。Wherein, local oscillator LO forms module is agitator。
Described simulation up-converter includes the first branch road, and described first branch road includes the first attenuator, the first amplifier, the first multiplier, the first band filter, the second amplifier, the first switch, second switch and the bonder that are sequentially connected with；Also including the second band filter, described second band filter is also connected with the first multiplier；Described first switch and described second switch all have the clock signal from outside to control its switch, and the quantity of described first branch road is identical with the output port quantity of described outfan 3。Second band filter is connected with the outfan of outfan 3, the intermediate-freuqncy signal of the 36MHZ exported by outfan 3 is mixed by the first branch road, the high-frequency signal forming 325MHZ is sent to power source system, and bonder is directional coupler, and output radiofrequency signal is to the input port of data acquisition end 1。
361MHZ signal is the local oscillation signal from local oscillator, is divided into two-way through power splitter, and simulation up-converter is given on a road, and another road is to analog down assembly；
Output gives the 361MHZ signal of simulation up-converter by after the first attenuator decay, amplify again through the first amplifier, then it is multiplied with the 36MHZ low frequency signal through the second band-pass filter, again through the second amplifier processing and amplifying, through first switch and second switch, eventually pass bonder carry out coupling formed 325MHZ high-frequency signal flow to power source system。First switch and second switch control its switch by outside CTL signal, it is possible to become pulsed RF signals to give power source system continuous print rf-signal modulation。CTL signal is two switches acting on each branch road, and it is to increase isolation that each branch road has two switches。
Analog down assembly includes at least two the second branch road, and described second branch road includes the second attenuator, the 3rd amplifier, the second multiplier, the 3rd band filter and the 4th amplifier that are sequentially connected with；Also include the 4th band filter, described 4th band filter and the second multiplier to connect；The quantity of described second branch road is more than the input port quantity of described data acquisition end 1。The quantity of the second branch road is more than the input port quantity of described data acquisition end 1。4th band filter is connected with power source system, receive the high-frequency signal of the 325MHZ of power source system output, with the signal multiplication after power splitter, the second attenuator and the 3rd amplifier process, processing again through the 3rd band filter and the 4th amplifier, the low frequency signal obtaining 36MHZ exports to data acquisition end 1。
Wherein the second branch road at least two, one of them branch road output 36MHZ signal, after doubler processes, forms the clock signal of 144MHZ；
Also including clock circuit 5, clock circuit 5 is connected with data acquisition end 1。Described clock circuit 5 includes the second branch road, also includes doubler, and the signal of described second branch road output processes through doubler, forms sampled clock signal。
Wherein, as shown in Figure 5, second branch road output 36MHZ signal input doubler, it is then passed through the attenuator decay in doubler, amplifier amplifies, the signal of amplification is multiplied by two by multiplier, filter filtering, send into directional coupler coupling after amplifying then through amplifier, be then multiplied by two then through multiplier, decay through attenuator, amplifier amplifies, eventually passing power splitter and be divided into multichannel, each road is amplified after attenuator is decayed again, and eventually forms 144MHZ signal feeding data acquisition port and the signal exported by analog down assembly is sampled；
The frequency of the sampling clock of clock circuit is 4 times of accelerator power source system output radio frequency signal frequency。
The foregoing is only preferred embodiment of the present utility model, not in order to limit this utility model, all within spirit of the present utility model and principle, any amendment of making, equivalent replacement, improvement etc., should be included within protection domain of the present utility model。
Claims (10)
1. the digital low for accelerator power source controls system, it is characterised in that include data acquisition end (1), processor (2), outfan (3) and simulated frequency conversion assembly (4)；
Described data acquisition end (1), is connected with described processor (2) and simulated frequency conversion assembly (4) respectively, is used for gathering the signal that simulated frequency conversion assembly (4) exports；
Described processor (2), processes for the signal gathered carries out numeral PI control；
Described outfan (3), is connected with described processor (2) and described simulated frequency conversion assembly (4) respectively, for exporting the signal that processor (2) processes to simulated frequency conversion assembly (4)；
Described simulated frequency conversion assembly (4), it is connected with power source system, rf power signal for power source system being exported is sent to data acquisition end (1) through frequency conversion, or is exported to power source system through frequency conversion by the signal that outfan (3) exports。
2. a kind of digital low for accelerator power source controls system according to claim 1, it is characterized in that, described data acquisition end (1) includes cavity pick_up signals collecting port (11), waveguide forward signal gathers port (12), waveguide reverse signal gathers at least one in port (13) and neighboring chambers pick_up signals collecting port (14)。
3. a kind of digital low for accelerator power source controls system according to claim 2, it is characterized in that, described cavity pick_up signals collecting port (11), waveguide forward signal gather port (12), waveguide reverse signal gathers port (13) and neighboring chambers pick_up signals collecting port (14) is 16 A/D changers。
4. a kind of digital low for accelerator power source controls system according to claim 1, it is characterised in that described outfan (3) is 16 D/A changers。
5. a kind of digital low for accelerator power source controls system according to claim 1, it is characterised in that described processor (2) includes FPGA (21), processes for the signal gathered carries out numeral PI control。
6. a kind of digital low for accelerator power source controls system according to claim 5, it is characterized in that, described processor (2) also includes DSP (22), described DSP (22) and described FPGA (21) is connected, for described FPGA (21) is carried out auxiliary operation process。
7. a kind of digital low for accelerator power source controls system according to claim 1, it is characterized in that, described simulated frequency conversion assembly (4) includes simulation up-converter (41), analog down assembly (42) and power splitter (43), described power splitter (43) inputs the local oscillation signal from local oscillator assembly, it is divided into two-way, one tunnel flows to simulation up-converter (41), and another road flows to analog down assembly (42)；Described simulation up-converter (41) is connected with the output port of described outfan (3), and described analog down assembly (42) is connected with the input port of described data acquisition end (1)。
8. a kind of digital low for accelerator power source controls system according to claim 7, it is characterized in that, described simulation up-converter (41) includes the first branch road, and described first branch road includes the first attenuator, the first amplifier, the first multiplier, the first band filter, the second amplifier, the first switch, second switch and the bonder that are sequentially connected with；Also including the second band filter, described second band filter is also connected with the first multiplier；Described first switch and described second switch control its on an off by from outside clock signal, and the quantity of described first branch road is identical with the output port quantity of described outfan (3)。
9. a kind of digital low for accelerator power source controls system according to claim 7, it is characterized in that, described analog down assembly includes at least two the second branch road, and described second branch road includes the second attenuator, the 3rd amplifier, the second multiplier, the 3rd band filter and the 4th amplifier that are sequentially connected with；Also include the 4th band filter, described 4th band filter and the second multiplier to connect；The quantity of described second branch road is more than the input port quantity of described data acquisition end (1)。
10. a kind of digital low for accelerator power source controls system according to claim 9, it is characterized in that, also include clock circuit (5), described clock circuit (5) includes the second branch road, also including doubler, the signal of described second branch road output processes through doubler, forms sampled clock signal, the signal that data collection terminal (1) is inputted is sampled, and is then sent to described processor (2)。
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107678338A (en) * | 2017-09-29 | 2018-02-09 | 安德信微波设备有限公司 | A kind of experimental provision of analogue accelerator regulator control system |
| CN108124373A (en) * | 2017-12-18 | 2018-06-05 | 合肥中科离子医学技术装备有限公司 | A kind of devices and methods therefor for being used to control superconducting cyclotron accelerating potential |
| CN108650771A (en) * | 2018-07-12 | 2018-10-12 | 北京航天广通科技有限公司 | Self-excitation stable control method, system and the storage medium of accelerator superconductor cavity |
| CN108684133A (en) * | 2018-06-22 | 2018-10-19 | 中国科学院上海应用物理研究所 | A kind of synchrotron radio frequency system and its frequency and chamber press regulation and control method |
| CN109219228A (en) * | 2018-08-24 | 2019-01-15 | 中国原子能科学研究院 | A kind of voltage balancing algorithm for medical superconducting cyclotron high frequency cavity |
| CN109561567A (en) * | 2018-11-27 | 2019-04-02 | 中国原子能科学研究院 | A kind of high power high stability varying load high frequency acceleration system |
| CN109819577A (en) * | 2019-04-01 | 2019-05-28 | 北京航天广通科技有限公司 | Synchrotron control method and system based on second harmonic |
| CN112057752A (en) * | 2020-09-15 | 2020-12-11 | 散裂中子源科学中心 | All-digital low-level control method and system for boron neutron capture treatment device |
| CN113260133A (en) * | 2021-04-21 | 2021-08-13 | 中国原子能科学研究院 | Low level system for BNCT (bayonet nut connector) cyclotron |
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| CN107678338A (en) * | 2017-09-29 | 2018-02-09 | 安德信微波设备有限公司 | A kind of experimental provision of analogue accelerator regulator control system |
| CN108124373A (en) * | 2017-12-18 | 2018-06-05 | 合肥中科离子医学技术装备有限公司 | A kind of devices and methods therefor for being used to control superconducting cyclotron accelerating potential |
| CN108684133A (en) * | 2018-06-22 | 2018-10-19 | 中国科学院上海应用物理研究所 | A kind of synchrotron radio frequency system and its frequency and chamber press regulation and control method |
| CN108650771A (en) * | 2018-07-12 | 2018-10-12 | 北京航天广通科技有限公司 | Self-excitation stable control method, system and the storage medium of accelerator superconductor cavity |
| CN109219228A (en) * | 2018-08-24 | 2019-01-15 | 中国原子能科学研究院 | A kind of voltage balancing algorithm for medical superconducting cyclotron high frequency cavity |
| CN109561567A (en) * | 2018-11-27 | 2019-04-02 | 中国原子能科学研究院 | A kind of high power high stability varying load high frequency acceleration system |
| CN109819577A (en) * | 2019-04-01 | 2019-05-28 | 北京航天广通科技有限公司 | Synchrotron control method and system based on second harmonic |
| CN109819577B (en) * | 2019-04-01 | 2021-03-19 | 北京航天广通科技有限公司 | Synchrotron control method and system based on second harmonic |
| CN112057752A (en) * | 2020-09-15 | 2020-12-11 | 散裂中子源科学中心 | All-digital low-level control method and system for boron neutron capture treatment device |
| CN113260133A (en) * | 2021-04-21 | 2021-08-13 | 中国原子能科学研究院 | Low level system for BNCT (bayonet nut connector) cyclotron |
| CN117825801A (en) * | 2023-12-28 | 2024-04-05 | 成都菲斯洛克电子技术有限公司 | Integrated broadband signal comprehensive tester and system control method |
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