CN205281609U - Vehicle recording system that traveles based on dual processor - Google Patents
Vehicle recording system that traveles based on dual processor Download PDFInfo
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- CN205281609U CN205281609U CN201520868604.8U CN201520868604U CN205281609U CN 205281609 U CN205281609 U CN 205281609U CN 201520868604 U CN201520868604 U CN 201520868604U CN 205281609 U CN205281609 U CN 205281609U
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Abstract
The utility model discloses a vehicle recording system that traveles based on dual processor, it includes: the singlechip, FPGA treater and video decoding chip, the analog video signal input port of video decoding chip is connected with the output of CCD camera, and the digital video signal output mouth of video decoding chip is connected with the data input mouth of treater, and the data output mouth of FPGA treater is connected with the input port of memory, the singlechip passes through SPI serial communication interface and realizes electric the connection with the FPGA treater: the clock terminal SCL of video decoding chip is connected with the input -output ports of singlechip, and the data terminal SDA of video decoding chip is connected with the input -output ports of singlechip. The utility model has the advantages of can realize good on -vehicle image acquisition storage, it is nimble to have control again concurrently, and the development degree of difficulty is little, and development cost is low.
Description
Technical field
The utility model relates to a kind of vehicle running recording instrument, specifically a kind of vehicle running recording instrument utilizing two treater to realize Design of System Software simplification object.
Background technology
It is a kind of instrument travelling state for registration of vehicle that on-vehicle vehicle travels register system.
In prior art, vehicle running state registering instrument extensively adopts micro-chip to be core processing device, this is owing to single chip application is very general, technician is to its development technique familiarity height, and, micro-chip is at car speed, the measurement of the vehicle parameter such as acceleration, record, and also very ripe with aspect technology such as PC communications; But there is the not good enough defect of processing power on the record of vehicle-mounted image in micro-chip, therefore prior art also exists the treater adopting image-capable stronger, such as DSP or ARM replaces processor of single chip computer, but this makes again Design of System Software complicated, processor of single chip computer can not be made full use of in the high advantage of various vehicle parameter fields of measurement technology maturity, system whole development cost height, development difficulty is big.
In addition it should be noted that image collection must be had very big convenience in the initial configuration of device video decode device by micro-chip, and the vehicle movement register system giving up micro-chip control device is when carrying out the configuration of video decode device, core processing device (being mainly used in the acquisition process to image) just can only be used to realize, this makes again system design difficulty increase, the core controller port wasting of resources.
Practical novel content
For prior art above shortcomings, the purpose of this utility model is: how to provide a kind of processor of single chip computer that makes full use of in the advantage that various vehicle parameter is measured and the fermentation technology maturity such as PC communication is high, make system can realize good onboard image collection to store, have again control concurrently flexibly, the vehicle movement register system that whole development cost and development difficulty are reduced.
In order to realize above-mentioned purpose, the utility model have employed following technical scheme.
A kind of vehicle movement register system based on two treater, it is characterised in that, it comprises: micro-chip, FPGA processor and video decoding chip;
The analog video signal input aperture of described video decoding chip is connected with the output terminal of CCD camera, the digital video signal delivery port of video decoding chip is connected with the data input port of treater, and the data output of FPGA processor is connected with the input aperture of storer;
Described micro-chip realizes being electrically connected by SPI serial communication interface and FPGA processor:
The clock end SCL of video decoding chip is connected with the input and output mouth of micro-chip, and the data end SDA of video decoding chip is connected with the input and output mouth of micro-chip;
The serial ports sending end USBTXD that serial ports sending end TXD and the USB of described micro-chip turns serial port module is connected, the serial ports receiving end USBRXD that receiving end RXD and the USB of microcontroller serial port turns serial port module is connected, and USB is turned serial port module and is connected by USB port with computer.
Further, described micro-chip is AT89C51 chip.
Further, described micro-chip also measures model calling with speed measurement module and acceleration respectively.
Compared to existing technology, the utility model tool has the following advantages:
The utility model utilizes micro-chip at car speed, the measurement of the vehicle parameter such as acceleration, record, and with the aspect technology such as PC communication also very proven technique present situation adopt processor of single chip computer to realize the conventional parameter measurement of vehicle movement, it is flexible that this takes full advantage of micro-chip control, technology maturation, the advantage that Software development difficulty is little; In addition the utility model adopts and realizes onboard image collection record by the FPGA processor of spi bus and single chip communication and through spi bus, view data is transferred to micro-chip, micro-chip is sent to PC to carry out storing record, and this takes full advantage of again the powerful feature of FPGA data processing power. Therefore the utility model has and can realize good onboard image collection and store, and has again control concurrently flexibly, and development difficulty is little, the advantage that cost of development is low.
Accompanying drawing explanation
Fig. 1 is functional block diagram of the present utility model;
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
As shown in Figure 1, a kind of vehicle movement register system based on two treater, it can be divided into conventional driving parameter measurement part and onboard image collection process storage part.
Conventional driving parameter measurement part thinks that micro-chip is process core:
Micro-chip adopts with low cost, and technician applies skilled AT89C51 chip.
Micro-chip measures model calling with speed measurement module and acceleration respectively, and speed measurement module and acceleration measure module for measuring relevant parameter under the control of micro-chip. Concrete device is selected and is controlled interface and adopts device to recommend usual manner.
Measurement gained data turn serial port module by USB and are transferred to computer, circuit connecting relation is: USB is turned serial port module and is connected by USB port with computer, specifically USB turns serial port module and turns serial port download line by a USB and be connected with the USB port of computer, owing to PL2303 module is the routine techniques application that a this area extensively adopts, it is not described in detail its structure and principle of work at this.
Onboard image collection process storage part thinks that FPGA processor is process core:
Specifically comprise FPGA processor and video decoding chip.
The analog video signal input aperture of video decoding chip is connected with the output terminal of CCD camera, the digital video signal delivery port of video decoding chip is connected with the data input port of treater, and the data output of FPGA processor is connected with the input aperture of data-carrier store; Data-carrier store can adopt SDRAM memory and FLASH memory.
Micro-chip realizes being electrically connected by SPI serial communication interface and FPGA processor:
The clock end SCL of video decoding chip is connected with the input and output mouth of micro-chip, and the data end SDA of video decoding chip is connected with the input and output mouth of micro-chip.
Principle of work of the present utility model is described below:
(1) conventional driving parameter measurement part: the routine driving such as the measurement module of speed measurement module and acceleration parameter measurement module turns serial port module by USB after carrying out relevant parameter measurement and transfers data to PC, also namely it is that PC adopts the USB interface of standard to be connected with the utility model, it is achieved computer and data interaction of the present utility model.
(2) onboard image collection process stores part:
Optical signal (needing the travel conditions video gathered) is converted into analog video signal by CCD camera, analog video signal is converted to the digital video signal of PAL by video decode device (SAA7113H chip), by FPGA processor, numerary signal is kept in chip external memory, and carry out the process such as compression of images, video data after processing the most at last are transferred to micro-chip by spi bus, and micro-chip is transferred to PC and stores.
Concrete chip microcontroller and the Principle of Communication of FPGA processor are: micro-chip produces SPI work sequential and realizes the SPI communication interface between micro-chip and FPGA chip, this kind of signalling methods at least has root 4 line when one-way communication (only need 3 lines also can realize), concrete respectively: 1, from device data input line SDI, be also primary device DOL Data Output Line; 2, from device data output line SDO, also it is primary device Data In-Line; 3, clocksignal line SCLK, clocksignal is produced by primary device; 4, from devices enable signal wire CS.
Primary device and carry out synchronous serial data transmission between equipment, under the shift pulse of primary device, data step-by-step is transmitted, and high-order front, low position, rear, is full duplex communication, simply efficiently. (in the utility model, micro-chip is primary device, and CPLD is from equipment)
In addition micro-chip also completes the initial configuration to video decoding chip and works: the video decode device SAA7113H chip extensively adopted is after the power-up, chip is not gather analog video signal immediately to carry out A/D conversion process, output digit signals, after its inside register must be carried out Initialize installation by front-end control device by I2C serial bus by it, could normal operation. The utility model utilizes serial data end SDA, the serial clock terminal SCL of two input/output port Simulation with I 2C of micro-chip, configure according to the sequential of I2C agreement, after configuration, SAA7113H chip is by the digital video signal of the Sequential output PAL of parity field, it is achieved video decode.
What finally illustrate is, above embodiment is only in order to illustrate the technical solution of the utility model and unrestricted, although the utility model being described in detail with reference to better embodiment, it will be understood by those within the art that, the technical solution of the utility model can be modified or equivalent replacement, and not departing from objective and the scope of technical solutions of the utility model, it all should be encompassed in the middle of right of the present utility model.
Claims (3)
1. the vehicle movement register system based on two treater, it is characterised in that, it comprises: micro-chip, FPGA processor and video decoding chip;
The analog video signal input aperture of described video decoding chip is connected with the output terminal of CCD camera, the digital video signal delivery port of video decoding chip is connected with the data input port of treater, and the data output of FPGA processor is connected with the input aperture of storer;
Described micro-chip realizes being electrically connected by SPI serial communication interface and FPGA processor:
The clock end SCL of video decoding chip is connected with the input and output mouth of micro-chip, and the data end SDA of video decoding chip is connected with the input and output mouth of micro-chip;
The serial ports sending end USBTXD that serial ports sending end TXD and the USB of described micro-chip turns serial port module is connected, the serial ports receiving end USBRXD that receiving end RXD and the USB of microcontroller serial port turns serial port module is connected, and USB is turned serial port module and is connected by USB port with computer.
2. a kind of vehicle movement register system based on two treater according to claim 1, it is characterised in that: described micro-chip is AT89C51 chip.
3. a kind of vehicle movement register system based on two treater according to claim 1, it is characterised in that: described micro-chip also measures model calling with speed measurement module and acceleration respectively.
Priority Applications (1)
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CN201520868604.8U CN205281609U (en) | 2015-10-27 | 2015-10-27 | Vehicle recording system that traveles based on dual processor |
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CN201520868604.8U CN205281609U (en) | 2015-10-27 | 2015-10-27 | Vehicle recording system that traveles based on dual processor |
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108594818A (en) * | 2018-04-27 | 2018-09-28 | 深圳市商汤科技有限公司 | Intelligent driving control method, intelligent vehicle-carried equipment and system |
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2015
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108594818A (en) * | 2018-04-27 | 2018-09-28 | 深圳市商汤科技有限公司 | Intelligent driving control method, intelligent vehicle-carried equipment and system |
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C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160601 Termination date: 20161027 |
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CF01 | Termination of patent right due to non-payment of annual fee |