CN205280892U - Survey test panel of area serial number structure - Google Patents
Survey test panel of area serial number structure Download PDFInfo
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- CN205280892U CN205280892U CN201520855775.7U CN201520855775U CN205280892U CN 205280892 U CN205280892 U CN 205280892U CN 201520855775 U CN201520855775 U CN 201520855775U CN 205280892 U CN205280892 U CN 205280892U
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Abstract
The utility model provides a survey test panel of area serial number structure, relate to chip testing technical field, its structure includes at least one test socket, the test socket has the ground connection pin, at least one test socket has high level pin and serial number pin, the serial number pin is connected with high level pin electricity or is connected the serial number for outside this survey of discernment test panel with ground connection pin electricity, the discernment of usable software is as the level condition of the pin of serial number, rethread software converts this level condition into numeral number, just but direct read should survey test panel's serial number, therefore, the utility model discloses a survey test panel and provide the serial number serial number that the pin discerned this survey test panel for the outside, and then save the time that test panel was surveyed in discernment.
Description
Technical field
The utility model relates to chip testing technology field, particularly relates to the test panel of a kind of band numbering structure.
Background technology
Along with the progress of ic manufacturing technology, unicircuit that people can produce circuit complex structure, that integrated level is very high, function is different. But these high integration, multi-functional unicircuit is only that the pin by Limited Number and external circuit connect, and this is just to judging that unicircuit quality brings many difficulties.
Any one piece of unicircuit is all the monolithic module designed for completing certain electrical characteristic function, and the test of unicircuit is exactly use various method, detects the undesirable sample that those cause in the fabrication process due to physical imperfection. Due to the defect that making processes is brought and material itself more or less has of reality, thus perfectly engineering all can produce bad individuality in any case, thus tests one of engineering of also just becoming indispensable in IC manufacturing.
Test macro comprises test panel, test machine and test procedure etc. Existing test panel does not all add numbering, can't see the numbering of test panel in the process of unicircuit test, if which block test panel what need understanding is, just must suspend test, take off test panel, like this will delay test, lose time.
Practical novel content
The test panel that the purpose of this utility model is to avoid weak point of the prior art and provides a kind of band numbering structure, the test panel of this band numbering structure can provide numbering pin to identify the numbering of this test panel to outside, and then saves the time identifying test panel.
The purpose of this utility model is achieved through the following technical solutions:
The test panel of a kind of band numbering structure is provided, comprise at least one test socket, test socket has ground pin, it is characterized in that: at least one test socket has high level pin and numbering pin, and numbering pin is electrically connected with high level pin or is electrically connected the numbering identifying this test panel for outside with ground pin.
Described test socket is provided with two, and each test socket has a numbering pin.
Described test socket is provided with two, and each test socket has two numbering pins.
Described test socket is provided with three, and each test socket has a numbering pin.
Described test socket is provided with three, and each test socket has two numbering pins.
Described test socket is provided with three, and each test socket has three numbering pins.
Described test socket is provided with four, and each test socket has a numbering pin.
Described test socket is provided with four, and each test socket has two numbering pins.
The beneficial effects of the utility model: the test panel of band numbering structure of the present utility model, comprise at least one test socket, test socket has ground pin, at least one test socket has high level pin and numbering pin, numbering pin is electrically connected with high level pin or is electrically connected the numbering identifying this test panel for outside with ground pin, therefore, the test panel of band numbering structure of the present utility model, numbering pin can be provided to identify the numbering of this test panel to outside, and then save the time identifying test panel.
Accompanying drawing explanation
Accompanying drawing is utilized to be described further practicality is novel, but the embodiment in accompanying drawing does not form any restriction of the present utility model, for the those of ordinary skill of this area, under the prerequisite not paying creative work, it is also possible to obtain other accompanying drawing according to the following drawings.
Fig. 1 is the local structure schematic diagram that a kind of band of the present utility model is numbered the test panel of 46.
Fig. 2 is the structural representation of the test socket SL0T7 of embodiment 1.
Fig. 3 is the structural representation of the test socket SL0T4 of embodiment 1.
Fig. 4 is the structural representation of the test socket SL0T3 of embodiment 1.
Fig. 5 is the structural representation of the test socket SL0T1 of embodiment 1.
Figure includes
Test panel 1.
Embodiment
With the following Examples the utility model is further described.
Embodiment 1.
The test panel of a kind of band numbering structure of the present embodiment, as shown in Figures 2 to 5, comprises four tests socket SL0T7, SL0T4, SL0T3 and SL0T1, and each test socket has two numbering pins.
The numbering pin of four tests socket SL0T7, SL0T4, SL0T3 and SL0T is the 14th pin and the 16th pin, and 15 pins are high level pin.
This test panel 1 be numbered No. 46, to reach and be numbered 46, the pin of test panel 1 need to be carried out as follows weld:
As shown in Figure 1, 48th pin of the 16th pin of test socket SL0T7 with test socket SL0T7 is welded together (i.e. ground connection), 16th pin of test socket SL0T4 welds together (i.e. ground connection) with the 48th pin of test socket SL0T4, 16th pin of test socket SL0T3 welds together (namely connecing high level) with the 15th pin of test socket SL0T3, 16th pin of test socket SL0T1 welds together (i.e. ground connection) with the 48th pin of test socket SL0T1, 14th pin of test socket SL0T7 welds together (namely connecing high level) with test socket SL0T7 the 15th pin, 14th pin of test socket SL0T4 welds together (namely connecing high level) with the 15th pin of test socket SL0T4, 14th pin of test socket SL0T3 welds together (namely connecing high level) with test socket SL0T3 the 15th pin, 14th pin of test socket SL0T1 welds together (i.e. ground connection) with the 46th pin of test socket SL0T1.
The test panel 1 of above band numbering structure, numbering pin can be provided to identify the numbering of this test panel to outside, software identification can be utilized as the level situation of the pin of numbering, by software, this level situation is converted to numeral number again, just can directly read the numbering of this test panel 1, therefore, the test panel of the band numbering structure of the present embodiment can provide numbering pin to identify the numbering of this test panel to outside, can save, at the auxiliary lower of software, the time identifying test panel 1.
Use four test sockets can realize more numbering, it is only necessary to amendment numbering pin and high level pin or lower level pin weld relation.
The present embodiment is as follows to the recognition methods of numbering pin:
Identify the level situation of the pin of two numberings of four test sockets respectively, the high level recognized and lower level are converted to different binary digit respectively, the binary digit sequential of conversion is formed octet string, then this octet string is converted to tens digit.
On four test sockets of embodiment 1, the 15th pin of four sockets SL0T7, SL0T4, SL0T3, SL0T1 is all put 1 by program.
14th pin and the 16th pin of four sockets SL0T7, SL0T4, SL0T3, SL0T1 are numbering pins.
The level of the numbering pin of four sockets SL0T7, SL0T4, SL0T3, SL0T1 is as follows:
The 16th pin ground connection of test socket SL0T7, for lower level, the 16th pin ground connection of test socket SL0T4, for lower level, 16th pin of test socket SL0T3 connects with test socket SL0T3 the 15th pin, for high level, the 16th pin ground connection of test socket SL0T1, for lower level, 14th pin of test socket SL0T7 is connect test socket SL0T7 the 15th pin, for high level, 14th pin of test socket SL0T4 connects test socket SL0T4 the 15th pin, for high level, 14th pin of test socket SL0T3 connects with test socket SL0T3 the 15th pin, for high level, the 14th pin ground connection of test socket SL0T1, for lower level.
Identify the level situation of the pin of two numberings of four test sockets respectively.
The high level recognized and lower level are converted to different binary digit respectively: high level is converted to binary digit 1, it are binary digit 0 by low transition. Then can obtain testing the corresponding Binary Zero of the 16th pin of socket SL0T7, the corresponding Binary Zero of 16th pin of test socket SL0T4, the corresponding binary one of 16th pin of test socket SL0T3, the corresponding Binary Zero of 16th pin of test socket SL0T1, the corresponding binary one of 14th pin of test socket SL0T7, the corresponding binary one of 14th pin of test socket SL0T4, the corresponding binary one of the 14th pin of test socket SL0T3, the corresponding Binary Zero of the 14th pin of test socket SL0T1.
Will conversion binary digit sequential formed octet string: according to test socket SL0T7 the 16th pin, test socket SL0T4 the 16th pin, test socket SL0T3 the 16th pin, test socket SL0T1 the 16th pin, test socket SL0T7 the 14th pin, test socket SL0T4 the 14th pin, above binary digit is carried out sequential by the order of the 14th pin of test socket SL0T3, the 14th pin of test socket SL0T1, and obtaining octet string is 00101110.
This octet string is converted to tens digit: octet string is that 00101110 to be converted to tens digit be then 46, therefore, the test panel 1 of embodiment 1 be numbered No. 46.
Recognition methods for the numbering of other numeral is analogized successively, sets forth no longer one by one at this.
Above test panel has eight numbering pins, it may be achieved 8 power the numberings of 2, i.e. 256 numberings.
Embodiment 2.
The test panel of a kind of band numbering structure of the present embodiment, is characterized in: test socket is provided with two, and each test socket has two numbering pins, namely one has four numbering pins, it may be achieved 4 power the numberings of 2, i.e. 16 numberings.
Embodiment 3.
The test panel of a kind of band numbering structure of the present embodiment, is characterized in: test socket is provided with three, and each test socket has three numbering pins, namely one has nine numbering pins, it may be achieved 9 power the numberings of 2, i.e. 512 numberings.
Finally should be noted that; above embodiment is only in order to illustrate the technical solution of the utility model; but not the restriction to the utility model protection domain; although having done to explain to the utility model with reference to better embodiment; it will be understood by those within the art that; the technical solution of the utility model can be modified or equivalent replacement, and not depart from essence and the scope of technical solutions of the utility model.
Claims (8)
1. the test panel of a band numbering structure, comprise at least one test socket, test socket has ground pin, it is characterized in that: at least one test socket has high level pin and numbering pin, and numbering pin is electrically connected with high level pin or is electrically connected the numbering identifying this test panel for outside with ground pin.
2. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with two, and each test socket has a numbering pin.
3. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with two, and each test socket has two numbering pins.
4. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with three, and each test socket has a numbering pin.
5. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with three, and each test socket has two numbering pins.
6. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with three, and each test socket has three numbering pins.
7. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with four, and each test socket has a numbering pin.
8. the test panel of a kind of band numbering structure as claimed in claim 1, it is characterised in that: described test socket is provided with four, and each test socket has two numbering pins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520855775.7U CN205280892U (en) | 2015-10-30 | 2015-10-30 | Survey test panel of area serial number structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520855775.7U CN205280892U (en) | 2015-10-30 | 2015-10-30 | Survey test panel of area serial number structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205280892U true CN205280892U (en) | 2016-06-01 |
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| CN201520855775.7U Active CN205280892U (en) | 2015-10-30 | 2015-10-30 | Survey test panel of area serial number structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105242195A (en) * | 2015-10-30 | 2016-01-13 | 广东利扬芯片测试股份有限公司 | Test board with number structure, and identification method of number |
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2015
- 2015-10-30 CN CN201520855775.7U patent/CN205280892U/en active Active
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105242195A (en) * | 2015-10-30 | 2016-01-13 | 广东利扬芯片测试股份有限公司 | Test board with number structure, and identification method of number |
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