CN205232016U - Error magnification device and drive circuit who contains said error magnification device - Google Patents
Error magnification device and drive circuit who contains said error magnification device Download PDFInfo
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- CN205232016U CN205232016U CN201521029118.3U CN201521029118U CN205232016U CN 205232016 U CN205232016 U CN 205232016U CN 201521029118 U CN201521029118 U CN 201521029118U CN 205232016 U CN205232016 U CN 205232016U
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Abstract
The utility model provides an error magnification device with contain the drive circuit of error magnification device the utility model provides an in the error amplifier device, pulse generating circuit produces first pulse and second pulse according to the output voltage of error amplifier unit, and the counter is counted first pulse and second pulse, and the count signal sample hold circuit interval set time is right the sampling of the counting value of counter, spaced set time and input exchange 50Hz60Hz voltage synchronism, the filtering exchange 50Hz60Hz's ripple voltage, make loop control voltage and input alternating voltage's ripple that it doesn't matter to the measure of going up has reduced the size of building -out capacitor, from this can with the integration of loop building -out capacitor to the IC inside, simplified peripheral design, eliminate the influence of moist electric leakage to the loop.
Description
Technical field
The utility model relates to a kind of error amplification device and comprises the drive circuit of described error amplification device.
Background technology
Traditional Alternating Current Power Supply, band power factor adjustment (PFC) function buck configuration constant current driver circuit for LED as shown in Figure 1, mainly comprise: AC input rectification circuit 101, interchange input source 102, input capacitance Cin, inductance L 1, power switch M1, sampling resistor Rs, sustained diode 1, output capacitance Cbulk, output current sample circuit 111, error amplifier 112, building-out capacitor Ccomp, pwm signal generation circuit 113.
Wherein, AC input rectification circuit 101 receive exchange input source 102 AC-input voltage and to its rectification; One end of input capacitance Cin connects input voltage incoming end Vin, its other end ground connection; The source of power switch M1 connects input voltage incoming end Vin, and its drain terminal connects one end of sampling resistor Rs, and its grid termination receives the drive singal of pwm signal generation circuit 113; One end of inductance L 1 connects the other end of sampling resistor Rs, and the other end of inductance L 1 connects one end of output capacitance Cbulk; The negative electrode of sustained diode 1 connects one end of sampling resistor Rs, and its anode connects the other end of output capacitance Cbulk; Output capacitance Cbulk is used in parallel with load, such as in parallel with LED load; Sampling resistor Rs sampled output current, with driving power switch M1.
Described output current sample circuit 111 calculates output current sampled voltage by carrying out sampling to the voltage Vcs on sampling resistor Rs; The output current sampled voltage that output current sample circuit 111 calculates by described error amplifier 112 and reference voltage V ref do error and amplify, export bucking voltage Vcomp, the output of error amplifier 112 connects building-out capacitor 103, after loop stability, bucking voltage Vcomp is substantially fixing, and output current is determined by reference voltage V ref; Described pwm signal generation circuit 113 connects the output of error amplifier 112 and the grid end of power switch M1, realizes driving the turn-on and turn-off of power switch M1.
When power switch M1 conducting, input current flows through sampling resistor Rs, inductance L 1, output capacitance Cbulk, output end vo ut, and the electric current flowing through inductance L 1 increases, inductance L 1 stored energy.Have no progeny when power switch M1 closes, flow through the electric current of inductance L 1 through sustained diode 1 afterflow, the electric current flowing through inductance L 1 reduces gradually, and inductance L 1 releases energy output capacitance Cbulk and output end vo ut.When the voltage Vcs on sampling resistor Rs is less than reference voltage V ref, through error amplifier 112 and pwm signal generation circuit 113 conducting power switch M1.Power switch M1 repeats switch motion above, circuit continuous firing, is in critical current mode conduction mode all the time.
But, due to exchange input source 102 input signal normally frequency be the AC signal of 50Hz/60Hz, the output current sampled voltage that output current sample circuit 111 calculates also is the signal with 50Hz/60Hz embossing ripple, in order to the interference signal of filtering 50Hz/60Hz, building-out capacitor Ccomp can not obtain too little, generally 1 more than μ F is all greater than in side circuit, the building-out capacitor of this size cannot be integrated into IC interior, chip exterior can only be accomplished, this is just easily subject to the impact of moist electric leakage and then affects output current, also the simplification of periphery circuit is unfavorable for.
Utility model content
The drive circuit that the purpose of this utility model is to provide a kind of error amplification device and comprises described error amplification device, to solve existing technical problem.
According to one side of the present utility model, a kind of error amplification device is provided, comprises:
Error amplifier block;
Pulse generating circuit, connects described error amplifier block, and produces the first pulse and the second pulse according to the output voltage of described error amplifier block;
Counter, connects described pulse generating circuit, and counts the first pulse and the second pulse;
Count signal sampling hold circuit, connect described counter and a fixed time intervals sampled signal synchronous with input AC rectified waveform, described fixed time intervals sampled signal controls described count signal sampling hold circuit fixed time intervals and samples to the count value of described counter.
Optionally, in described error amplification device, described pulse generating circuit comprises the first pulse generating circuit producing described first pulse and the second pulse generating circuit producing described second pulse.
Optionally, in described error amplification device, described error amplifier block comprises: the first timing circuit produces circuit, the first electric capacity, the first switch, the first comparator, the second timing circuit generation circuit, the second electric capacity, second switch and the second comparator; The positive input terminal of described first comparator connects described first timing circuit and produces circuit, one end of the first electric capacity and the source of the first switch, the negative input end of described first comparator connects one first reference voltage, and the output of described first comparator connects the input of described first pulse generating circuit; The output of described first pulse generating circuit is connected an input of described counter with the grid end of the first switch, the other end of described first electric capacity and the drain terminal ground connection of described first switch; The positive input terminal of described second comparator connects described second timing circuit and produces circuit, one end of the second electric capacity and the source of second switch, the negative input end of described second comparator connects one second reference voltage, and the output of described second comparator connects the input of described second pulse generating circuit; The output of described second pulse generating circuit is connected another input of described counter with the grid end of second switch, the other end of described second electric capacity and the drain terminal ground connection of described second switch.
Optionally, in described error amplification device, described first timing circuit produces circuit under a reference voltage controls to described first capacitor charging, first comparator upset described in when charging voltage reaches described first reference voltage, described first pulse generating circuit produces first pulse, first switch conduction described in described first Pulse Width Control, to remove the voltage on described first electric capacity, then starts to charge and pulses generation next time; Described second timing circuit produces circuit under an output current sampled signal controls to described second capacitor charging, second comparator upset described in when charging voltage reaches described second reference voltage, described second pulse generating circuit produces second pulse, second switch conducting described in described second Pulse Width Control, to remove the voltage on described second electric capacity, then starts to charge and pulses generation next time.
Optionally, in described error amplification device, exchange half cycle at one, set up following relation: I1 × C22 × VB=I2avg × C21 × VA; Wherein, I1 is the current value that described first timing circuit produces circuit, C22 is the capacitance of described second electric capacity, VB is the magnitude of voltage of described second reference voltage, I2avg is the current average that described second timing circuit produces circuit, C21 is the capacitance of described first electric capacity, and VA is the magnitude of voltage of described first reference voltage.
Optionally, in described error amplification device, described error amplifier block comprises: error amplifier, electric capacity, the first switch, the first comparator, second switch and the second comparator; The positive input terminal of described error amplifier connects a reference voltage, the negative input end of described error amplifier connects an output current sampled signal, and the output of described error amplifier connects the positive input terminal of described first comparator and the positive input terminal of the second comparator; The negative input end of described first comparator connects one the 3rd reference voltage, and the output of described first comparator connects the input of described first pulse generating circuit; The output of described first pulse generating circuit connects an input of described forward-backward counter, and the pulse signal that described first pulse generating circuit exports controls the break-make of described first switch; The negative input end of described second comparator connects one the 4th reference voltage, and the output of described second comparator connects the input of described second pulse generating circuit; The output of described second pulse generating circuit connects another input of described forward-backward counter, and the pulse signal that described second pulse generating circuit exports controls the break-make of described second switch; Described electric capacity one end connects the output of described error amplifier, other end ground connection.
Optionally, in described error amplification device, when the positive input terminal input voltage of described error amplifier is greater than negative input end input voltage, described capacitor charging, when charging voltage is more than producing first pulse during the 3rd reference voltage, first pulse makes the first switch conduction, and the current potential of electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage); When the positive input terminal input voltage of described error amplifier is less than negative input end input voltage, described capacitor discharge, when discharge voltage is lower than producing second pulse during the 4th reference voltage, second pulse makes second switch conducting, and the current potential of electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage).
Optionally, in described error amplification device, described error amplifier is transconductance type error amplifier.
Optionally, in described error amplification device, described pulse generating circuit comprises the 3rd pulse generating circuit producing described first pulse and the second pulse.
Optionally, in described error amplification device, described error amplifier block comprises: error amplifier, electric capacity, switch, the first comparator, the second comparator, four selector switches and inverter; The positive input terminal of described error amplifier connects a reference voltage, and the negative input end of described error amplifier connects an output current sampled signal; The positive input terminal of described first comparator connects the 5th reference voltage, the negative input end of described first comparator connects the output of described error amplifier, the output of described first comparator connects input and the inverter of described 3rd pulse generating circuit, and described 5th reference voltage is 1/2* (the 3rd reference voltage+the four reference voltage); The positive input terminal of described second comparator by described four selector switches connect described electric capacity with the 3rd reference voltage or the 4th reference voltage, the output of described second comparator connects the input of described 3rd pulse generating circuit; The output of described 3rd pulse generating circuit connects the input of described forward-backward counter, and the pulse signal that described 3rd pulse generating circuit exports controls the break-make of described switch.
Optionally, in described error amplification device, when the positive input terminal input voltage of described error amplifier is greater than negative input end input voltage, described capacitor charging, when charging voltage is more than 1/2* (the 3rd reference voltage+the four reference voltage), described first comparator exports the first switch selection signal, the positive input terminal of described comparator connects described electric capacity, negative input end connects the 3rd reference voltage, first switch selection signal controls the 3rd pulse generating circuit simultaneously, when charging voltage is more than producing first pulse during the 3rd reference voltage, described first pulse makes switch conduction, the current potential of described electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage), when the positive input terminal input voltage of described error amplifier is less than negative input end input voltage, described capacitor discharge, when discharge voltage is lower than 1/2* (the 3rd reference voltage+the four reference voltage), described first comparator exports second switch and selects signal, the positive input terminal of described second comparator connects the 4th reference voltage, negative input end connects described electric capacity, second pulse is produced when discharge voltage is less than the 4th reference voltage, described second pulse makes switch conduction, the current potential of described electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage).
Optionally, in described error amplification device, described counter is a forward-backward counter.Described counter uses plus coujnt to described first pulse, uses subtraction count to described second pulse, or described counter uses plus coujnt to described second pulse, uses subtraction count to described first pulse.Exchange half cycle at one, plus coujnt is greater than subtraction count, and the count value of described counter increases, and the store digital signal of described count signal sampling hold circuit increases; Exchange half cycle at one, plus coujnt is less than subtraction count, and the count value of described counter reduces, and the store digital signal of described count signal sampling hold circuit reduces; Exchange half cycle at one, plus coujnt equals subtraction count, and the count value of described counter is constant, and the store digital signal of described count signal sampling hold circuit is constant.
Optionally, in described error amplification device, described counter uses trigger structure, and described count signal sampling hold circuit uses trigger structure.
Optionally, in described error amplification device, described fixed time intervals sampled signal is obtained by the voltage and current waveform relevant to described input AC waveform.
Optionally, in described error amplification device, the digital signal that described count signal sampling hold circuit exports directly controls a pwm signal, or, remove control one pwm signal again after the digital signal that described count signal sampling hold circuit exports converts analog signal to.
Optionally, in described error amplification device, described error amplification device is used in Closed-loop Constant-current control circuit, closed loop constant-voltage control circuit or closed loop constant-power control circuit.
Optionally, in described error amplification device, described error amplification device is used in buck configuration, boost configuration, Flyback configuration or buck structure.
According to another aspect of the present utility model, also a kind of drive circuit, comprises error amplification device as above.
Optionally, in described drive circuit, also comprise: output current sample circuit and pwm signal generation circuit; The input of described error amplifier connects described output current sample circuit, and the output of described error amplifier connects described pwm signal generation circuit.
In the error amplification device that the utility model provides, pulse generating circuit produces the first pulse and the second pulse according to the output voltage of error amplifier block, counter counts the first pulse and the second pulse, count signal sampling hold circuit fixed time intervals is sampled to the count value of described counter, the set time at interval and input AC 50Hz/60Hz voltage synchronous, 50Hz/60Hz signal is not exchanged in the output signal of count signal sampling hold circuit, namely filtering exchanges the ripple voltage of 50Hz/60Hz, it doesn't matter to make the ripple of loop control voltage and input ac voltage, above measure reduces the size of building-out capacitor, loop compensation electric capacity can be integrated into IC inside thus, simplify periphery design, eliminate the impact of moist electric leakage on loop.
Accompanying drawing explanation
Fig. 1 is the buck configuration constant current driver circuit for LED structural representation of prior art;
Fig. 2 is the error amplification device electrical block diagram that the utility model first embodiment provides;
Fig. 3 is the voltage relationship schematic diagram in Fig. 2 on burst pulse and building-out capacitor;
Fig. 4 is fixed time intervals sampled signal schematic diagram synchronous with input AC rectified waveform;
Fig. 5 is the error amplification device electrical block diagram that the utility model second embodiment provides;
Fig. 6 is the error amplification device electrical block diagram that the utility model the 3rd embodiment provides;
The driving circuit structure schematic diagram that Fig. 7 the utility model the 4th embodiment provides.
Embodiment
Core concept of the present utility model is, provides a kind of error amplification device, comprising: error amplifier block, pulse generating circuit, counter and count signal sampling hold circuit; Described pulse generating circuit connects described error amplifier block, and produces the first pulse and the second pulse according to the output voltage of described error amplifier block; Described counter connects described pulse generating circuit, and counts the first pulse and the second pulse; Described count signal sampling hold circuit connects described counter and a fixed time intervals sampled signal synchronous with input AC rectified waveform, and described fixed time intervals sampled signal controls described count signal sampling hold circuit fixed time intervals and samples to the count value of described counter.The utility model uses counter bucking voltage digitlization, and at given spaced time-samples, interlude and input AC 50Hz/60Hz voltage synchronous, 50Hz/60Hz signal is not exchanged in the output signal of count signal sampling hold circuit, filtering exchanges the ripple voltage of 50Hz/60Hz, loop control voltage is produced by digital-to-analogue conversion, control pwm signal produces, it doesn't matter, to reduce the size of building-out capacitor can to accomplish the ripple of loop control voltage and input ac voltage.
Below in conjunction with the drawings and specific embodiments, the error amplification device that the utility model proposes is described in further detail.According to the following describes and claims, advantage of the present utility model and feature will be clearer.It should be noted that, accompanying drawing all adopts the form that simplifies very much and all uses non-ratio accurately, only in order to object that is convenient, aid illustration the utility model embodiment lucidly.
First embodiment
Fig. 2 is the error amplification device electrical block diagram of the utility model first embodiment.Described error amplification device comprises: the first timing circuit produces circuit I 1, first electric capacity C21, the first switch M2, the first comparator 201, first pulse generating circuit 202; Second timing circuit produces circuit I 2, second electric capacity C22, second switch M3, the second comparator 203, second pulse generating circuit 203; Forward-backward counter 205, count signal sampling hold circuit 206, the digital signal that count signal sampling hold circuit 206 exports removes control loop.
Specifically as shown in Figure 2, reference voltage V ref controls described first timing circuit and produces circuit I 1, one end that described first timing circuit produces circuit I 1, first electric capacity C21 is connected the positive input terminal of the first comparator 201 with the source of the first switch M2, the negative input end of described first comparator 201 connects one first reference voltage VA, the output of described first comparator 201 connects the input of the first pulse generating circuit 202, and the output of described first pulse generating circuit 202 is connected an input of forward-backward counter 205 with the grid end of the first switch M2; The other end of described first electric capacity C21 and the drain terminal ground connection of the first switch M2.Described output current sample circuit 208 calculates output current sampled signal to control the second timing circuit generation circuit I 2 by carrying out sampling to the voltage Vcs on sampling resistor Rs, described second timing circuit produces circuit I 2, one end of second electric capacity C22 is connected the positive input terminal of the second comparator 203 with the source of second switch M3, the negative input end of described second comparator 203 connects one second reference voltage VB, the output of described second comparator 203 connects the input of the second pulse generating circuit 204, the described output of the second pulse generating circuit 204 is connected an input of forward-backward counter 205 with the grid end of second switch M3, the described other end of the second electric capacity C22 and the drain terminal ground connection of second switch M3.The input of the output connection count signal sampling hold circuit 206 of described forward-backward counter 205, the loop control signal of the output output of described count signal sampling hold circuit 206 is in order to control loop.
Shown in composition graphs 2 and Fig. 3, reference voltage V ref controls the first timing circuit and produces circuit I 1, first timing circuit produces circuit I 1 and charges to the first electric capacity C21, when charging voltage reaches the first reference voltage VA, first comparator 201 overturns, a first pulse CK1 is produced through the first pulse generating circuit 202, first pulse CK1 controls the first switch M2 conducting, remove the voltage on the first electric capacity C21, then start again to charge and pulses generation next time, the number of such first pulse CK1 pulse just illustrates I1 is charged to the first reference voltage VA number of times to the first electric capacity C21.Equally, output current sampled signal controls the second timing circuit and produces circuit I 2, second timing circuit produces circuit I 2 and charges to the second electric capacity C22, when charging voltage reaches the second reference voltage VB, second comparator 203 overturns, a second pulse CK2 is produced through the second pulse generating circuit 203, second pulse CK2 controls second switch M3 conducting, remove the voltage on the second electric capacity C22, then start again to charge and pulses generation next time, the number of such second pulse CK2 just illustrates the second timing circuit and produces circuit I 2 is charged to the second reference voltage VB number of times to the second electric capacity C22.
Wherein, forward-backward counter 205 produces addition and subtraction counting; The first situation, uses plus coujnt to the first pulse CK1, uses subtraction count to the second pulse CK2; The second situation, uses plus coujnt to the second pulse CK2, uses subtraction count to the first pulse CK1.The output connection count signal sampling hold circuit 206 of forward-backward counter 205, keeps in the count value sampling of fixed time intervals to counter 205.As a nonrestrictive example, forward-backward counter 205 uses trigger structure, and count signal sampling hold circuit 206 uses trigger structure.
With reference to figure 4, fixed time intervals sampled signal is synchronous with input AC rectified waveform, and exchange half cycle at one, plus coujnt is greater than subtraction count, and the count value of forward-backward counter 205 increases, and the store digital signal of count signal sampling hold circuit 206 increases; Exchange half cycle at one, plus coujnt is less than subtraction count, and the count value of forward-backward counter 205 reduces, and the store digital signal of count signal sampling hold circuit 206 reduces; Exchange half cycle at one, plus coujnt equals subtraction count, and the count value of forward-backward counter 205 is constant, and the store digital signal of count signal sampling hold circuit 206 is constant.
After loop stability, exchange half cycle at one, have following relation to set up:
I1×C22×VB＝I2avg×C21×VA
Wherein, I1 is the current value that described first timing circuit produces circuit, C22 is the capacitance of described second electric capacity, VB is the magnitude of voltage of described second reference voltage, I2avg is the current average that described second timing circuit produces circuit, C21 is the capacitance of described first electric capacity, and VA is the magnitude of voltage of described first reference voltage.I2avg represents the size of output current, as long as this equation represent set the first timing circuit produce circuit I 1, second electric capacity C22, the second reference voltage VB, the first electric capacity C21, the first reference voltage VA numerical value just can determine also namely to determine the size of output current by the mean value of the second timing circuit generation circuit I 2.The effect of the signal that count signal sampling hold circuit 206 exports is equal to the loop compensation voltage Vcomp in structure shown in Fig. 1.
As a nonrestrictive example, fixed time intervals sampled signal can obtain from the voltage relevant to input AC waveform, current waveform.The digital signal that count signal sampling hold circuit 206 exports can directly go to control pwm signal, and regulate the duty ratio of pwm signal, the negative feedback through loop reaches the object of stabilizing output current.The digital signal that described count signal sampling hold circuit 206 exports also first can convert analog signal to, then goes to control pwm signal, and regulate the duty ratio of pwm signal, the negative feedback through loop reaches the object of stabilizing output current.
Second embodiment
Owing to using two the first electric capacity C21, the second electric capacity C22 in Fig. 2, relate to and arrive the problem of Circuit Matching, therefore, in the present embodiment, use an electric capacity C31 to substitute the first electric capacity C21 and the second electric capacity C22.Further, use an error amplifier 401 to substitute the first timing circuit and produce circuit I 1 and the second timing circuit generation circuit I 2, described error amplifier 401 is generally transconductance type error amplifier.
Fig. 5 is the utility model second embodiment medial error amplifying device electrical block diagram.As shown in Figure 5, described error amplifier block comprises: error amplifier 401, electric capacity C31, the first switch 403, first comparator 201, second switch 404 and the second comparator 203.
Wherein, two inputs of error amplifier 401 connect reference voltage V ref and output current sampled signal respectively, the output of error amplifier 401 connects the positive input terminal of the first comparator 201 and the positive input terminal of the second comparator 203, the negative input end of the first comparator 201 connects one the 3rd reference voltage VC, the output of the first comparator 201 connects the input of the first pulse generating circuit 202, the output of the first pulse generating circuit 202 connects an input of forward-backward counter 205, the pulse signal that first pulse generating circuit 202 exports controls the break-make of the first switch 403, the negative input end of the second comparator 203 connects one the 4th reference voltage VD, the output of the second comparator 203 connects the input of the second pulse generating circuit 204, the output of the second pulse generating circuit 204 connects another input of forward-backward counter 205, and the pulse signal that the second pulse generating circuit 204 exports controls the break-make of second switch 404, electric capacity C31 one end connects the output of described error amplifier 401, other end ground connection.
When the positive input terminal input voltage of error amplifier 401 is greater than negative input end input voltage, electric capacity C31 charges, when charging voltage is more than the 3rd reference voltage VC, produce a first pulse CK1, first pulse CK1 makes the first switch 403 conducting, and the current potential of electric capacity C31 is haled to 1/2* (VC+VD); When the positive input terminal input voltage of error amplifier 401 is less than negative input end input voltage, electric capacity C31 discharges, when discharge voltage is lower than the 4th reference voltage VD, produce a second pulse CK2, second pulse CK2 makes second switch 404 conducting, and the current potential of electric capacity C31 is haled to 1/2* (VC+VD); First switch 403 and second switch 404 can share.
The voltage difference charged due to the electric capacity C31 that the first pulse CK1 pulse is corresponding is 1/2* (VC-VD), the voltage difference of the electric capacity C31 electric discharge that the second pulse CK2 pulse is corresponding is also 1/2* (VC-VD), namely the difference changed is identical, if then exchange half cycle at one, first pulse CK1 is identical with the second pulse CK2 count value, it is identical for just illustrating electric capacity C31 charging and discharging, it can thus be appreciated that the positive input terminal of error amplifier is identical with negative input end voltage, also namely achieve the effect of error amplifier.
3rd embodiment
Fig. 6 is the utility model the 3rd embodiment error amplification device electrical block diagram.As shown in Figure 6, the present embodiment is on the basis of Fig. 5, merge the first pulse generating circuit and the second pulse generating circuit, namely adopts the 3rd pulse generating circuit 503.The input of the second comparator 502 connects electric capacity C31, VC, VD by selector switch, and the first comparator 501 obtains the first switch selection signal S1 and second switch selects signal S2; First switch selection signal S1 also controls the 3rd pulse generating circuit the 503, three pulse generating circuit 503 and produces the first pulse CK1 and the second pulse CK2.
Specifically, described error amplifier block comprises: error amplifier 401, electric capacity C31, switch 403, first comparator 501, second comparator 502, selector switch 601,602,603,604, inverter 504.Wherein, two inputs of error amplifier 401 connect reference voltage V ref and output current sampled signal respectively; The positive input terminal of the first comparator 501 connects the 5th reference voltage 1/2* (VC+VD), and negative input end connects the output of error amplifier 401, and output connects input and the inverter 504 of the 3rd pulse generating circuit 503; The positive input terminal of the second comparator 502 connects electric capacity C31 or VD by selector switch 601,602, and negative input end connects electric capacity C31 or VC by selector switch 603,604, and output connects the input of the 3rd pulse generating circuit 503; The output of the 3rd pulse generating circuit 503 connects the input of forward-backward counter 205, the break-make of the pulse signal control switch 403 that the 3rd pulse generating circuit 503 exports.
When the positive input terminal input voltage of error amplifier 401 is greater than negative input end input voltage, electric capacity C31 charges, when charging voltage is more than 1/2* (VC+VD), first comparator 501 exports the first switch selection signal S1, first switch selection signal S1 controls selector switch 601, 604 close, the positive input terminal of comparator 502 is made to connect electric capacity C31, negative input end connects the 3rd reference voltage VC, simultaneously, first switch selection signal S1 controls the 3rd pulse generating circuit 503, when charging voltage is more than the 3rd reference voltage VC, produce a first pulse CK1, first pulse CK1 makes switch 403 conducting, the current potential of electric capacity C31 is haled to 1/2* (VC+VD).
When the positive input terminal input voltage of error amplifier 401 is less than negative input end input voltage, electric capacity C31 discharges, when discharge voltage is lower than 1/2* (VC+VD), first comparator 501 exports second switch and selects signal S2, second switch selects signal S2 to control selector switch 602, 603 close, the positive input terminal of the second comparator 502 is made to connect the 4th reference voltage VD, negative input end connects electric capacity C31, when discharge voltage is less than VD, produce a second pulse CK2, second pulse CK2 makes switch 403 conducting, the current potential of electric capacity C31 is haled to 1/2* (VC+VD).
The voltage difference charged due to the electric capacity C31 that the first pulse CK1 pulse is corresponding is 1/2* (VC-VD), the voltage difference of the electric capacity C31 electric discharge that the second pulse CK2 pulse is corresponding is also 1/2* (VC-VD), namely the difference changed is identical, if then exchange half cycle at one, first pulse CK1 is identical with the second pulse CK2 count value, it is identical for just illustrating electric capacity C31 charging and discharging, it can thus be appreciated that the positive input terminal of error amplifier is identical with negative input end voltage, also namely achieve the effect of error amplifier.Wherein, the effect of described first pulse CK1, the second pulse CK2 is identical with Fig. 2, Fig. 4, repeats no more herein.
4th embodiment
The present embodiment provides a kind of drive circuit, comprises error amplification device 701, and described error amplification device 701 can adopt the structure described by above-mentioned any embodiment to realize.
Specifically as shown in Figure 7, described drive circuit mainly comprises: AC input rectification circuit 101, interchange input source 102, input capacitance Cin, inductance L 1, power switch M1, sampling resistor Rs, sustained diode 1, output capacitance Cbulk, output current sample circuit 208, error amplification device 701, pwm signal generation circuit 113.
Wherein, AC input rectification circuit 101 receive exchange input source 102 AC-input voltage and to its rectification; One end of input capacitance Cin connects input voltage incoming end Vin, its other end ground connection; The source of power switch M1 connects input voltage incoming end Vin, and its drain terminal connects one end of sampling resistor Rs, and its grid termination receives the drive singal of pwm signal generation circuit 113; One end of inductance L 1 connects the other end of sampling resistor Rs, and the other end of inductance L 1 connects one end of output capacitance Cbulk; The negative electrode of sustained diode 1 connects one end of sampling resistor Rs, and its anode connects the other end of output capacitance Cbulk; Output capacitance Cbulk is used in parallel with load, such as in parallel with LED load; Sampling resistor Rs sampled output current, with driving power switch M1; The input of described error amplification device 701 connects described output current sample circuit 208, and its output connects described pwm signal generation circuit 113.
It should be noted that, the utility model not only can be used in Closed-loop Constant-current control circuit and reduce building-out capacitor, can also be used in closed loop constant-voltage control circuit and reduce building-out capacitor, building-out capacitor is reduced with being used in closed loop constant-power control circuit, all can realize object building-out capacitor being built into chip internal, to simplify periphery circuit, to improve the reliability of circuit.
The utility model error amplification device circuit structure can be used in various power supply topologies, include, without being limited to buck configuration, boost configuration, Flyback configuration, buck structure etc., when using, directly error amplifier structure of the present utility model is replaced the error amplifier structure of original circuit, so place illustrates no longer one by one.
In this specification, each embodiment adopts the mode of going forward one by one to describe, and what each embodiment stressed is the difference with other embodiments, between each embodiment identical similar portion mutually see.For system disclosed in embodiment, owing to corresponding to the method disclosed in Example, so description is fairly simple, relevant part illustrates see method part.
Foregoing description is only the description to the utility model preferred embodiment; any restriction not to the utility model scope; any change that the those of ordinary skill in the utility model field does according to above-mentioned disclosure, modification, all belong to the protection range of claims.
Claims (25)
1. an error amplification device, is characterized in that, comprising:
Error amplifier block;
Pulse generating circuit, connects described error amplifier block, and produces the first pulse and the second pulse according to the output voltage of described error amplifier block;
Counter, connects described pulse generating circuit, and counts the first pulse and the second pulse;
Count signal sampling hold circuit, connect described counter and a fixed time intervals sampled signal synchronous with input AC rectified waveform, described fixed time intervals sampled signal controls described count signal sampling hold circuit fixed time intervals and samples to the count value of described counter.
2. error amplification device as claimed in claim 1, is characterized in that, described pulse generating circuit comprises the first pulse generating circuit producing described first pulse and the second pulse generating circuit producing described second pulse.
3. error amplification device as claimed in claim 2, it is characterized in that, described error amplifier block comprises: the first timing circuit produces circuit, the first electric capacity, the first switch, the first comparator, the second timing circuit generation circuit, the second electric capacity, second switch and the second comparator;
The positive input terminal of described first comparator connects described first timing circuit and produces circuit, one end of the first electric capacity and the source of the first switch, the negative input end of described first comparator connects one first reference voltage, and the output of described first comparator connects the input of described first pulse generating circuit;
The output of described first pulse generating circuit is connected an input of described counter with the grid end of the first switch, the other end of described first electric capacity and the drain terminal ground connection of described first switch;
The positive input terminal of described second comparator connects described second timing circuit and produces circuit, one end of the second electric capacity and the source of second switch, the negative input end of described second comparator connects one second reference voltage, and the output of described second comparator connects the input of described second pulse generating circuit;
The output of described second pulse generating circuit is connected another input of described counter with the grid end of second switch, the other end of described second electric capacity and the drain terminal ground connection of described second switch.
4. error amplification device as claimed in claim 3, it is characterized in that, described first timing circuit produces circuit under a reference voltage controls to described first capacitor charging, first comparator upset described in when charging voltage reaches described first reference voltage, described first pulse generating circuit produces first pulse, first switch conduction described in described first Pulse Width Control, to remove the voltage on described first electric capacity, then starts to charge and pulses generation next time; Described second timing circuit produces circuit under an output current sampled signal controls to described second capacitor charging, second comparator upset described in when charging voltage reaches described second reference voltage, described second pulse generating circuit produces second pulse, second switch conducting described in described second Pulse Width Control, to remove the voltage on described second electric capacity, then starts to charge and pulses generation next time.
5. error amplification device as claimed in claim 4, is characterized in that, exchanges half cycle, set up following relation at one:
I1×C22×VB＝I2avg×C21×VA
Wherein, I1 is the current value that described first timing circuit produces circuit, C22 is the capacitance of described second electric capacity, VB is the magnitude of voltage of described second reference voltage, I2avg is the current average that described second timing circuit produces circuit, C21 is the capacitance of described first electric capacity, and VA is the magnitude of voltage of described first reference voltage.
6. error amplification device as claimed in claim 4, it is characterized in that, the numerical value according to described first timing circuit generation circuit, the second electric capacity, the second reference voltage, the first electric capacity, the first reference voltage determines that described second timing circuit produces the mean value of circuit.
7. error amplification device as claimed in claim 2, it is characterized in that, described error amplifier block comprises: error amplifier, electric capacity, the first switch, the first comparator, second switch and the second comparator;
The positive input terminal of described error amplifier connects a reference voltage, the negative input end of described error amplifier connects an output current sampled signal, and the output of described error amplifier connects the positive input terminal of described first comparator and the positive input terminal of the second comparator;
The negative input end of described first comparator connects one the 3rd reference voltage, and the output of described first comparator connects the input of described first pulse generating circuit;
The output of described first pulse generating circuit connects an input of described counter, and the pulse signal that described first pulse generating circuit exports controls the break-make of described first switch;
The negative input end of described second comparator connects one the 4th reference voltage, and the output of described second comparator connects the input of described second pulse generating circuit;
The output of described second pulse generating circuit connects another input of described counter, and the pulse signal that described second pulse generating circuit exports controls the break-make of described second switch;
Described electric capacity one end connects the output of described error amplifier, other end ground connection.
8. error amplification device as claimed in claim 7, it is characterized in that, when the positive input terminal input voltage of described error amplifier is greater than negative input end input voltage, described capacitor charging, when charging voltage is more than producing first pulse during the 3rd reference voltage, first pulse makes the first switch conduction, and the current potential of electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage); When the positive input terminal input voltage of described error amplifier is less than negative input end input voltage, described capacitor discharge, when discharge voltage is lower than producing second pulse during the 4th reference voltage, second pulse makes second switch conducting, and the current potential of electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage).
9. error amplification device as claimed in claim 8, it is characterized in that, the voltage difference of the capacitor charging that described first pulse is corresponding is 1/2* (the 3rd reference voltage-four reference voltage), the voltage difference of the capacitor discharge that described second pulse is corresponding is also 1/2* (the 3rd reference voltage-four reference voltage), if exchange half cycle at one, first pulse is identical with the second counted number of pulses, represents that capacitor charging and electric discharge are identical.
10. error amplification device as claimed in claim 7, it is characterized in that, described error amplifier is transconductance type error amplifier.
11. error amplification devices as claimed in claim 1, is characterized in that, described pulse generating circuit comprises the 3rd pulse generating circuit producing described first pulse and the second pulse.
12. error amplification devices as claimed in claim 11, it is characterized in that, described error amplifier block comprises: error amplifier, electric capacity, switch, the first comparator, the second comparator, four selector switches and inverter;
The positive input terminal of described error amplifier connects a reference voltage, and the negative input end of described error amplifier connects an output current sampled signal;
The positive input terminal of described first comparator connects the 5th reference voltage, the negative input end of described first comparator connects the output of described error amplifier, the output of described first comparator connects input and the inverter of described 3rd pulse generating circuit, and described 5th reference voltage is 1/2* (the 3rd reference voltage+the four reference voltage);
The positive input terminal of described second comparator by described four selector switches connect described electric capacity with the 3rd reference voltage or the 4th reference voltage, the output of described second comparator connects the input of described 3rd pulse generating circuit;
The output of described 3rd pulse generating circuit connects the input of described counter, and the pulse signal that described 3rd pulse generating circuit exports controls the break-make of described switch.
13. error amplification devices as claimed in claim 12, it is characterized in that, when the positive input terminal input voltage of described error amplifier is greater than negative input end input voltage, described capacitor charging, when charging voltage is more than 1/2* (the 3rd reference voltage+the four reference voltage), described first comparator exports the first switch selection signal, the positive input terminal of described comparator connects described electric capacity, negative input end connects the 3rd reference voltage, first switch selection signal controls the 3rd pulse generating circuit simultaneously, when charging voltage is more than producing first pulse during the 3rd reference voltage, described first pulse makes switch conduction, the current potential of described electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage), when the positive input terminal input voltage of described error amplifier is less than negative input end input voltage, described capacitor discharge, when discharge voltage is lower than 1/2* (the 3rd reference voltage+the four reference voltage), described first comparator exports second switch and selects signal, the positive input terminal of described second comparator connects the 4th reference voltage, negative input end connects described electric capacity, second pulse is produced when discharge voltage is less than the 4th reference voltage, described second pulse makes switch conduction, the current potential of described electric capacity is haled to 1/2* (the 3rd reference voltage+the four reference voltage).
14. error amplification devices as claimed in claim 13, it is characterized in that, the voltage difference of the capacitor charging that described first pulse is corresponding is 1/2* (the 3rd reference voltage-four reference voltage), the voltage difference of the capacitor discharge that described second pulse is corresponding is also 1/2* (the 3rd reference voltage-four reference voltage), if exchange half cycle at one, first pulse is identical with the second counted number of pulses, represents that capacitor charging and electric discharge are identical.
15. error amplification devices according to any one of claim 1 to 14, it is characterized in that, described counter is a forward-backward counter.
16. error amplification devices as claimed in claim 15, is characterized in that, described counter uses plus coujnt to described first pulse, use subtraction count to described second pulse; Or described counter uses plus coujnt to described second pulse, subtraction count is used to described first pulse.
17. error amplification devices as claimed in claim 16, is characterized in that, exchange half cycle at one, plus coujnt is greater than subtraction count, and the count value of described counter increases, and the store digital signal of described count signal sampling hold circuit increases; Exchange half cycle at one, plus coujnt is less than subtraction count, and the count value of described counter reduces, and the store digital signal of described count signal sampling hold circuit reduces; Exchange half cycle at one, plus coujnt equals subtraction count, and the count value of described counter is constant, and the store digital signal of described count signal sampling hold circuit is constant.
18. error amplification devices according to any one of claim 1 to 14, is characterized in that, described counter uses trigger structure.
19. error amplification devices according to any one of claim 1 to 14, is characterized in that, described count signal sampling hold circuit uses trigger structure.
20. error amplification devices according to any one of claim 1 to 14, it is characterized in that, described fixed time intervals sampled signal is obtained by the voltage and current waveform relevant to described input AC rectified waveform.
21. error amplification devices according to any one of claim 1 to 14, it is characterized in that, the digital signal that described count signal sampling hold circuit exports directly controls a pwm signal, or, after the digital signal that described count signal sampling hold circuit exports converts analog signal to, remove control one pwm signal again.
22. error amplification devices according to any one of claim 1 to 14, it is characterized in that, described error amplification device is used in Closed-loop Constant-current control circuit, closed loop constant-voltage control circuit or closed loop constant-power control circuit.
23. error amplification devices according to any one of claim 1 to 14, it is characterized in that, described error amplification device is used in buck configuration, boost configuration, Flyback configuration or buck structure.
24. 1 kinds of drive circuits, is characterized in that, comprise as the error amplification device in claim 1 to 21 as described in any one.
25. drive circuits as claimed in claim 24, is characterized in that, also comprise: output current sample circuit and pwm signal generation circuit; The input of described error amplifier connects described output current sample circuit, and the output of described error amplifier connects described pwm signal generation circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521029118.3U CN205232016U (en) | 2015-12-10 | 2015-12-10 | Error magnification device and drive circuit who contains said error magnification device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201521029118.3U CN205232016U (en) | 2015-12-10 | 2015-12-10 | Error magnification device and drive circuit who contains said error magnification device |
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| Publication Number | Publication Date |
|---|---|
| CN205232016U true CN205232016U (en) | 2016-05-11 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201521029118.3U Withdrawn - After Issue CN205232016U (en) | 2015-12-10 | 2015-12-10 | Error magnification device and drive circuit who contains said error magnification device |
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| CN (1) | CN205232016U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356730A (en) * | 2015-12-10 | 2016-02-24 | 杭州士兰微电子股份有限公司 | Error amplification device and driving circuit comprising same |
| CN108429440A (en) * | 2018-05-18 | 2018-08-21 | 清华四川能源互联网研究院 | A kind of ripplet hop cycle control method and control circuit |
-
2015
- 2015-12-10 CN CN201521029118.3U patent/CN205232016U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105356730A (en) * | 2015-12-10 | 2016-02-24 | 杭州士兰微电子股份有限公司 | Error amplification device and driving circuit comprising same |
| WO2017097260A1 (en) * | 2015-12-10 | 2017-06-15 | 杭州士兰微电子股份有限公司 | Error amplification apparatus and drive circuit comprising error amplification apparatus |
| CN105356730B (en) * | 2015-12-10 | 2018-03-06 | 杭州士兰微电子股份有限公司 | Error amplification device and the drive circuit for including the error amplification device |
| CN108429440A (en) * | 2018-05-18 | 2018-08-21 | 清华四川能源互联网研究院 | A kind of ripplet hop cycle control method and control circuit |
| CN108429440B (en) * | 2018-05-18 | 2024-03-29 | 清华四川能源互联网研究院 | Small ripple skip period control method and control circuit |
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Granted publication date: 20160511 Effective date of abandoning: 20180306 |