CN205212692U

CN205212692U - Low dropout regulator's current foldback circuit and low voltage difference linear constant voltage power supply

Info

Publication number: CN205212692U
Application number: CN201520822340.2U
Authority: CN
Inventors: 闫琳静
Original assignee: Beijing Jingwei Hirain Tech Co Ltd
Current assignee: Beijing Jingwei Hirain Tech Co Ltd
Priority date: 2015-10-22
Filing date: 2015-10-22
Publication date: 2016-05-04
Anticipated expiration: 2025-10-22

Abstract

The application discloses low dropout regulator's current foldback circuit and low voltage difference linear constant voltage power supply, including electric current production circuit and current -limiting circuit, the electric current produces the circuit and is used for producing the electric current of following that risees along with mains voltage's rising to current output will be followed and the NMOS pipe in the current -limiting circuit will be given, the current -limiting circuit is used for exceeding at low dropout regulator's output current and is restricted to output current in the restriction electric current that reduces along with mains voltage's rising according to following the electric current when predetermineeing the threshold value. Like this, the electric current of accompanying that the electric current produced the circuit production increases along with mains voltage's increase, makes the restriction electric current of current -limiting circuit output reduce along with mains voltage's increase, when mains voltage risees, makes low dropout regulator's output current reduce promptly to low dropout regulator's the advancing the speed of output is advanced the speed in order to restrain the temperature when restraining mains voltage and rising, avoids because mains voltage increase and the LDO superheated damage that causes rapidly.

Description

The current foldback circuit of low pressure difference linear voltage regulator and low pressure difference linearity stabilized voltage power supply

Technical field

The application relates to circuit engineering field, particularly relates to a kind of current foldback circuit and low pressure difference linearity stabilized voltage power supply of low pressure difference linear voltage regulator.

Background technology

Power supply is very important part in electronic system, due to LDO (LowDropoutVoltageRegulator, low pressure difference linear voltage regulator) have that volume is little, noise is little, output ripple is low, without electromagnetic interference and the advantage such as simplicity of design, peripheral cell be few, stable supply voltage can be provided, so be widely used in various electronic system for output loading.

The carrying load ability of LDO embodies as a significant capability of application of power chip, when output loading may cause LDO to damage more than when the carrying load ability of LDO and overload.At present, in order to prevent the LDO caused due to overload from damaging, normally when the carrying load ability of output loading more than LDO, being limited by the maximum output current of overcurrent protection module to LDO, avoiding LDO to cause overcurrent damage due to excessive output current.

But when LDO is operated under overload state, although the maximum output current of LDO can be restricted to a value determined, the power of LDO can increase along with the increase of supply voltage, thus the temperature of LDO also can raise along with the increase of supply voltage.Therefore, when supply voltage increases rapidly, easily make the temperature of LDO raise rapidly and cause the mistake cause thermal damage of LDO.

Utility model content

In view of this, the embodiment of the present application provides a kind of current foldback circuit and low pressure difference linearity stabilized voltage power supply of low pressure difference linear voltage regulator, crosses cause thermal damage to avoid the LDO caused because supply voltage increases rapidly.

To achieve these goals, the technical scheme that provides of the embodiment of the present application is as follows:

A kind of current foldback circuit of low pressure difference linear voltage regulator, described low pressure difference linear voltage regulator comprises operational amplifier, power tube, first feedback resistance and the second feedback resistance, the first input end of described operational amplifier is connected with reference voltage, the output of described operational amplifier is connected with the grid of described power tube, the drain electrode of described power tube is connected with the first end of described first feedback resistance, second end of described first feedback resistance is connected with the first end of described second feedback resistance and the second input of described operational amplifier respectively, second end ground connection of described second feedback resistance, the first end of described first feedback resistance and the second end of described second feedback resistance are the output of described low pressure difference linear voltage regulator, described current foldback circuit comprises:

Current generating circuit and current-limiting circuit;

Described current-limiting circuit comprises: the first PMOS, the second PMOS, the first NMOS tube, the second NMOS tube and the first resistance;

The source electrode of described first PMOS is connected with supply voltage, and the grid of described first PMOS is connected with the grid of described power tube, and the drain electrode of described first PMOS is connected with the drain electrode of described first NMOS tube;

The source ground of described first NMOS tube, the drain electrode of described first NMOS tube is connected with the grid of the grid of described first NMOS tube and described second NMOS tube;

The source ground of described second NMOS tube, the drain electrode of described second NMOS tube is connected with the grid of the first end of described first resistance and described second PMOS;

The source electrode of described second PMOS is connected with described supply voltage, and the drain electrode of described second PMOS is connected with the grid of described power tube;

Second end of described first resistance is connected with described supply voltage;

The follow current that described current generating circuit raises for generation of the rising with described supply voltage, and described follow current is exported to described first NMOS tube in described current-limiting circuit;

Described current-limiting circuit is used for described output current being restricted to according to described follow current the Limited Current reduced with the rising of described supply voltage when the output current of described low pressure difference linear voltage regulator exceedes predetermined threshold value.

Preferably, described current generating circuit comprises:

3rd PMOS MP1, the 4th PMOS HVMP1, the 5th PMOS HVMP2, the 6th PMOS HVMP3, the 7th PMOS HVMP4, the 8th PMOS HVMP5, the 9th PMOS HVMP6, the 3rd NMOS tube MNBN1, the 4th NMOS tube HVMN1, the 5th NMOS tube MN1, the second resistance R1, the 3rd resistance R2, the 4th resistance R3, bias current sources IBIAS;

The source electrode of described 3rd PMOS MP1 is connected with described supply voltage, and the grid of described 3rd PMOS MP1 is connected with the drain electrode of the drain electrode of described 3rd PMOS MP1 and described 3rd NMOS tube MNBN1;

The grid of described 3rd NMOS tube MNBN1 and drain electrode short circuit, the source electrode of described 3rd NMOS tube MNBN1 is connected with the first end of described second resistance R1, and second end of described second resistance R1 is connected with the source electrode of described 4th PMOS HVMP1;

The drain electrode of described 4th PMOS HVMP1 is connected with one end of described bias current sources IBIAS, the other end ground connection of described bias current sources IBIAS, the grid of described 4th PMOS HVMP1 is connected with the grid of the drain electrode of described 4th PMOS HVMP1 and described 5th PMOS HVMP2;

The grounded drain of described 5th PMOS HVMP2, the source electrode of described 5th PMOS HVMP2 is connected with the source electrode of described 4th NMOS tube HVMN1;

The grid of described 4th NMOS tube HVMN1 is connected with the source electrode of described 4th PMOS HVMP1, and the drain electrode of described 4th NMOS tube HVMN1 is connected with the drain electrode of described 6th PMOS HVMP3;

The source electrode of described 6th PMOS HVMP3 is connected with described supply voltage, and the drain electrode of described 6th PMOS HVMP3 is connected with the grid of the grid of described 6th PMOS HVMP3 and described 7th PMOS HVMP4;

The source electrode of described 7th PMOS HVMP4 is connected with described supply voltage, and the drain electrode of described 7th PMOS HVMP4 is connected with the drain electrode of described 9th PMOS HVMP6 and the drain electrode of described first NMOS tube HVMN2;

The source electrode of described 8th PMOS HVMP5 is connected with described supply voltage, the drain electrode of described 8th PMOS HVMP5 and the grid of described 8th PMOS HVMP5 and the drain electrode of described 5th NMOS tube MN1 and the grid of described 9th PMOS HVMP6 are connected, and the source electrode of described 9th PMOS HVMP6 is connected with described supply voltage;

The source ground of described 5th NMOS tube MN1, the grid of described 5th NMOS tube MN1 is connected with the first end of the first end of described 3rd resistance and described 4th resistance, second end of described 3rd resistance is connected with the source electrode of described 5th PMOS HVMP2, the second end ground connection of described 4th resistance.

Preferably, described current generating circuit comprises:

3rd PMOS MP1, the 4th PMOS HVMP1, the 5th PMOS HVMP2, the 6th PMOS HVMP3, the 7th PMOS HVMP4, the 3rd NMOS tube MNBN1, the 4th NMOS tube HVMN1, the second resistance R1, the 3rd resistance R2, the 4th resistance R3, bias current sources IBIAS;

The source electrode of described 7th PMOS HVMP4 is connected with described supply voltage, and the drain electrode of described 7th PMOS HVMP4 is connected with the drain electrode of described first NMOS tube HVMN2;

The first end of described 3rd resistance is connected with the first end of described 4th resistance, and the second end of described 3rd resistance is connected with the source electrode of described 5th PMOS HVMP2, the second end ground connection of described 4th resistance.

Preferably, described current generating circuit comprises:

3rd PMOS MP1, the 4th PMOS HVMP1, the 5th PMOS HVMP2, the 8th PMOS HVMP5, the 9th PMOS HVMP6, the 3rd NMOS tube MNBN1, the 4th NMOS tube HVMN1, the 5th NMOS tube MN1, the second resistance R1, the 3rd resistance R2, the 4th resistance R3, bias current sources IBIAS;

The grid of described 4th NMOS tube HVMN1 is connected with the source electrode of described 4th PMOS HVMP1, and the drain electrode of described 4th NMOS tube HVMN1 is connected with described supply voltage;

The source electrode of described 8th PMOS HVMP5 is connected with described supply voltage, and the drain electrode of described 8th PMOS HVMP5 and the grid of described 8th PMOS HVMP5 and the drain electrode of described 5th NMOS tube MN1 and the grid of described 9th PMOS HVMP6 are connected;

The source electrode of described 9th PMOS HVMP6 is connected with described supply voltage, and the drain electrode of described 9th PMOS HVMP6 is connected with the drain electrode of described first NMOS tube HVMN2;

A kind of low pressure difference linearity stabilized voltage power supply, comprising:

Low pressure difference linear voltage regulator and current foldback circuit;

Described low pressure difference linear voltage regulator comprises: operational amplifier, power tube, the first feedback resistance, the second feedback resistance;

Described current foldback circuit comprises: current generating circuit and current-limiting circuit;

The first input end of described operational amplifier is connected with reference voltage, the output of described operational amplifier is connected with the grid of described power tube, the drain electrode of described power tube is connected with the first end of described first feedback resistance, second end of described first feedback resistance is connected with the first end of described second feedback resistance and the second input of described operational amplifier respectively, second end ground connection of described second feedback resistance, the first end of described first feedback resistance and the second end of described second feedback resistance are the output of described low pressure difference linear voltage regulator;

Preferably, described current generating circuit comprises:

The technical scheme provided from above the application, relative to prior art, the application has following beneficial effect:

The current foldback circuit of the low pressure difference linear voltage regulator that the application provides and low pressure difference linearity stabilized voltage power supply, comprise current generating circuit and current-limiting circuit, the follow current that described current generating circuit raises for generation of the rising with described supply voltage, and described follow current is exported to described first NMOS tube in described current-limiting circuit; Described current-limiting circuit is used for described output current being restricted to according to described follow current the Limited Current reduced with the rising of described supply voltage when the output current of described low pressure difference linear voltage regulator exceedes predetermined threshold value.Like this, the adjoint electric current that current generating circuit produces increases with the increase of supply voltage, the output current of described low pressure difference linear voltage regulator is not limited with electric current itself, but the Limited Current making current-limiting circuit export reduces along with the increase of supply voltage, namely when supply voltage raises, the output current of low pressure difference linear voltage regulator is reduced, thus the advancing the speed of power output of low pressure difference linear voltage regulator when suppressing supply voltage to raise, the advancing the speed of temperature of low pressure difference linear voltage regulator when raising to suppress supply voltage, the LDO caused because supply voltage increases rapidly is avoided to cross cause thermal damage.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present application or technical scheme of the prior art, be briefly described to the accompanying drawing used required in embodiment or description of the prior art below, apparently, the accompanying drawing that the following describes is only some embodiments recorded in the application, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to these accompanying drawings.

The structural representation of the current foldback circuit of a kind of low pressure difference linear voltage regulator that Fig. 1 provides for the application;

The structural representation of the current foldback circuit of the another kind of low pressure difference linear voltage regulator that Fig. 2 provides for the application;

The structural representation of the current foldback circuit of another low pressure difference linear voltage regulator that Fig. 3 provides for the application;

The structural representation of the current foldback circuit of another low pressure difference linear voltage regulator that Fig. 4 provides for the application.

Embodiment

For making the object of the utility model embodiment, technical scheme and advantage clearly, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, instead of whole embodiments.Based on the embodiment in the utility model, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.

In order to make those skilled in the art person understand the application's scheme better, below in conjunction with accompanying drawing, the application is described in further detail.

The structural representation of the current foldback circuit of a kind of low pressure difference linear voltage regulator that Fig. 1 provides for the application.

The current foldback circuit of the low pressure difference linear voltage regulator that the embodiment of the present application provides, for providing overcurrent protection to low pressure difference linear voltage regulator.

With reference to shown in Fig. 1, the low pressure difference linear voltage regulator LDO of band overcurrent protection function, mainly comprises operational amplifier EA, power tube HVMP9, the first feedback resistance R5, and the second feedback resistance R6, and current foldback circuit.Current foldback circuit comprises current generating circuit and current-limiting circuit;

The first input end of described operational amplifier EA is connected with reference voltage V ref, the output of described operational amplifier EA is connected with the grid of described power tube HVMP9, the drain electrode of described power tube HVMP9 is connected with the first end of described first feedback resistance R5, second end of described first feedback resistance R5 is connected with the first end of described second feedback resistance R6 and second input of described operational amplifier EA respectively, first feedback resistance R5 and the second feedback resistance R6 produces a feedback signal transmission to second input of operational amplifier EA by dividing potential drop, the second end ground connection of described second feedback resistance R6, the first end of described first feedback resistance R5 and second end of described second feedback resistance R6 are the output of described low pressure difference linear voltage regulator, for connecting load RL.

Current-limiting circuit comprises the first PMOS HVMP7, the second PMOS HVMP8, the first NMOS tube HVMN2, the second NMOS tube HVMN3 and the first resistance R4.Wherein, HVMP7 and HVMP8 is high voltage PMOS device, HVMN2 and HVMN3 is high pressure NMOS part.

In the embodiment of the present application, with reference to shown in Fig. 1, the source electrode of described first PMOS HVMP7 is connected with supply voltage VDD, the grid of described first PMOS HVMP7 is connected with the grid of described power tube HVMP9, and the drain electrode of described first PMOS HVMP7 is connected with the drain electrode of described first NMOS tube HVMN2;

The source ground of described first NMOS tube HVMN2, the drain electrode of described first NMOS tube HVMN2 is connected with the grid of the grid of described first NMOS tube HVMN2 and described second NMOS tube HVMN3;

The source ground of described second NMOS tube HVMN3, the drain electrode of described second NMOS tube HVMN3 is connected with the first end of described first resistance R4 and the grid of described second PMOS HVMN3;

The source electrode of described second PMOS HVMP8 is connected with described supply voltage VDD, and the drain electrode of described second PMOS HVMP8 is connected with the grid of described power tube HVMP9;

Second end of described first resistance R4 is connected with described supply voltage VDD;

The follow current that described current generating circuit raises for generation of the rising with described supply voltage VDD, and described follow current is exported to the described first NMOS tube HVMN2 in described current-limiting circuit;

Described current-limiting circuit is used for described output current being restricted to according to described follow current the Limited Current reduced with the rising of described supply voltage VDD when the output current of described low pressure difference linear voltage regulator exceedes predetermined threshold value.

The size of power tube HVMP9 is set to the M of HVMP7 doubly, this size refers to the wide of the raceway groove of MOS device and length, namely the electric current of HVMP7 is 1/M times of HVMP9 electric current, the drain and gate of the HVMN2 of the drain electrode diode-connected of HVMP7, HVMN3 grid connects grid and the drain electrode formation mirror of HVMN2, first resistance R4 one end connects the drain electrode of HVMN3, the other end connects supply voltage VDD, operational amplifier EA in course of normal operation, power tube HVMP9, first feedback resistance R5 and the second feedback resistance R6 forms a degeneration factor, there is provided a stable voltage signal can to load RL.Generally because the value of the first feedback resistance R5 and the second feedback resistance R6 is larger, so the electric current of power tube HVMP9 equals the electric current of load RL substantially, particularly in heavy duty situation, when output load current is Iout, power tube HVMP9 electric current I MP9 approximates Iout, the output current IMP9 of the electric current I MP7 certain proportion mirror image HVMP9 of HVMP7 is Iout/M, namely

IMP 7 = \frac{IMP 9}{M} \approx \frac{Iout}{M} - - - (1)

HVMN2 is owing to adopting diode-connected, the electric current I MN2 of HVMN2 equals the electric current I MP7 of HVMP7, the electric current I MN2 of the electric current I MN3 mirror image HVMN2 of HVMN3, namely IMN3=IMN2 is Iout/M, so now the voltage of the first resistance R4 reduces to Vr=IMN3 × R=IMN2 × R=Iout × R/M, wherein R is the resistance of the first resistance R4.When Iout is smaller, Vr is less than the threshold voltage vt hp of HVMP8, so HVMP8 turns off, does not affect normal loop work; When Iout is larger, Vr is greater than the threshold voltage vt hp of HVMP8, and HVMP8 produces pull-up effect.So can reach the effect of power-limiting pipe output current as Vr=Vthp, output current Iout now can be defined as Limited Current Ilim, i.e. the Iout=Ilim when the output current of described low pressure difference linear voltage regulator exceedes predetermined threshold value.

In the embodiment of the present application, the adjoint electric current that current generating circuit produces increases with the increase of supply voltage, can with supply voltage direct proportionality, also can not direct proportionality, the output current of described low pressure difference linear voltage regulator is not limited with electric current itself, but the Limited Current making current-limiting circuit export reduces along with the increase of supply voltage, namely when supply voltage raises, the output current of low pressure difference linear voltage regulator is reduced, thus the advancing the speed of power output of low pressure difference linear voltage regulator when suppressing supply voltage to raise, the advancing the speed of temperature of low pressure difference linear voltage regulator when raising to suppress supply voltage, the LDO caused because supply voltage increases rapidly is avoided to cross cause thermal damage.

The structural representation of the current foldback circuit of the another kind of low pressure difference linear voltage regulator that Fig. 2 provides for the application.

With reference to shown in Fig. 2, the current foldback circuit of the low pressure difference linear voltage regulator that the embodiment of the present application provides, on the basis of the above, described current generating circuit comprises:

3rd PMOS MP1, the 4th PMOS HVMP1, the 5th PMOS HVMP2, the 6th PMOS HVMP3, the 7th PMOS HVMP4, the 8th PMOS HVMP5, the 9th PMOS HVMP6, the 3rd NMOS tube MNBN1, the 4th NMOS tube HVMN1, the 5th NMOS tube MN1, the second resistance R1, the 3rd resistance R2, the 4th resistance R3 and bias current sources IBIAS;

In the embodiment of the present application, MP1 and MNBN1 adopts diode-connected (the grid drain electrode short circuit by self) respectively, the source electrode of MP1 connects power supply, the drain and gate of MP1 connects leakage and the grid of MNBN1, form Diode series structure, one end of the source electrode contact resistance R1 of MNBN1, the other end of R1 connects the source electrode of HVMP1, the drain electrode of HVMP1 connects bias current sources IBIAS, the grid of HVMP1 connects the grid of HVMP2, the grounded drain of HVMP2, the source electrode of HVMP2 connects the source electrode of HVMN1, the grid of HVMN1 connects the source electrode of HVMP1, the drain electrode of HVMN1 connects the drain electrode of the HVMP3 of a diode-connected, the grid of HVMP3 connects the grid of HVMP4.Resistance R2 and R3 forms series resistance, one end ground connection of R3, the grid of another termination R2 and MN1, the resistance R2 mono-termination R3 other end connects the source electrode (being also the source electrode of HVMP2) of HVMN1, the drain and gate of the HVMP5 of the drain electrode diode-connected of MN1, the grid of HVMP5 and the grid of drain electrode and HVMP6 connect and compose mirror.The drain electrode of HVMP4 is connected the drain electrode of HVMP7 with the drain electrode of HVMP6.

If the gate source voltage difference that the gate source voltage difference of MP1 is VGSP1, MNBN1 is VGSMN1, then resistance R1 and bias current sources IBIAS determines the grid voltage V1 of HVMN1 pipe and the relation of supply voltage VDD, that is:

V1＝VDD-IBIAS×R1-VGSP1-VGSMN1(2)

HVMN1 pipe and HVMP2 pipe adopt source electrode to follow anatomical connectivity, and the source voltage V2 size determining HVMP2 pipe depends on grid voltage V1 and the gate source voltage difference VGSN1 of HVMN1 pipe, that is:

V2＝V1-VGSN1(3)

The grid voltage V3 of MN1 pipe depends on the dividing potential drop of V2 and resistance R2, R3, that is:

V3＝V2×R3/(R3+R2)(4)

When supply voltage VDD is wide enough so that V3 is greater than the threshold voltage vt hn of MN1 pipe, the electric current I MN1 that MN1 produces is:

I M N 1 = \frac{1}{2} u C o x \frac{W}{L} {(V 3 - V t h n)}^{2} - - - (5)

Wherein: u is device mobility, Cox is device oxide layer electric capacity, W and L is the wide of device channel and length respectively;

The electric current I MP5 of HVMP5 equals the electric current I MN1 of MN1, and arranging HVMP6 and HVMP5 image current ratio is N1, by the electric current I MP6 of formula (5) known HVMP6 is:

IMP6＝N1×IMP5＝N1×IMN1(6)

The electric current I MP3 flowing through HVMP3 is:

IMP3＝V2/(R2+R3)(7)

Arranging HVMP4 and HVMP3 image current ratio is N2, by the electric current I MP4 of formula (7) known HVMP4 is:

IMP4＝N2×IMP3＝N2×V2/(R2+R3)(8)

HVMN2 adopts diode-connected, and the electric current I MN2 flowing through HVMN2 is:

IMN2＝IMP7+IMP6+IMP4(9)

From formula (1), (6), (8), (9):

I M N 2 = \frac{I O U T}{M} + N 1 \times \frac{1}{2} u C o x \frac{W}{L} {(V 3 - V t h n)}^{2} + N 2 \times \frac{V 2}{R 2 + R 3} - - - (10)

Wherein V2, V3 reference formula (2), (3), (4), namely

V2＝VDD-IBIAS×R1-VGSP1-VGSMN1-VGSN1(11)

V3＝[VDD-IBIAS×R1-VGSP1-VGSMN1-VGSN1]×R3/(R3+R2)(12)

Because VR=IMN3 × R=IMN2 × R=Vthp, can be obtained by formula (10):

I M N 2 = \frac{I \lim}{M} + N 1 \times \frac{1}{2} u C o x \frac{W}{L} {(V 3 - V t h n)}^{2} + N 2 \times \frac{V 2}{R 2 + R 3} = V t h p / R - - - (13)

That is:

I \lim = M \times [V t h p / R - N 1 \times \frac{1}{2} u C o x \frac{W}{L} {(V 3 - V t h n)}^{2} - N 2 \times \frac{V 2}{R 2 + R 3}] - - - (14)

From formula (11), (12), V2, V3 increase with the increase of VDD, are reduced with the increase of V2, V3 by the known Limited Current Ilim of formula (14), so when VDD larger limit electric current I lim is less.

Simultaneously from formula (11), (12), (14), the circuit parameter of adjustment current generating circuit can adjust the rate of change of Limited Current Ilim with supply voltage VDD.

In the current generating circuit that above-described embodiment provides, create the follow current that a part relevant to the source voltage V2 of HVMP2 pipe is directly proportional to supply voltage, create the follow current that a part relevant to the grid voltage V3 of MN1 pipe is directly proportional to supply voltage simultaneously, this two parts follow current outputs in HVMN2 pipe simultaneously, the common factor as affecting Limited Current, makes Limited Current reduce with the increase of VDD.

The application also provides other embodiment, make current generating circuit can produce separately the follow current that to supply voltage be directly proportional relevant to the source voltage V2 of HVMP2 pipe, or produce the follow current that to supply voltage be directly proportional relevant to the grid voltage V3 of MN1 pipe separately, and different follow currents is outputted in HVMN2 pipe respectively, as affecting Limited Current factor, Limited Current is reduced with the increase of VDD.

It should be noted that, when producing the follow current that to supply voltage be directly proportional relevant to the source voltage V2 of HVMP2 pipe separately, or when producing separately the follow current that to supply voltage be directly proportional relevant to the grid voltage V3 of MN1 pipe, the rate of change that the follow current be directly proportional to supply voltage of being correlated with from the source voltage V2 of HVMP2 pipe and the follow current be directly proportional to supply voltage of being correlated with to the grid voltage V3 of MN1 pipe increase with the increase of supply voltage VDD is different.Therefore, when being used alone the follow current that to supply voltage be directly proportional relevant to the source voltage V2 of HVMP2 pipe, or when being used alone the follow current that to supply voltage be directly proportional relevant to the grid voltage V3 of MN1 pipe, the rate of change that limiting circuit reduces with the increase of supply voltage VDD also can be different.

Specific implementation circuit as shown in Figure 3, Figure 4.

The structural representation of the current foldback circuit of another low pressure difference linear voltage regulator that Fig. 3 provides for the application.

With reference to shown in Fig. 3, the current foldback circuit of the low pressure difference linear voltage regulator that the embodiment of the present application provides, for producing the follow current that to supply voltage be directly proportional relevant to the source voltage V2 of HVMP2 pipe separately, described current generating circuit comprises:

In the embodiment of the present application, the source voltage V2 of HVMP2 pipe can increase with the increase of VDD, the principle provided from above-described embodiment, Limited Current Ilim can reduce with the increase of V2, so when VDD larger limit electric current I lim is less, concrete principle refers to above-described embodiment, repeats no more herein.

With reference to shown in Fig. 4, the current foldback circuit of the low pressure difference linear voltage regulator that the embodiment of the present application provides, for producing the follow current that to supply voltage be directly proportional relevant to the grid voltage V3 of MN1 pipe separately, described current generating circuit comprises:

In the embodiment of the present application, the grid voltage V3 of MN1 pipe can increase with the increase of VDD, the principle provided from above-described embodiment, Limited Current Ilim can reduce with the increase of V3, so when VDD larger limit electric current I lim is less, concrete principle refers to above-described embodiment, repeats no more herein.

The application also provides a kind of low pressure difference linearity stabilized voltage power supply, comprising:

Low pressure difference linear voltage regulator and current foldback circuit;

The current-limiting circuit that the application provides can adopt the current-limiting circuit provided in above-described embodiment, and the current generating circuit that the application provides can adopt the current generating circuit provided in above-mentioned any embodiment, repeats no more herein.

It should be noted that, in this article, such as " be greater than " or " exceeding " or " higher than " or " being less than " or " lower than " etc. and so on relationship description, all can be understood as " be greater than and be not equal to " or " be less than and be not equal to ", also can be understood as " being more than or equal to " or " being less than or equal to ", and not necessarily require or imply that be necessary for restriction or intrinsic a kind of situation.

In addition, in this article, the such as relational terms of " first " and " second " etc. and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, in this article, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or equipment.When not more restrictions, the key element limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment comprising described key element and also there is other identical element.

For convenience of description, various unit is divided into describe respectively with function when describing above device.Certainly, the function of each unit can be realized in same or multiple software and/or hardware when implementing the application.

Each embodiment in this specification all adopts the mode of going forward one by one to describe, between each embodiment identical similar part mutually see, what each embodiment stressed is the difference with other embodiments.Especially, for device or system embodiment, because it is substantially similar to embodiment of the method, so describe fairly simple, relevant part illustrates see the part of embodiment of the method.Apparatus and system embodiment described above is only schematic, the wherein said unit illustrated as separating component or can may not be and physically separates, parts as unit display can be or may not be physical location, namely can be positioned at a place, or also can be distributed in multiple network element.Some or all of module wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.Those of ordinary skill in the art, when not paying creative work, are namely appreciated that and implement.

Professional can also recognize further, in conjunction with unit and the algorithm steps of each example of embodiment disclosed herein description, can realize with electronic hardware, computer software or the combination of the two, in order to the interchangeability of hardware and software is clearly described, generally describe composition and the step of each example in the above description according to function.These functions perform with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can use distinct methods to realize described function to each specifically should being used for, but this realization should not thought and exceeds scope of the present utility model.

The software module that the method described in conjunction with embodiment disclosed herein or the step of algorithm can directly use hardware, processor to perform, or the combination of the two is implemented.Software module can be placed in the storage medium of other form any known in random asccess memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technical field.

To the above-mentioned explanation of the disclosed embodiments, professional and technical personnel in the field are realized or uses the utility model.To be apparent for those skilled in the art to the multiple amendment of these embodiments, General Principle as defined herein when not departing from spirit or scope of the present utility model, can realize in other embodiments.Therefore, the utility model can not be restricted to these embodiments shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims

1. the current foldback circuit of a low pressure difference linear voltage regulator, described low pressure difference linear voltage regulator comprises operational amplifier, power tube, first feedback resistance and the second feedback resistance, the first input end of described operational amplifier is connected with reference voltage, the output of described operational amplifier is connected with the grid of described power tube, the drain electrode of described power tube is connected with the first end of described first feedback resistance, second end of described first feedback resistance is connected with the first end of described second feedback resistance and the second input of described operational amplifier respectively, second end ground connection of described second feedback resistance, the first end of described first feedback resistance and the second end of described second feedback resistance are the output of described low pressure difference linear voltage regulator, it is characterized in that, described current foldback circuit comprises:

Current generating circuit and current-limiting circuit;

2. current foldback circuit according to claim 1, is characterized in that, described current generating circuit comprises:

3. current foldback circuit according to claim 1, is characterized in that, described current generating circuit comprises:

4. current foldback circuit according to claim 1, is characterized in that, described current generating circuit comprises:

5. a low pressure difference linearity stabilized voltage power supply, is characterized in that, comprising:

Low pressure difference linear voltage regulator and current foldback circuit;

6. low pressure difference linearity stabilized voltage power supply according to claim 5, is characterized in that, described current generating circuit comprises:

7. low pressure difference linearity stabilized voltage power supply according to claim 5, is characterized in that, described current generating circuit comprises:

8. low pressure difference linearity stabilized voltage power supply according to claim 5, is characterized in that, described current generating circuit comprises: