CN205210877U - Balanced preemphasis circuit and USB driver feedover - Google Patents
Balanced preemphasis circuit and USB driver feedover Download PDFInfo
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- CN205210877U CN205210877U CN201520771153.6U CN201520771153U CN205210877U CN 205210877 U CN205210877 U CN 205210877U CN 201520771153 U CN201520771153 U CN 201520771153U CN 205210877 U CN205210877 U CN 205210877U
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Abstract
The utility model relates to a balanced preemphasis circuit and USB driver feedover, this circuit includes: first order amplifier (101), partial pressure filter network (102), delay element (103), secondary amplification ware (104) and pre -emphasis summing circuit (105), first order amplifier (101) for enlarge the incoming signal amplitude, and output, partial pressure filter network (102) for carry out filtering with the output signal of first order amplifier (101), partial pressure, and output, delay element (103) for the output signal of partial pressure filter network (102) delays, and output, secondary amplification ware (104) for enlarge the recovering with delay element's (103) output signal, the pre -emphasis summing circuit for accept the output signal of first order amplifier (101) and the output signal who accepts secondary amplification ware (102), and carry out pre -emphasis summation operation, and the output operation result. Going on in advance adding rehandle to the signal at the input, having avoided the in -process of signal in the communication channel transmission, the signal generation intersymbol interference is so that lose the problem of data, fine assurance communication quality.
Description
Technical field
The utility model relates to USB igh-speed wire-rod production line field, particularly a kind of feed forward equalization preemphasis circuit and usb driver.
Background technology
In the application of USB high speed transmission of signals, because communication channel presents low-pass characteristic, the amplitude of the high-frequency signal that transmitting terminal sends, can be disturbed by code stream after by channel, even can obliterated data time more serious.In order to address this problem, pre-emphasis process can be carried out at transmitting terminal to signal.
The pre-emphasis process of digital signal needs the cooperation of clock, and the pre-emphasis process of simulating signal then cannot add clock, adds the waveform of clock meeting crash simulation signal.Therefore, the delay process for simulating signal then needs to carry out under the prerequisite not destroying waveform.Often comprise a lot of frequency content in high speed transmission of signals, therefore to continuous time time delay chain design propose very high requirement.On the one hand, requiring that time delay chain has identical gain to different frequency composition, when inputting identical amplitude, avoiding the output of different amplitude as far as possible; On the other hand, enough delay length be ensured, export correct waveform with the pre-emphasis summing circuit after guaranteeing.
Utility model content
The utility model is in order to solve prior art high speed signal some problems existing for the process of traffic channel: in order to realize high-speed data in the zero-decrement transmission of communication channel, thus provide a kind of feed forward equalization preemphasis circuit and usb driver.
To achieve these goals, first aspect, the utility model provides a kind of feed forward equalization preemphasis circuit, and this circuit comprises: first order amplifier, divider filter network, delay unit, second level amplifier and pre-emphasis summing circuit; Wherein,
First order amplifier, for amplifying input signal amplitude, and exports; Divider filter network, for the output signal of first order amplifier being carried out filtering, dividing potential drop, and exports; Delay unit, for the output signal of divider filter network is carried out time delay, and exports; Second level amplifier, recovers for the output signal of delay unit being carried out amplification; Pre-emphasis summing circuit, for accepting the output signal of first order amplifier and accepting the output signal of second level amplifier, and carries out pre-emphasis sum operation, and output function result.
Preferably, divider filter network comprises: ac coupling capacitor, and first order amplifier and delay unit are isolated by ac coupling capacitor; Exchange derided capacitors, interchange derided capacitors and ac coupling capacitor form range of decrease circuit; Direct current biasing resistance, direct current biasing resistance provides DC common-mode to be biased for delay unit input, forms high-pass filtering network simultaneously, carry out filtering, and export low frequency signal with ac coupling capacitor.
Preferably, the gain of range of decrease circuit is less than unity gain.
Preferably, delay unit carries out the delay transmission of continuous time to the output signal of divider filter network, and in transmittance process, ensure that the signal gain under each frequency is consistent.
Second aspect, the utility model provides a kind of usb driver, and this driver comprises above-mentioned feed forward equalization preemphasis circuit.
The third aspect, the utility model provides a kind of feed forward equalization pre-emphasis disposal route, and the method comprises the following steps:
Amplifieroperation is carried out to input signal amplitude, and exports;
Input signal amplitude after amplifying is carried out filtering, point press operation, and export;
Output signal after filtering, point press operation is carried out delay operation, and exports;
Output signal after delay operation is carried out amplification to recover;
Pre-emphasis sum operation is carried out to the input signal amplitude after amplification and the output signal after amplifying recovery, and output function result.
Carry out pre-emphasis process at input end to signal, avoid signal in the process of traffic channel, signal generation intersymbol interference, so that the problem of obliterated data, well ensure that communication quality.
Accompanying drawing explanation
In order to the technical scheme of the utility model embodiment is more clearly described, below the accompanying drawing used required in describing embodiment is done and introduce simply, apparently, accompanying drawing in the following describes is only embodiments more of the present utility model, for those of ordinary skill in the art, under the prerequisite not paying creative work, can also expand according to these accompanying drawings.
Fig. 1 is the usb driver structural representation of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver;
Fig. 2 is the structural representation of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver;
Fig. 3 is the structural representation of the divider filter network of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver;
Fig. 4 is the structure flow chart of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver.
Embodiment
Below by drawings and Examples, the technical scheme of the embodiment of the present application is described in further detail.
Fig. 1 is the usb driver structural representation of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver.As shown in Figure 1, usb driver comprises feed forward equalization pre-emphasis treatment circuit.
Fig. 2 is the structural representation of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver.As shown in Figure 2, feed forward equalization preemphasis circuit comprises first order amplifier 101, divider filter network 102, delay unit 103, second level amplifier 104 and pre-emphasis summing circuit 105.
First order amplifier 101 pairs of input signals carry out amplitude amplification, and by the signal transmission after amplification to rear class pre-emphasis summing circuit 105 and divider filter network 102; Divider filter network 102, for the output signal of first order amplifier 101 is carried out filtering, dividing potential drop, and export, first order amplifier 101 output voltage is carried out the reduction in amplitude, to ensure that high speed signal is unlikely to make circuit saturated in delay unit 103 transmitting procedure, cause distorted signals, simultaneously by the output common mode point voltage of first order amplifier 101 and continuous time delay unit 103 input common-mode point voltage isolate, the input common-mode point voltage of delay unit 103 continuous time can be biased separately, to ensure optimum duty; Delay unit 103, carried out time delay to the signal after amplitude reduces, ensured that signal has identical gain in each frequency simultaneously continuous time; Second level amplifier 104, carries out the recovery of amplitude by the signal after time delay, to ensure that the signal after time delay is identical with the signal amplitude that first order amplifier exports, then pass to rear class pre-emphasis summing circuit.
Fig. 3 is a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and and the structural representation of divider filter network of usb driver.As shown in Figure 3, divider filter network 102 comprises ac coupling capacitor C1, exchanges derided capacitors C2 and direct current biasing resistance R.
First order amplifier 101 and delay unit 103 are isolated by ac coupling capacitor C1; Exchange derided capacitors C2 and ac coupling capacitor C1 and form range of decrease circuit; Direct current biasing resistance R provides DC common-mode to be biased for delay unit 103 input, forms high-pass filtering network simultaneously, carry out filtering, and export low frequency signal with ac coupling capacitor C1.
Particularly, the gain of range of decrease circuit is less than unity gain.
Fig. 4 is the structure flow chart of a kind of feed forward equalization preemphasis circuit of providing of the utility model embodiment and usb driver.As shown in Figure 4, disposal route comprises the following steps:
Step 200, carries out amplifieroperation to input signal amplitude, and exports;
Step 201, by amplify after input signal amplitude carry out filtering, point press operation, and to export;
Step 202, carries out delay operation by the output signal after filtering, point press operation, and exports;
Step 203, carries out amplification and recovers by the output signal after delay operation;
Step 204, the output signal after recovering the input signal amplitude after amplification and described amplification carries out pre-emphasis sum operation, and output function result.
Carry out pre-emphasis process at input end to signal, avoid signal in the process of traffic channel, signal generation intersymbol interference, so that the problem of obliterated data, well ensure that communication quality.
It should be noted last that, above embodiment is only in order to illustrate the technical solution of the utility model and unrestricted.Although be described in detail the utility model with reference to embodiment, those of ordinary skill in the art is to be understood that, modify to the technical solution of the utility model or be equal to the spirit and scope of replacing and not departing from technical solutions of the utility model, it all should be encompassed in the middle of claim scope of the present utility model.
Claims (5)
1. a feed forward equalization preemphasis circuit, it is characterized in that, comprising: first order amplifier (101), divider filter network (102), delay unit (103), second level amplifier (104) and pre-emphasis summing circuit (105);
Described first order amplifier (101), for amplifying input signal amplitude, and exports;
Described divider filter network (102), for the output signal of described first order amplifier (101) is carried out filtering, dividing potential drop, and exports;
Described delay unit (103), for the output signal of described divider filter network (102) is carried out time delay, and exports;
Described second level amplifier (104), recovers for the output signal of described delay unit (103) being carried out amplification;
Described pre-emphasis summing circuit, for accepting the output signal of described first order amplifier (101) and accepting the output signal of described second level amplifier (102), and carries out pre-emphasis sum operation, and output function result.
2. circuit according to claim 1, is characterized in that, described divider filter network (102) comprising:
Ac coupling capacitor (C1), described first order amplifier (101) and described delay unit (103) are isolated by described ac coupling capacitor (C1);
Exchange derided capacitors (C2), described interchange derided capacitors (C2) and described ac coupling capacitor (C1) form range of decrease circuit;
Direct current biasing resistance (R), described direct current biasing resistance (R) for described delay unit (103) input provide DC common-mode be biased, form high-pass filtering network with described ac coupling capacitor (C1) simultaneously, filtering is carried out to low frequency signal, and exports.
3. circuit according to claim 2, is characterized in that, the gain of described range of decrease circuit is less than unity gain.
4. circuit according to claim 1, it is characterized in that, the output signal of described delay unit (103) to described divider filter network (102) carries out the delay transmission of continuous time, and in transmittance process, ensure that the signal gain under each frequency is consistent.
5. a usb driver, is characterized in that, comprises the feed forward equalization preemphasis circuit as described in claim arbitrary in claim 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520771153.6U CN205210877U (en) | 2015-09-30 | 2015-09-30 | Balanced preemphasis circuit and USB driver feedover |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520771153.6U CN205210877U (en) | 2015-09-30 | 2015-09-30 | Balanced preemphasis circuit and USB driver feedover |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205210877U true CN205210877U (en) | 2016-05-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520771153.6U Withdrawn - After Issue CN205210877U (en) | 2015-09-30 | 2015-09-30 | Balanced preemphasis circuit and USB driver feedover |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205210877U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105243041A (en) * | 2015-09-30 | 2016-01-13 | 英特格灵芯片(天津)有限公司 | Feedforward equalization pre-emphasis circuit, processing method and USB driver |
| CN110300076A (en) * | 2019-07-24 | 2019-10-01 | 南方科技大学 | The feed forward equalizer of PAM-4 modulation format |
-
2015
- 2015-09-30 CN CN201520771153.6U patent/CN205210877U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105243041A (en) * | 2015-09-30 | 2016-01-13 | 英特格灵芯片(天津)有限公司 | Feedforward equalization pre-emphasis circuit, processing method and USB driver |
| CN105243041B (en) * | 2015-09-30 | 2018-08-28 | 英特格灵芯片(天津)有限公司 | A kind of feed forward equalization preemphasis circuit and processing method, usb driver |
| CN110300076A (en) * | 2019-07-24 | 2019-10-01 | 南方科技大学 | The feed forward equalizer of PAM-4 modulation format |
| CN110300076B (en) * | 2019-07-24 | 2022-05-31 | 南方科技大学 | Feed forward equalizer for PAM-4 modulation format |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210208 Address after: 100094 Room 601, unit 3, 6 / F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Patentee after: Beijing Weihao integrated circuit design Co.,Ltd. Address before: Room 2701-1, building 2, TEDA service outsourcing park, 19 Xinhuan West Road, Tianjin Development Zone, Binhai New Area, Tianjin, 300457 Patentee before: INTERNATIONAL GREEN CHIP (TIANJIN) Co.,Ltd. |
|
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20160504 Effective date of abandoning: 20180828 |
|
| AV01 | Patent right actively abandoned |
Granted publication date: 20160504 Effective date of abandoning: 20180828 |
|
| CU01 | Correction of utility model | ||
| CU01 | Correction of utility model |
Correction item: Patentee|Address Correct: Ingerling chip (Tianjin) Co., Ltd.|Room 2701-1, building 2, TEDA service outsourcing park, 19 Xinhuan West Road, Tianjin Development Zone, Binhai New Area, Tianjin, 300457 False: Beijing Weihao integrated circuit design Co., Ltd.|100094 Room 601, unit 3, 6 \F, building 2, yard 9, FengHao East Road, Haidian District, Beijing Number: 09-02 Volume: 37 |