CN205140943U - Electronic device - Google Patents

Electronic device Download PDF

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Publication number
CN205140943U
CN205140943U CN201520764718.8U CN201520764718U CN205140943U CN 205140943 U CN205140943 U CN 205140943U CN 201520764718 U CN201520764718 U CN 201520764718U CN 205140943 U CN205140943 U CN 205140943U
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China
Prior art keywords
encapsulated layer
matrix substrate
grid matrix
encapsulating material
integrated circuit
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Active
Application number
CN201520764718.8U
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Chinese (zh)
Inventor
K-Y·吴
Y·马
张学仁
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STMicroelectronics SRL
STMicroelectronics Pte Ltd
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STMicroelectronics Pte Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48105—Connecting bonding areas at different heights
    • H01L2224/48106—Connecting bonding areas at different heights the connector being orthogonal to a side surface of the semiconductor or solid-state body, e.g. parallel layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/162—Disposition
    • H01L2924/16251—Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The utility model relates to an electronic device includes: the grid matrix substrate, the grid matrix substrate has a plurality of connections on its lower surface, the integrated circuit nude film, the integrated circuit nude film is in and have a plurality of bonding welding pads on the upper surface of grid matrix substrate, many bonded wiring, the bonded wiring respectively will the bonding welding pad is coupled to the grid matrix substrate, first encapsulated layer, first encapsulated layer is in the integrated circuit nude film with first encapsulating material has on the bonded wiring, the radiator, the radiator by the grid matrix substrate bear in first encapsulated layer top and with first encapsulated layer is spaced apart, and second encapsulated layer, the second encapsulated layer is in have on the first encapsulated layer and be different from the second encapsulating material of first encapsulating material will be and will the radiator embedding is in in the second encapsulated layer.

Description

Electronic device
Technical field
The utility model relates to electronic device, and relates more specifically to the electronic device comprising integrated circuit.
Background technology
Along with electronic device becomes relatively little, encapsulation may become and make people interested especially.Such as, low k interlayer dielectric (ILD) material may be used for replacing such as SiO 2iLD is to reduce interconnect delay.
Low KILD material is incorporated in silicon and may applies new challenge to high wiring density encapsulation.Particularly, in low k interconnection, intrinsic weak bonding makes silicon that the fault of ILD cracking or layering more easily occur usually can be called.ILD cracking or layering cause the fault of electronic device, such as, during fault often occurs in temperature cycling test.The technical papers being entitled as " the encapsulation challenge (PackagingChallengesinLow-kSiliconwithThermallyEnhancedBa llGridArray (TE-PBGA)) with in the low k silicon of the ball grid array (TE-PBGA) of temperature enhancing " delivered in EPTC2010 by people such as special human relations (Tran) has highlighted the problem of low KILD material.
Described in the technical papers people such as special human relations, the reason having determined low k fault is the uneven distribution of the composite filled thing of mould in the nude film turning relative with mould gate.The radiator inserted hinders the flowing of mould compound during transfer modling process, which results in filler loss larger in this turning.
Utility model content
The object of embodiment of the present disclosure is to provide a kind of electronic device, to solve the aforementioned problems in the prior at least in part.
A kind of method manufacturing electronic device can comprise be positioned integrated circuit (IC) nude film to have on the lower surface thereof the grid matrix substrate of multiple connection upper surface on and with many bonding wiring, the bonding welding pad of multiple correspondences of this IC nude film is coupled to this grid matrix.The method can also be included in form the first encapsulated layer on this IC nude film and these bonding wiring and after this first encapsulated layer of formation by radiator location over the substrate above this first encapsulated layer.The method may further include and on this first encapsulated layer, forms the second encapsulated layer and be embedded in this second encapsulated layer by this radiator.Thus, the method can reduce the fault of electronic device, such as, by reducing two step encapsulatings of ILD cracking and layering.
Such as, this IC nude film can be rectangular shape.Form this first encapsulated layer can comprise and this first encapsulated layer is formed as extending across and covers each turning of the IC nude film of this rectangular shape.
This first and second encapsulated layer can comprise identical encapsulating material separately.In other embodiments, this first and second encapsulated layer can comprise different encapsulating materials separately.This IC nude film can comprise low k interlayer dielectric.
Such as, form this first encapsulated layer the first mould can be comprised to be positioned on this grid matrix substrate, with the first encapsulating material fill this first mould, solidify this first encapsulating material and remove this first mould.Form this second encapsulated layer the second mould can be comprised to be positioned on this grid matrix substrate, with the second encapsulating material fill this second mould, solidify this second encapsulating material and remove this second mould.Such as, form this first encapsulated layer can be included in and to apply encapsulating material body on this IC and solidify this encapsulating material body.
Device aspect relates to the electronic device that one can comprise grid matrix substrate and integrated circuit (IC) nude film, this grid matrix substrate has multiple connection on the lower surface thereof, and this integrated circuit die is on the upper surface of this grid matrix substrate and have multiple bonding welding pad.This electronic device can also comprise respectively these bonding welding pads are coupled to this grid matrix many bonding wiring, first encapsulated layer with the first encapsulating material on this IC nude film and these bonding wiring and by this grid matrix substrate supporting above this first encapsulated layer and with the isolated radiator of this first encapsulated layer.This electronic device may further include the second encapsulated layer, and this second encapsulated layer has the second encapsulating material of being different from this first encapsulating material and is embedded in this second encapsulated layer by this radiator on this first encapsulated layer.
According to embodiment, described integrated circuit die is rectangular shape, and wherein, described first encapsulated layer is formed to extend across and covers each turning of the integrated circuit die of described rectangular shape
According to embodiment, described integrated circuit die comprises low k interlayer dielectric.
In embodiment of the present disclosure, the formation of the first and second encapsulated layers advantageously can providing package closure material in those turnings relative with mould gate of nude film evenly distribution.
Accompanying drawing explanation
Figure 1A to Fig. 1 I is the diagrammatic cross-sectional view of this electronic device when the method for the manufacture electronic device according to an embodiment manufactures electronic device.
Fig. 2 A to Fig. 2 G is the diagrammatic cross-sectional view of this electronic device when the method for the manufacture electronic device according to another embodiment manufactures electronic device.
Fig. 3 is the perspective cut view of the electronic device according to an embodiment.
Embodiment
Hereafter with reference to these accompanying drawings, the utility model is more fully described now, preferred embodiment of the present utility model shown in the drawings.But the utility model can embody by many different forms, and should not be interpreted as the restriction of the embodiment be subject to listed by this.On the contrary, provide these embodiments so that this disclosure will be thorough and complete, and scope of the present utility model will be passed on fully to those skilled in the art.Run through similar numeral in full and refer to similar element, and apostrophe symbol is used to indicate like in alternative embodiments.
Initial reference Figure 1A to Fig. 1 I, describes a kind of method manufacturing electronic device 20.The method comprises and being positioned on the upper surface 23 of grid matrix substrate 22 by integrated circuit (IC) nude film 21.IC nude film 21 can comprise low k interlayer dielectric 28 and have rectangular shape (Figure 1A) illustratively.Certainly, IC nude film 21 can have other and/or additional interlayer of identical or different material, and can have different shapes.
Grid matrix substrate 22 has multiple connection 25 on its lower surface 24.Grid matrix substrate 22 is ball grid array (BGA) substrate illustratively, and plastic ball grid array substrate (PBGA) more specifically.Certainly, as the skilled person will recognize, grid matrix substrate 22 can be the substrate of another kind of type.
The method comprises, with many bonding wiring 27, the bonding welding pad 26 of multiple correspondences of this IC nude film 21 is coupled to this grid matrix substrate 22 (Figure 1B).The method is also included on this IC nude film 21 and these bonding wiring 27 and forms the first encapsulated layer 30.This first encapsulated layer 30 is formed as extending across and covers each turning of the IC nude film 21 of this rectangular shape.
In order to form this first encapsulated layer 30, the first mould 31 is positioned to (Fig. 1 C) on this grid matrix substrate 22.Fill this first mould 31 with the first encapsulating material 32 and it is cured (Fig. 1 d).Then, the first mould 31 (Fig. 1 E) is removed.First encapsulating material 32 does not extend to the end of this grid matrix substrate 22 illustratively.
The method is included in further to be formed after this first encapsulated layer and is positioned on grid matrix substrate 22 by radiator 51, and this radiator is above this first encapsulated layer 30 and (Fig. 1 F) spaced away.Such as, radiator 51 can be copper, and is positioned such that illustratively to be exposed on the upper surface of electronic device 20.
After the radiator 51 of location, the method is included in further and forms the second encapsulated layer 40 on this first encapsulated layer 30 and be embedded in this second encapsulated layer by radiator 51.Second encapsulated layer 40 by the second mould 41 being positioned to (Fig. 1 G) on this grid matrix substrate 22, fill this second mould with the second encapsulating material 42 and solidify this second encapsulating material (Fig. 1 H) and remove this second mould (Fig. 1 I) and formed.This first and second encapsulating material can be respectively identical naturally material.In certain embodiments, this first and second encapsulating material can be different material.
With reference now to Fig. 2 A to Fig. 2 G, in another embodiment, the first encapsulated layer 30' is formed by applying the first encapsulating material main body 55' on IC nude film 21'.Such as, this first encapsulating material main body 55'(Fig. 2 C) be ball topping material.More specifically, this first encapsulating material main body 55' can be low modulus ball top resin, and this resin can be thermosetting resin or thermoplastic resin.In other words, mould is not used.As the skilled person will recognize, low modulus ball top resin such as can advantageously for chip on board technology provides the encapsulation means of relatively low cost.
Although be to be noted that and be not specifically described, these method steps corresponding to Fig. 2 A to Fig. 2 B are similar to about those method steps described by Figure 1A to Figure 1B.Allow to be cured this first encapsulating material main body 55'.
Be similar to embodiment as described above, and particularly about Fig. 1 F, radiator 51' is positioned on grid matrix substrate 22' after being included in further and forming this first encapsulated layer by the method for the present embodiment, and this radiator is above this first encapsulated layer 30' and (Fig. 2 D) spaced away.
After the radiator 51' of location, the method is included in further and forms the second encapsulated layer 40' on this first encapsulated layer 30' and be embedded in this second encapsulated layer by radiator 51'.Second encapsulated layer 40' by the second mould 41' being positioned to (Fig. 2 E) on this grid matrix substrate 22', fill this second mould with the second encapsulating material and solidify this second encapsulating material (Fig. 2 F) and remove this second mould (Fig. 2 G) and formed.Certainly, in certain embodiments, alternative second mould and the second encapsulating material can be come with the second encapsulating material main body (such as, ball topping material).
Really, as the skilled person will recognize, the formation of the first and second encapsulated layers advantageously can providing package closure material in those turnings relative with mould gate of nude film evenly distribution.In prior art encapsulating method, radiator hinders the flowing of encapsulating material usually during transfer modling process, which results in encapsulating material loss larger in this turning.The two-stage process forming the first and second encapsulated layers can be provided in the loss of the minimizing in the turning of nude film, and therefore can reduce fault.
Other reference diagram 3 now, device aspect relates to a kind of electronic device 20 comprising grid matrix substrate 22 and IC nude film 21, this grid matrix substrate has multiple connection 25 on its lower surface 24, and this IC nude film is on upper surface 23 and have multiple bonding welding pad 26.This electronic device 20 also comprises many bonding wiring 27 respectively these bonding welding pads 26 being coupled to this grid matrix substrate 22 and first encapsulated layer 30 with the first encapsulating material on this IC nude film 21 and these bonding wiring 27.Radiator 51 to be carried on above this first encapsulated layer 30 by this grid matrix substrate 22 and spaced apart with this first encapsulated layer.Second encapsulated layer 40 with the second encapsulating material being different from this first encapsulating material is on this first encapsulated layer 30 and be embedded in this second encapsulated layer by this radiator 51.
That benefits from the instruction presented in aforementioned description and relevant drawings those skilled in the art will recognize that a lot of amendment of the present utility model and other embodiments.Therefore, be to be understood that the utility model is not limited to disclosed specific embodiment, and those amendments and embodiment are intended to be included in the scope of appended claims.

Claims (3)

1. an electronic device, is characterized in that, comprising:
Grid matrix substrate, described grid matrix substrate has multiple connection on the lower surface thereof;
Integrated circuit die, described integrated circuit die is on the upper surface of described grid matrix substrate and have multiple bonding welding pad;
Many bonding wiring, described bonding welding pad is coupled to described grid matrix substrate by described bonding wiring respectively;
First encapsulated layer, described first encapsulated layer has the first encapsulating material on described integrated circuit die and described bonding wiring;
Radiator, described radiator is with described first encapsulated layer spaced apart above described first encapsulated layer by described grid matrix substrate supporting; And
Second encapsulated layer, described second encapsulated layer has the second encapsulating material of being different from described first encapsulating material and is embedded in described second encapsulated layer by described radiator on described first encapsulated layer.
2. electronic device as claimed in claim 1, it is characterized in that, described integrated circuit die is rectangular shape, and wherein, described first encapsulated layer is formed to extend across and covers each turning of the integrated circuit die of described rectangular shape.
3. electronic device as claimed in claim 1, it is characterized in that, described integrated circuit die comprises low k interlayer dielectric.
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US14/585,566 2014-12-30

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CN105742192A (en) * 2014-12-30 2016-07-06 意法半导体有限公司 Method of making an electronic device including two-step encapsulation and related devices

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WO2020101706A1 (en) 2018-11-16 2020-05-22 Hewlett-Packard Development Company, L.P. Two-step molding for a lead frame
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CN109742032A (en) 2019-05-10
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US20160190029A1 (en) 2016-06-30
CN105742192A (en) 2016-07-06

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