CN205123240U - Electrostatic protection circuit is prevented to mainboard - Google Patents
Electrostatic protection circuit is prevented to mainboard Download PDFInfo
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- CN205123240U CN205123240U CN201520696624.1U CN201520696624U CN205123240U CN 205123240 U CN205123240 U CN 205123240U CN 201520696624 U CN201520696624 U CN 201520696624U CN 205123240 U CN205123240 U CN 205123240U
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Abstract
The utility model provides an electrostatic protection circuit is prevented to mainboard, include: output interface, electrostatic protection module and IO chip, two signal lines of IO chip are connected with the electrostatic protection module through the difference wire pair respectively, electrostatic protection module ground connection, the IO chip pass through the connector cable with the output interface is connected. The utility model discloses when ESD or surge introduction circuit, can pass through the energy of ESD or surge the electrostatic protection module place of working of releasing to play the effect of protection back level IO chip, including the protection of IO chip integrated ESD just can form the dual electrostatic protection of preventing, promote the probability that prevents the mainboard and burnt out greatly, also can effectively reduce the probability that the IO chip is burnt out simultaneously.
Description
Technical field
The utility model relates to a kind of electrostatic discharge protective circuit, particularly relates to a kind of mainboard anti-static protection circuit.
Background technology
A lot of hardware product has antistatic to design now, the mainly inner integrated simple ESD element of IC, Main Function is the interference preventing the ESD of IC inside generation and outside slight ESD grade, and adopt simple ESD element, as TVS diode, build reverse bias breakdown voltage at a few hectovolt to the diode only between a few volt, it is essentially unidirectional device, and protected mode is voltage clamp; This mode inner integrated at IC, ESD degree of protection is low, because IC only considers IC itself and main utilization domain design at the beginning of design, considers that the IC sensitivity be inherently only directed to during signal accepts does a protection; For utilization field, just only can consider the large range of application at the beginning of IC design, natively not comprehensive in design.Such as military, industry and civilian etc. difference are just very large, and the impact etc. produced in the change of operational environment, operating structure, base material and auxiliary material etc. is all considered complete, and protected effect is not obvious.
Summary of the invention
Technical problem to be solved in the utility model needs to provide a kind of can greatly promote the probability preventing mainboard PCB to be burned, and also effectively reduces IO chip by the probability of burning simultaneously, and then play the mainboard anti-static protection circuit of multiple-protection effect.
To this, the utility model provides a kind of mainboard anti-static protection circuit, comprising: output interface, electrostatic protection module and IO chip; Two holding wires of described IO chip are connected with electrostatic protection module respectively by differential lines pair, described electrostatic protection module ground; Described IO chip is connected with described output interface by connector cable.
Further improvement of the utility model is, also comprise electric capacity C1, electric capacity C2, resistance R3 and resistance R4, a holding wire of described IO chip is connected with one end of resistance R3, the other end of described resistance R3 is connected with one end of described electric capacity C1, and the other end of described electric capacity C1 is connected with electrostatic protection module; Another root holding wire of described IO chip is connected with one end of resistance R4, and the other end of described resistance R4 is connected with one end of described electric capacity C2, and the other end of described electric capacity C2 is connected with electrostatic protection module.
Further improvement of the utility model is, also comprises resistance R1 and resistance R2, and one end that described electric capacity C1 is connected with described electrostatic protection module is connected to one end of described resistance R1, and the other end of described resistance R1 is connected with output interface; One end that described electric capacity C2 is connected with described electrostatic protection module is connected to one end of described resistance R2, and the other end of described resistance R2 is connected with output interface.
Further improvement of the utility model is, described electrostatic protection module comprises energy bleeder.
Further improvement of the utility model is, described electrostatic protection module comprises the first diode, the second diode, the 3rd diode, the 4th diode, the 5th diode, the 6th diode, the 7th diode and the 8th diode; The plus earth of described first diode, the negative electrode of described first diode is connected with the anode of described second diode, and the negative electrode of described second diode is connected with power supply; The plus earth of described 3rd diode, the negative electrode of described 3rd diode is connected with the anode of described 4th diode, and the negative electrode of described 4th diode is connected with power supply; The plus earth of described 5th diode, the negative electrode of described 5th diode is connected with the anode of described 6th diode, and the negative electrode of described 6th diode is connected with power supply; The plus earth of described 7th diode, the negative electrode of described 7th diode is connected with the anode of described 8th diode, and the negative electrode of described 8th diode is connected with power supply.
Further improvement of the utility model is, a holding wire of described IO chip is connected with the anode of described 4th diode with the negative electrode of described 3rd diode respectively.
Further improvement of the utility model is, another root holding wire of described IO chip is connected with the anode of described 6th diode with the negative electrode of described 5th diode respectively.
Further improvement of the utility model is, described electrostatic protection module also comprises voltage stabilizing didoe, the plus earth of described voltage stabilizing didoe, and the negative electrode of described voltage stabilizing didoe is connected with power supply.
Compared with prior art, the beneficial effects of the utility model are: two holding wires of described IO chip are connected with electrostatic protection module respectively by differential lines pair, described electrostatic protection module ground, described IO chip is connected with described output interface by connector cable, and then when ESD or surge introduce circuit, the energy of ESD or surge can be released to place of working by described electrostatic protection module, thus play the effect of protection rear class IO chip, on this basis, add that the integrated esd protection of IO chip internal just can form dual antistatic protection, greatly improve the probability preventing mainboard to be burned, also effectively can reduce IO chip by the probability of burning simultaneously.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of a kind of embodiment of the utility model;
Fig. 2 is the circuit theory diagrams of a kind of embodiment of the utility model.
Embodiment
Below in conjunction with accompanying drawing, preferably embodiment of the present utility model is described in further detail.
As shown in Figure 1, this example provides a kind of mainboard anti-static protection circuit, comprising: output interface J1, electrostatic protection module D1 and IO chip U1; Two holding wires of described IO chip U1 are connected with electrostatic protection module D1 respectively by differential lines pair, described electrostatic protection module D1 ground connection; Described IO chip U1 is connected with described output interface J1 by connector cable.
The operation principle that described differential lines is right is that the signal making to receive equals two complementations and difference between the signal of reference each other each other, therefore greatly can reduce the electrical noise effect of signal; Described differential lines to being symmetrical differential lines, differential lines centering, positive and negative both sides all must all the time under identical environment along transmission path transmission signal.Connector cable is connector cable.
As depicted in figs. 1 and 2, this example also comprises electric capacity C1, electric capacity C2, resistance R3, resistance R4, resistance R1 and resistance R2, a holding wire S1 of described IO chip U1 is connected with one end of resistance R3, the other end of described resistance R3 is connected with one end of described electric capacity C1, and the other end of described electric capacity C1 is connected with electrostatic protection module D1; Another root holding wire S2 of described IO chip U1 is connected with one end of resistance R4, and the other end of described resistance R4 is connected with one end of described electric capacity C2, and the other end of described electric capacity C2 is connected with electrostatic protection module D1; One end that described electric capacity C1 is connected with described electrostatic protection module D1 is connected to one end of described resistance R1, and the other end of described resistance R1 is connected with output interface J1; One end that described electric capacity C2 is connected with described electrostatic protection module D1 is connected to one end of described resistance R2, and the other end of described resistance R2 is connected with output interface J1.
This routine described electrostatic protection module D1 comprises energy bleeder.As shown in Figure 2, described electrostatic protection module D1 comprises the first diode, the second diode, the 3rd diode, the 4th diode, the 5th diode, the 6th diode, the 7th diode and the 8th diode; The plus earth of described first diode, the negative electrode of described first diode is connected with the anode of described second diode, and the negative electrode of described second diode is connected with power supply; The plus earth of described 3rd diode, the negative electrode of described 3rd diode is connected with the anode of described 4th diode, and the negative electrode of described 4th diode is connected with power supply; The plus earth of described 5th diode, the negative electrode of described 5th diode is connected with the anode of described 6th diode, and the negative electrode of described 6th diode is connected with power supply; The plus earth of described 7th diode, the negative electrode of described 7th diode is connected with the anode of described 8th diode, and the negative electrode of described 8th diode is connected with power supply; A holding wire S1 of described IO chip U1 is connected with the anode of described 4th diode with the negative electrode of described 3rd diode respectively, concrete, a holding wire S1 of described IO chip U1 is connected with one end of resistance R3, the other end of described resistance R3 is connected with one end of described electric capacity C1, and the other end of described electric capacity C1 is connected with the anode of described 4th diode with the negative electrode of described 3rd diode respectively; Another root holding wire S2 of described IO chip U1 is connected with the anode of described 6th diode with the negative electrode of described 5th diode respectively, concrete, another root holding wire S2 of described IO chip U1 is connected with one end of resistance R4, the other end of described resistance R4 is connected with one end of described electric capacity C2, and the other end of described electric capacity C2 is connected with the anode of described 6th diode with the negative electrode of described 5th diode respectively; Described electrostatic protection module D1 also comprises voltage stabilizing didoe, the plus earth of described voltage stabilizing didoe, and the negative electrode of described voltage stabilizing didoe is connected with power supply.
Two holding wires of this routine described IO chip U1 are connected with electrostatic protection module D1 respectively by differential lines pair, described electrostatic protection module D1 ground connection, described IO chip U1 is connected with described output interface J1 by connector cable, and then when ESD or surge introduce circuit, the energy of ESD or surge can be released to place of working by described electrostatic protection module D1, thus play the effect of protection rear class IO chip U1, add that the inner integrated esd protection of IO chip U1 can form dual antistatic protection on this basis, greatly improve the probability preventing mainboard to be burned, also effectively can reduce IO chip U1 by the probability of burning simultaneously.
This example can also select different circuit element targetedly, and for difference output signal, different sensitivity and protection requirement, to different voltage, bigoted and signal voltage etc., select suitable element, reach better protective effect.In the design of circuit board, this example does optimal design to multilayer board, comprise conductor layer, embedded conducting element, ground plane, insulating barrier and perforation, wherein conductor layer provides electric current to pass through, embedded conducting element is connected to conductor layer, and has the tip being enough to produce point discharge effect; Ground plane is made up of conductive material; and design all more complete than other layer; the conductive material area of plane exceeds other all layer; adjacent with tip; be used for receiving the most advanced and sophisticated electric charge that discharges and import mainly, and the grounding path of electrostatic protection module D1 being accomplished the shortest and Kongzui large, when connector cable suffers alien influence generation static discharge effect; utilize this structure to be imported mainly by electric current sharply, prevent IC or circuit from being destroyed and losing efficacy.
The embodiment of the above is better embodiment of the present utility model; not limit concrete practical range of the present utility model with this; scope of the present utility model comprises and is not limited to this embodiment, and the equivalence change that all shapes according to the utility model, structure are done is all in protection range of the present utility model.
Claims (8)
1. a mainboard anti-static protection circuit, is characterized in that, comprising: output interface, electrostatic protection module and IO chip; Two holding wires of described IO chip are connected with electrostatic protection module respectively by differential lines pair, described electrostatic protection module ground; Described IO chip is connected with described output interface by connector cable.
2. mainboard anti-static protection circuit according to claim 1, it is characterized in that, also comprise electric capacity C1, electric capacity C2, resistance R3 and resistance R4, a holding wire of described IO chip is connected with one end of resistance R3, the other end of described resistance R3 is connected with one end of described electric capacity C1, and the other end of described electric capacity C1 is connected with electrostatic protection module; Another root holding wire of described IO chip is connected with one end of resistance R4, and the other end of described resistance R4 is connected with one end of described electric capacity C2, and the other end of described electric capacity C2 is connected with electrostatic protection module.
3. mainboard anti-static protection circuit according to claim 2, it is characterized in that, also comprise resistance R1 and resistance R2, one end that described electric capacity C1 is connected with described electrostatic protection module is connected to one end of described resistance R1, and the other end of described resistance R1 is connected with output interface; One end that described electric capacity C2 is connected with described electrostatic protection module is connected to one end of described resistance R2, and the other end of described resistance R2 is connected with output interface.
4. the mainboard anti-static protection circuit according to claims 1 to 3 any one, is characterized in that, described electrostatic protection module comprises energy bleeder.
5. the mainboard anti-static protection circuit according to claims 1 to 3 any one, it is characterized in that, described electrostatic protection module comprises the first diode, the second diode, the 3rd diode, the 4th diode, the 5th diode, the 6th diode, the 7th diode and the 8th diode; The plus earth of described first diode, the negative electrode of described first diode is connected with the anode of described second diode, and the negative electrode of described second diode is connected with power supply; The plus earth of described 3rd diode, the negative electrode of described 3rd diode is connected with the anode of described 4th diode, and the negative electrode of described 4th diode is connected with power supply; The plus earth of described 5th diode, the negative electrode of described 5th diode is connected with the anode of described 6th diode, and the negative electrode of described 6th diode is connected with power supply; The plus earth of described 7th diode, the negative electrode of described 7th diode is connected with the anode of described 8th diode, and the negative electrode of described 8th diode is connected with power supply.
6. mainboard anti-static protection circuit according to claim 5, is characterized in that, a holding wire of described IO chip is connected with the anode of described 4th diode with the negative electrode of described 3rd diode respectively.
7. mainboard anti-static protection circuit according to claim 6, is characterized in that, another root holding wire of described IO chip is connected with the anode of described 6th diode with the negative electrode of described 5th diode respectively.
8. mainboard anti-static protection circuit according to claim 5, is characterized in that, described electrostatic protection module also comprises voltage stabilizing didoe, the plus earth of described voltage stabilizing didoe, and the negative electrode of described voltage stabilizing didoe is connected with power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520696624.1U CN205123240U (en) | 2015-09-09 | 2015-09-09 | Electrostatic protection circuit is prevented to mainboard |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520696624.1U CN205123240U (en) | 2015-09-09 | 2015-09-09 | Electrostatic protection circuit is prevented to mainboard |
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| Publication Number | Publication Date |
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| CN205123240U true CN205123240U (en) | 2016-03-30 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520696624.1U Active CN205123240U (en) | 2015-09-09 | 2015-09-09 | Electrostatic protection circuit is prevented to mainboard |
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| CN (1) | CN205123240U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018113346A1 (en) * | 2016-12-23 | 2018-06-28 | 华为技术有限公司 | Interface protection circuit and device interface |
| CN111600589A (en) * | 2020-05-09 | 2020-08-28 | 深圳市火乐科技发展有限公司 | Antistatic circuit and electronic device |
-
2015
- 2015-09-09 CN CN201520696624.1U patent/CN205123240U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2018113346A1 (en) * | 2016-12-23 | 2018-06-28 | 华为技术有限公司 | Interface protection circuit and device interface |
| CN108242802A (en) * | 2016-12-23 | 2018-07-03 | 华为技术有限公司 | Interface protection circuit and equipment interface |
| JP2019526223A (en) * | 2016-12-23 | 2019-09-12 | 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． | Interface protection circuit and device interface |
| US11509134B2 (en) | 2016-12-23 | 2022-11-22 | Huawei Technologies Co., Ltd. | Communication interface protection circuit having transient voltage suppression |
| CN111600589A (en) * | 2020-05-09 | 2020-08-28 | 深圳市火乐科技发展有限公司 | Antistatic circuit and electronic device |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20220614 Address after: 518000 1204, building 1, Shenzhen new generation industrial park, No. 136, Zhongkang Road, Meidu community, Meilin street, Futian District, Shenzhen, Guangdong Province Patentee after: Shenzhen Qicaihong Yugong Information Technology Development Co.,Ltd. Address before: 1206, floor 13, central business building, No. 88, Fuhua 1st Road, Futian District, Shenzhen, Guangdong 518057 Patentee before: COLORFUL TECHNOLOGY Co.,Ltd. |
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| TR01 | Transfer of patent right |