CN205029651U - S wave band sectional type multi -system chirp makes wireless communication system - Google Patents
S wave band sectional type multi -system chirp makes wireless communication system Download PDFInfo
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- CN205029651U CN205029651U CN201520807130.6U CN201520807130U CN205029651U CN 205029651 U CN205029651 U CN 205029651U CN 201520807130 U CN201520807130 U CN 201520807130U CN 205029651 U CN205029651 U CN 205029651U
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Abstract
The utility model relates to a S wave band sectional type multi -system chirp makes wireless communication system, including transmitter and receiver, the transmission signal that comes from the transmitter is received to the receiver, the transmitter includes FPGA, system clock, high -speed DDS unit, radio frequency local oscillator unit, first detector, power amplifier, antenna, the high -speed DDS unit of FPGA drive produces the chirp code signal, local oscillator signal that radio frequency local oscillator unit produced, and the chirp code signal carries out the mixing with the local oscillator signal through the first detector to be handled, and the mixing is handled and is moved the 2 -4GHz frequency channel with the frequency spectrum of chirp code signal, sends into power amplifier after the mixing is handled and amplifies, and the signal after amplifying is by the sky line emission, FPGA is according to user defined model data demand system encode and select the transmitted bandwidth and the frequency channel interval, the user defined model data include digital system, code bandwidth, code section gap and transmit frequency band, the system clock provides clock frequency for high -speed DDS unit and FPGA.
Description
Technical field
The utility model relates to a kind of S-band segmented multi-system chirp modulation wireless commnication and communication means thereof, belongs to communication technical field.
Background technology
Along with people to Large Copacity, at a high speed, the continuous growth of the demand of the radio communication of high security, high reliability, people have to find new technique on overcrowding and very limited wireless frequency spectrum.Chirp spread spectrum is the core technology of Chirp communication.1962, mentioned by Winkler, Chirp spread spectrum just starts to be applied to the communications field.But Winkler only proposed idea at that time, and do not provide complete system realization scheme for this idea.Until 1966, Hata finds that Chirp spread-spectrum signal has the characteristic to Doppler shift immunity, propose the system schema utilizing Chirp spread-spectrum signal to carry out transfer of data, but owing to also not producing the way of Chirp signal at that time preferably, so the program could not be put into effect.Until 1973, Bush proposes the method using surface acoustic wave (SurfaceAcousticWave is called for short SAW) device to produce Chirp signal first.Henceforth, the researchers of Chirp spread spectrum communication start to have employed this analog machine with low cost in a large number to produce Chirp signal.After 2000, Chirp spread spectrum is subject to increasing tissue and manufacturer pays close attention to.In March, 2005, through IEEE802.15TG4a (low rate WLAN standard working group) ballot, adopt unanimously the super-broadband tech based on Chirp as one of latter two alternative of IEEE802.15.4a physical layer standard.In March, 2007, in the formal IEEE802.15.4a physical layer standard that the IEEE committee announces, Chirp spread spectrum becomes one of possibility.
Modulator approach at present for Chirp ultra-wideband communications can be divided into two large classes, binary orthogonal keying (BinaryOrthogonalKeying, BOK) modulation and directly modulation (DirectModulation, DM).Two kinds of modulator approaches are completely different: in BOK, Chirp signal is used to indicate the symbol after modulation; And in DM, Chirp signal is only for expanding the frequency spectrum of modulated signal.
Utility model content
The purpose of this utility model is the deficiency that customer service prior art exists, thus provide one can realize data high-speed communication, strong interference immunity, with low cost, the S-band segmented multi-system chirp modulation wireless commnication of structural design advantages of simple and communication means thereof.
The technical scheme that the utility model adopts for achieving the above object is: this S-band segmented multi-system chirp modulation wireless commnication, comprises transmitter and receiver, and receiver receives transmitting from transmitter; Transmitter comprises FPGA, system clock, high-speed DDS unit, radio-frequency (RF) local oscillator unit, frequency mixer, power amplifier, antenna; FPGA drives high-speed DDS unit to produce chirp code signal, the local oscillation signal that radio-frequency (RF) local oscillator unit produces, chirp code signal and local oscillation signal carry out Frequency mixing processing through frequency mixer, Frequency mixing processing by the frequency spectrum shift of chirp code signal to 2-4GHz frequency range, send into power amplifier after Frequency mixing processing to amplify, the signal after amplification is by antenna transmission; FPGA, carries out encoding according to User Defined data demand system and selects transmitted bandwidth and frequency range interval; User Defined data comprise digital system, encoded bandwidth, encoded segment interval and transmit frequency band; System clock provides clock frequency to high-speed DDS unit and FPGA; Receiver comprises pre-low-noise amplifier, one-level band pass filter, one-level frequency mixer, one-level radio-frequency (RF) local oscillator, multichannel medium frequency reception unit and signal acquiring processing system; Pre-low-noise amplifier amplifies to the received signal, one-level band pass filter does filtering process to amplifying signal, the local oscillation signal that signal after filtering process and radio-frequency (RF) local oscillator produce is carried out mixing by one-level frequency mixer, and the signal of Frequency mixing processing is reduced to 10MHz-1GHZ frequency; Signal multi-system as required through Frequency mixing processing carries out selection and process along separate routes by multichannel medium frequency reception unit.
Described multichannel medium frequency reception unit comprise some roads intermediate frequency amplifying unit, wherein arbitrary road intermediate frequency amplifying unit is made up of secondary band pass filter, amplifier, secondary frequency mixer, intermediate frequency local oscillator unit, high-gain logarithmic amplifier; The passband of the secondary band pass filter of each intermediate frequency amplifying unit is different; The secondary band pass filter of different passband is split signal band, amplifier amplifies splitting signal, splitting signal through amplifying and the signal of intermediate frequency local oscillator unit do down conversion process through secondary frequency mixer, then are sent to signal acquiring processing system process through high-gain logarithmic amplifier; Signal acquiring processing system, adopts A/D conversion to carry out signals collecting, the signal after conversion is carried out demodulation, recovers the data that transmitter sends.
Multichannel medium frequency reception unit described in the utility model adopts modularized design.
The signal frequency that the intermediate frequency local oscillator unit of each intermediate frequency amplifying unit described in the utility model produces is different.
The radio-frequency (RF) local oscillator unit of transmitter described in the utility model adopts ADF4350 chip, and the frequency mixer of transmitter adopts MAC-85L+ mixing chip.The circuit of transmitter adopts ADF4350 as local oscillator, and coordinate MAC-85L+ mixing chip as up-converter circuit, have the advantages such as adjustment is simple, frequency stability is high, emission band wide ranges, user can adjust tranmitting frequency as required in 2-4GHz.
The pre-low-noise amplifier of receiver described in the utility model adopts CMA-545+ chip, band pass filter, frequency mixer to adopt MAC-85L+ mixing chip, radio-frequency (RF) local oscillator employing ADF4350 chip.The radio frequency part of receiver adopts CMA-545+ ultra-wideband low-noise amplifier, and radio-frequency (RF) local oscillator adopts ADF4350 as local oscillator, coordinates MAC-85L+ mixing chip as lower frequency changer circuit, has frequency acceptance band wide, the advantages such as noise factor is low.
Amplifier described in the utility model adopts wide-band amplifier MAR-8A+ chip, and amplifier amplifies as pre-IF, and coordinate high-gain logarithmic amplifier to adopt AD8306 chip, high-gain logarithmic amplifier amplifies as rear class.Adopt wide-band amplifier MAR-8A+ to amplify as pre-IF, coordinate AD8306 to amplify as rear class, can output amplitude be limited, automatically adjust gain, and index signal intensity simultaneously, avoid rear class sample circuit and produce distortion because of saturated.
The means of communication of S-band segmented multi-system chirp modulation wireless commnication described in the utility model, transmitter is before transmission data, FPGA first drives high-speed DDS unit to produce the single-point frequency sine-wave preset, then launch with impulse form, with pulsewidth finish time for timing node, postpone set time transmission data, after receiver receives the single-point frequency sine-wave signal of default pulsewidth, same with pulsewidth finish time for timing node, postpone the enabling signal process of same time interval, settling signal is synchronous.
When sending data, FPGA according to the digital system preset, encoded bandwidth, encoded segment interval and transmit frequency band, and drives high-speed DDS unit data transaction to be become the chirp code signal of segmentation, then through mixing, amplifies, sends into antenna transmission.
Receiver receives the signal from transmitter, and signal is sent into pre-low-noise amplifier amplify, then filtering, again by one-level frequency mixer by local oscillation signal and Received signal strength mixing, signal frequency is reduced, subsequently by Received signal strength simultaneously by the secondary band pass filter of different passband, thus a road signal is divided into multiple passage, signal and intermediate frequency local oscillator are again through the mixing of secondary frequency mixer in each channel, signal is reduced to baseband signal, digital signal is become by the collection of A/D data transaction, then through fraction Fourier conversion, by data demodulates out.
The advantage that the utility model is had compared to existing technology:
1, the utility model adopts multi-system segmented chirp signal to encode to initial data, and compared to traditional PSK, ASK, FSK, emitted energy is evenly distributed in each frequency range by the utility model, and its anti-interference performance is frequently strengthened.
2, FPGA described in the utility model adopts the Spartan6XC6SLX9-2TQG144I parallel DDS of promotion chip AD9914 to produce segmentation chirp signal, FPGA is according to the digital system preset, encoded bandwidth, encoded segment interval and transmit frequency band, high-speed DDS unit is driven data transaction to be become segmentation chirp signal, there is fm linearity good, frequency inverted speed advantages of higher.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of transmitter described in the utility model.
Fig. 2 is the circuit diagram that high-speed DDS unit described in the utility model is connected with FPGA.
Fig. 3 is the circuit diagram of radio-frequency (RF) local oscillator unit in transmitter described in the utility model.
Fig. 4 is the circuit diagram of system clock in transmitter described in the utility model.
Fig. 5 is the circuit diagram of receiver described in the utility model.
Fig. 6 is the circuit diagram of one-level radio-frequency (RF) local oscillator in receiver described in the utility model.
Fig. 7 is the circuit diagram of intermediate frequency amplifying unit in receiver described in the utility model.
Embodiment
Below in conjunction with accompanying drawing, also by embodiment, the utility model is described in further detail, and following examples are that the utility model is not limited to following examples to explanation of the present utility model.
As Fig. 1, Fig. 5, S-band segmented multi-system chirp modulation wireless commnication described in the utility model, comprises transmitter and receiver, and receiver receives transmitting from transmitter; Transmitter comprises FPGA, system clock, high-speed DDS unit, radio-frequency (RF) local oscillator unit, frequency mixer, power amplifier, antenna; FPGA drives high-speed DDS unit to produce chirp code signal, the local oscillation signal that radio-frequency (RF) local oscillator unit produces, chirp code signal and local oscillation signal carry out Frequency mixing processing through frequency mixer, Frequency mixing processing by the frequency spectrum shift of chirp code signal to 2-4GHz frequency range, send into power amplifier after Frequency mixing processing to amplify, the signal after amplification is by antenna transmission; FPGA, carries out encoding according to User Defined data demand system and selects transmitted bandwidth and frequency range interval; User Defined data comprise digital system, encoded bandwidth, encoded segment interval and transmit frequency band; System clock provides clock frequency to high-speed DDS unit and FPGA; Receiver comprises pre-low-noise amplifier, one-level band pass filter, one-level frequency mixer, one-level radio-frequency (RF) local oscillator, multichannel medium frequency reception unit and signal acquiring processing system composition; Pre-low-noise amplifier amplifies to the received signal, one-level band pass filter does filtering process to amplifying signal, the local oscillation signal that signal after filtering process and radio-frequency (RF) local oscillator produce is carried out mixing by one-level frequency mixer, and the signal of Frequency mixing processing is reduced to 10MHz-1GHZ frequency; Signal multi-system as required through Frequency mixing processing carries out selection and process along separate routes by multichannel medium frequency reception unit.
Described multichannel medium frequency reception unit comprise some roads intermediate frequency amplifying unit, wherein arbitrary road intermediate frequency amplifying unit is made up of secondary band pass filter, amplifier, secondary frequency mixer, intermediate frequency local oscillator unit, high-gain logarithmic amplifier; The passband of the secondary band pass filter of each intermediate frequency amplifying unit is different; The secondary band pass filter of different passband is split signal band, amplifier amplifies splitting signal, splitting signal through amplifying and the signal of intermediate frequency local oscillator unit do down conversion process through secondary frequency mixer, then are sent to signal acquiring processing system process through high-gain logarithmic amplifier; Signal acquiring processing system, adopts A/D conversion to carry out signals collecting, the signal after conversion is carried out demodulation, recovers the data that transmitter sends.
Multichannel medium frequency reception unit described in the utility model adopts modularized design.
The signal frequency that the intermediate frequency local oscillator unit of each intermediate frequency amplifying unit described in the utility model produces is different.
The radio-frequency (RF) local oscillator unit of transmitter described in the utility model adopts ADF4350 chip, and the frequency mixer of transmitter adopts MAC-85L+ mixing chip.The circuit of transmitter adopts ADF4350 as local oscillator, and coordinate MAC-85L+ mixing chip as up-converter circuit, have the advantages such as adjustment is simple, frequency stability is high, emission band wide ranges, user can adjust tranmitting frequency as required in 2-4GHz.
The pre-low-noise amplifier of receiver described in the utility model adopts CMA-545+ chip, band pass filter, frequency mixer to adopt MAC-85L+ mixing chip, radio-frequency (RF) local oscillator employing ADF4350 chip.The radio frequency part of receiver adopts CMA-545+ ultra-wideband low-noise amplifier, and radio-frequency (RF) local oscillator adopts ADF4350 as local oscillator, coordinates MAC-85L+ mixing chip as lower frequency changer circuit, has frequency acceptance band wide, the advantages such as noise factor is low.
Amplifier described in the utility model adopts wide-band amplifier MAR-8A+ chip, and amplifier amplifies as pre-IF, and coordinate high-gain logarithmic amplifier to adopt AD8306 chip, high-gain logarithmic amplifier amplifies as rear class.Adopt wide-band amplifier MAR-8A+ to amplify as pre-IF, coordinate AD8306 to amplify as rear class, can output amplitude be limited, automatically adjust gain, and index signal intensity simultaneously, avoid rear class sample circuit and produce distortion because of saturated.
The means of communication of S-band segmented multi-system chirp modulation wireless commnication described in the utility model, transmitter is before transmission data, FPGA first drives high-speed DDS unit to produce the single-point frequency sine-wave preset, then launch with impulse form, with pulsewidth finish time for timing node, postpone set time transmission data, after receiver receives the single-point frequency sine-wave signal of default pulsewidth, same with pulsewidth finish time for timing node, postpone the enabling signal process of same time interval, settling signal is synchronous.
When sending data, FPGA according to the digital system preset, encoded bandwidth, encoded segment interval and transmit frequency band, and drives high-speed DDS unit data transaction to be become the chirp code signal of segmentation, then through mixing, amplifies, sends into antenna transmission.
Receiver receives the signal from transmitter, and signal is sent into pre-low-noise amplifier amplify, then filtering, again by one-level frequency mixer by local oscillation signal and Received signal strength mixing, signal frequency is reduced, subsequently by Received signal strength simultaneously by the secondary band pass filter of different passband, thus a road signal is divided into multiple passage, signal and intermediate frequency local oscillator are again through the mixing of secondary frequency mixer in each channel, signal is reduced to baseband signal, digital signal is become by the collection of A/D data transaction, then through fraction Fourier conversion, by data demodulates out.
As shown in Figure 2, high-speed DDS unit adopts the AD9914 chip of AD company, D18 meets IO_L1P_3, D17 meets IO_L1N_VREF_3, D16 meets IO_L2P_3, D15 meets IO_L2N_3, D14 meets IO_L36P_3, D13 meets IO_L36N_3, D12 meets IO_L37P_3, D11 meets IO_L37N_3, D10 meets IO_L41P_GCLK27_3, D9 meets IO_L41N_GCLK26_3, D8 meets IO_L42P_GCLK25_TRDY2_3, D7 meets IO_L42N_GCLK24_3, D6 meets IO_L43P_GCLK23_3, D5 meets IO_L43N_GCLK22_IRDY2_3, D4 meets IO_L44P_GCLK21_3, D3 meets IO_L44N_GCLK20_3, D2 meets IO_L49P_3, D1 meets IO_L49N_3, D0 meets IO_L50P_3, PS0 meets IO_L50N_3, PS1 meets IO_L51P_3, PS2 meets IO_L51N_3, F0 meets IO_L52P_3, F1 meets IO_L52N_3, F2 meets IO_L83P_3, F3 meets IO_L83N_VREF_3, PWN meets IO_L12P_D1_MISO2_2, D31 meets IO_L12N_D2_MISO3_2, D30 meets IO_L13N_D10_2, D29 meets IO_L14P_D11_2, D28 meets IO_L14N_D12_2, D27 meets IO_L30P_GCLK1_D13_2, D26 meets IO_L30N_GCLK0_USERCCLK_2, D25 meets IO_L31P_GCLK31_D14_2, D24 meets IO_L31N_GCLK30_D15_2, D23 meets IO_L48P_D7_2, D22 meets IO_L48N_RDWR_B_VREF_2, D21 meets IO_L49P_D3_2, D20 meets IO_L49N_D4_2, SYNC_CLK meets IO_L62P_D5_2, REST meets IO_L62N_D6_2, I/O_UPDATE meets IO_L64P_D8_2, D19 meets IO_L64N_D9_2, DROVER meets IO_L74P_AWAKE_1, OSK meets IO_L74N_DOUT_BUSY_1, SYNC_OUT meets IO_L46P_1, SYNC_IN meets IO_L46N_1, DRCTL meets IO_L47P_1, DRHOLD meets IO_L47N_1, 6th pin DVDD (1.8V) meets electric capacity C48 and is connected with digital power system 1.8V, another termination of C48 digitally, 16th pin DVDD_I/O meets electric capacity C61 and is connected with digital power system 1.8V, another termination of C61 digitally, 23rd pin DVDD (1.8V) meets electric capacity C68 and is connected with digital power system 1.8V, another termination of C68 digitally, 73rd pin DVDD (1.8V) meets electric capacity C19 and is connected with digital power system 1.8V, another termination of C19 digitally, 83rd pin DVDD (3.3V) meets electric capacity C20 and is connected with digital power system 3.3V, another termination of C20 digitally, 32nd pin AVDD (1.8V) meets electric capacity C70 and is connected with the simulation 1.8V that powers, another termination of C70 in analog, 34th pin AVDD (3.3V) meets electric capacity C71 and is connected with the simulation 3.3V that powers, another termination of C71 in analog, 39th pin AVDD (3.3V) is connected with the 40th pin AVDD (3.3V) and meets electric capacity C73 again and be connected with the simulation 3.3V that powers, another termination of C73 in analog, 43rd pin AVDD (3.3V) meets electric capacity C75 and is connected with the simulation 3.3V that powers, another termination of C75 in analog, 47th pin AVDD (3.3V) meets electric capacity C62 and is connected with the simulation 3.3V that powers, another termination of C62 in analog, 50th pin AVDD (3.3V) meets electric capacity C60 and is connected with the simulation 3.3V that powers, another termination of C60 in analog, 52nd pin AVDD (3.3V) is connected with the 53rd pin AVDD (3.3V) and meets electric capacity C59 again and be connected with the simulation 3.3V that powers, another termination of C59 in analog, 56th pin AVDD (1.8V) is connected with the 57th pin AVDD (1.8V) and meets electric capacity C56 again and be connected with the simulation 1.8V that powers, another termination of C56 in analog, 60th pin AVDD (3.3V) meets electric capacity C47 and is connected with the simulation 3.3V that powers, another termination of C47 in analog, 7th pin DGND connects digitally, 17th pin DGND connects digitally, 24th pin DGND connects digitally, 74th pin DGND connects digitally, 84th pin DGND connects digitally, 33rd pin GND connects in analog, 35th pin GND connects in analog, 37th pin GND connects in analog, 38th pin GND connects in analog, 44th pin GND connects in analog, 46th pin GND connects in analog, 49th pin GND connects in analog, 51st pin GND connects in analog, 45th pin DAC_BP is connected with electric capacity C66 with C67, another termination of C66 and C67 in analog, 48th pin DAC_RSET and R13 is connected, another termination of R13 in analog, 41st pin is connected with R16 with C77, another termination of R16 simulation power supply 3.3V, the C77 other end is connected with the 4th pin of * 6 coupling transformer TC1-1-13M+ chips.42nd pin AOUT and R17 is connected with C78, and another termination of R17 simulation power supply 3.3V, the C78 other end is connected with the 6th pin of * 6 coupling transformer TC1-1-13M+ chips.* 1st pin of 6 coupling transformer TC1-1-13M+ exports as DDS, be connected with the 3rd pin IF of frequency mixer * 10 (MAC-85L+), and * 6 coupling transformers the 2nd pin and the 3rd pin link together and connect in analog.54th pin is connected with C58, and the C58 other end is connected with the 1st pin of R12 one end with * 3 coupling transformer TC1-1-13M+ chips.55th pin REFCLK and C57 is connected, and the C57 other end is connected with the 3rd pin of the R12 other end with * 3 coupling transformer TC1-1-13M+ chips.* 6th pin of 3 coupling transformer TC1-1-13M+ is connected with system clock 2, * 3 coupling transformers the 2nd pin and the 4th pin link together and connect in analog.58th pin LOOP_FILTER and R11 is connected with C46, and the R11 other end is connected with C45, and the 59th pin REF is connected with the C45 other end, the C46 other end C42, C43.The C42 other end and the C43 other end are connected together in analog.
At work, FPGA carries out encoding according to the data demand system that user interface provides and selects transmitted bandwidth and frequency range interval, then parallel drive high-speed DDS unit, produces chirp code signal.For 4 scale codings, if swept bandwidth is 50MHz, encoded segment interval 200MHz, when start code frequency is 300MHz, coding method is, when driving DDS produces 300-350MHz positive slope chirp signal interval scale data 00, negative slope chirp signal 350-300MHz representative data 01, positive slope chirp signal 500-550MHz representative data 10, negative slope chirp signal 550-500MHz representative data 11.User can self-defined digital system, encoded bandwidth, encoded segment interval and transmit frequency band according to actual needs.
As shown in Figure 3, radio-frequency (RF) local oscillator unit adopts the ADF4350 chip of AD company, CLK meets IO_L3N_0, DATA meets IO_L4P_0, LE meets IO_L4N_0, LD meets IO_L34P_GCLK19_0, MUXOUT meets IO_L34N_GCLK18_0, CE meets digital power system 3.3V, Vp meets simulation power supply 3.3V, CPOUT and C82, C81, R21 is connected, another termination of C82 in analog, another termination R23 of C81, another termination of R23 in analog, the R21 other end is connected with pin VTUNE with C80, another termination of C80 in analog, CPGND connects in analog, AGND connects in analog, AVDD meets simulation power supply 3.3V, AGNDVCO connects in analog, 16 pin VVCO meet simulation power supply 3.3V, 17 pin VVCO meet simulation power supply 3.3V, AGND connects in analog, TEMP meets C83, another termination of C83 in analog, AGNDVCO connects in analog, RSET meets R22, another termination of R22 in analog, VCOM meets C84, another termination of C84 in analog, VREF meets C85, another termination of C85 in analog, PDREF meets digital power system 3.3V, DGND connects digitally, DVDD meets digital power system 3.3V, REFIN welding system signal clock input 3, SDGND connects digitally, SDVDD meets digital power system 3.3V, RFOUTA+ meets the 10th pin LO that L11 meets mixing unit * 10 (MAC-85L+) simultaneously, another termination of L11 simulation power supply 3.3V.
Frequency mixer adopts MAC-85L+ chip, its 1,2,4,6,7,8, and 9 pin are connected together in analog, and 3 pin IF connect high-speed DDS cell signal and export, and 10 pin LO connect local oscillator unit and export, and 5 pin RF export as mixing unit and connect power amplifier input.
Power Amplifier Unit adopts LEE-39+ chip, its 1 pin meets C86, another termination mixing unit of C86 exports, its 2 pin, 4 pin connect in analog, and 3 pin meet C87 and L12, the C87 other end exports as power amplifier and connects antenna, the L12 other end is connected with C88 with R30, and C88 other end connecting analog ground, R30 other end connecting analog is powered+5V.
At work, the local oscillation signal that the chirp code signal driving high-speed DDS unit to produce via FPGA and ADF4350 produce carries out mixing, by the frequency spectrum shift of code signal to the frequency range be applicable to, then send into power amplifier and amplify, the signal after amplification sends via transmitting antenna.Launching frequency drives ADF4350 to control by FPGA, can at 2GHz-4GHz by User Defined.
As shown in Figure 4, system clock, comprises constant-temperature crystal oscillator and peripheral circuit thereof and two constant power two power splitters.Constant-temperature crystal oscillator 1 pin is connected with C64 with L5, the C64 other end connects digitally, the L5 other end and C63 with simulate+the 5V that powers and be connected, C63 other end connecting analog ground, constant-temperature crystal oscillator 2 pin is connected with R14, the R14 other end is connected with constant-temperature crystal oscillator 3 pin with R15, constant-temperature crystal oscillator 4 pin connects in analog, 5 pin connect 1 pin of * 4 (power splitter chip ADP-2-1W+) as exporting, * 3 pin of 4 connect C69, the 84 pin IO_L43N_GCLK4_1 that the other end of C69 connects FPGA input as the clock of FPGA, * 6 pin of 4 connect in analog, 4 pin connect 1 pin of * 8 (power splitter chip ADP-2-1W+), * 3 pin of 8 connect electric capacity C65, the C65 other end connects 6 pin of DDS element coupling transformer * 3, as input end of clock, * 4 pin of 8 connect electric capacity C72, the C72 other end connects the REFIN pin of local oscillator ADF4350, as input end of clock, * 6 pin of 8 connect in analog.
Receiver unit of the present utility model as shown in Figure 5, data acquisition and treatment system thereof adopt the FPGA of current comparative maturity to add multi-channel a/d converter scheme.
Fig. 6 shows receiver radio frequency element circuit of the present utility model, pre-low-noise amplifier adopts CMA-545+, 1 pin, 3 pin, 5 pin, 6 pin are connected with 8 pin and connect in analog, 2 pin meet C101 and are connected with L101, another termination reception antenna of C101, 4 pin connect the L101 other end and are connected with R101, another termination of R101 simulation power supply 3.3V is also connected with C103 with L102, another termination of C103 in analog, 7 pin connect the L102 other end and are connected with C102, the IN pin of another termination radio frequency band filter of C102 * 12, * the GND pin of 12 be connected in analog, * the OUT pin of 12 is connected with the RF pin of mixing unit * 13 (MAC-85L+).
The radio-frequency (RF) local oscillator unit of receiver adopts the ADF4350 chip of AD company equally, CLK, DATA, LE, LD, 5 pins such as MUXOUT connect the data handling system of receiver, CE meets digital power system 3.3V, Vp meets simulation power supply 3.3V, CPOUT and C112, C111, R104 is connected, another termination of C112 in analog, another termination R105 of C111, another termination of R105 in analog, the R104 other end is connected with pin VTUNE with C110, another termination of C110 in analog, CPGND connects in analog, AGND connects in analog, AVDD meets simulation power supply 3.3V, AGNDVCO connects in analog, 16 pin VVCO meet simulation power supply 3.3V, 17 pin VVCO meet simulation power supply 3.3V, AGND connects in analog, TEMP meets C109, another termination of C109 in analog, AGNDVCO connects in analog, RSET meets R103, another termination of R103 in analog, VCOM meets C106, another termination of C106 in analog, VREF meets C105, another termination of C105 in analog, PDREF meets digital power system 3.3V, DGND connects digitally, DVDD meets digital power system 3.3V, REFIN welding system signal clock input 3, SDGND connects digitally, SDVDD meets digital power system 3.3V, RFOUTA+ connects the LO pin that L104 meets mixing unit * 13 simultaneously, another termination of L104 simulation power supply 3.3V.
After the signal received is amplified by pre-low-noise amplifier, filtering is carried out through one-level band pass filter, remove the noise of other frequency range, then signal is sent into the local oscillation signal that frequency mixer and ADF4350 produce and carry out mixing, signal is reduced to a lower frequency.
The intermediate frequency amplifying unit multi-system as required of receiver carries out shunt process, intermediate frequency amplifying unit adopts modularized design, with different system transmission data, the intermediate frequency amplifying unit number needed is also different, but the design circuit structure on every road is identical, just the frequency of front end filter is different with intermediate frequency local oscillator frequency setting, and the design on an intermediate-frequency circuit wherein road is described below.
Shown in Fig. 7, receiver of the present utility model is a road intermediate frequency amplifying unit circuit wherein, the IF pin of the in termination radio frequency unit frequency mixer * 13 of an if bandpas filter * 18, GND termination in analog, out termination C107, the C107 other end is connected with the RFIN of amplifier * 15 (MAR-8+), * 15 2, 4 pin are connected and connect in analog, 3 pin meet C108 and L103, the L103 other end is connected with C104 with R102, another termination of C104 in analog, another termination of R102 simulation power supply+5V, the C108 other end is connected with the RF pin of frequency mixer * 16 (ADE-5+), 1 of frequency mixer * 16, 4, 5 pin are connected and connect in analog, 2 pin connect the input of low pass filter * 19, 6 pin connect the output of intermediate frequency local oscillator unit * 20.The GND pin of low pass filter * 19 connects in analog, and output pin OUT meets C118.
Intermediate frequency local oscillator unit adopts SI550, its 1 pin, 2 pin and C123 with simulate the 3.3V that powers and be connected, another termination of C123 is in analog, 3 pin connect digitally, 6 pin meet simulation power supply 3.3V and are connected with C122, and in analog, 5 pin export as local oscillator and are connected with 6 pin of * 16 another termination of C122.
High-gain logarithmic amplifier adopts AD8306, its 1, 3, 6, 7, 11, 14 pin link together and are connected in analog, 2 pin are connected with 8 pin and meet C116 and R109, C116 other end ground connection, another termination of R109 simulation power supply+5V, 4 pin connect R113 and the C118 other end, 5 pin meet the R113 other end and C120, another termination R115 of C120, another termination of R115 in analog, 9 pin meet R116, another termination of R116 in analog, 10 pin meet C117, 12 pin meet R111, L106 and C121, another termination R114 of C121, another termination R117 of R114, another termination of R117 in analog, 13 pin connect the L106 other end and are connected with R110 with C119, another termination R112 of C119, the R112 other end is as the final output of ifd module, send into signal processing system, 15 pin meet the R110 other end and C115, R108 is also connected with the R111 other end, another termination of C115 in analog, another termination of R108 simulation power supply+5V, 16 pin connect the C117 other end and are connected with R107, the R110 other end is connected with R106 and sends into signal processing system as signal strength signal intensity indication output end, the R106 other end be connected in analog.
The frequency partition of band pass filter mainly sees the encoded frequency range that user oneself customizes, and such as quaternary coding, is respectively 00,01,10,11 4 kinds of states, need two segmentations, then just with the band pass filter that two frequencies are different, the coding of transmitter, such as: frequency modulation 100-130MHz, upper frequency sweep represents 00, and lower frequency sweep represents 01, frequency modulation 200-230MHz, upper frequency sweep represents 10, and lower frequency sweep represents 11, then the frequency of two band pass filters is 100-130MHz and 200-230MHz.Due to foregoing band pass filter to the received signal frequency range carried out dividing processing, at this moment signal frequency does not become, still higher, now cannot with A/D to signal Direct Sampling, need to carry out down-converted with frequency mixer to signal, signal is moved lower frequency, be applicable to A/D sampling, the function of two mixing is the same, but due to the difference of segmentation, the local oscillator of frequency mixer is signal is different, such as the frequency range of two band pass filters is respectively above: 400-500MHz, 600-800MHz, the signal frequency of this two-way is different, the frequency mixer local oscillation signal of the first via can select 380MHz, the frequency mixer local oscillation signal on the second tunnel can select 580MHz, the signal first via after such mixing is 20-120MHz, second tunnel is 20-120MHz, frequency is lower, be applicable to follow-up A/D sampling setting different.
Claims (6)
1.S wave band segmented multi-system chirp modulation wireless commnication, is characterized in that:
Comprise transmitter and receiver, receiver receives transmitting from transmitter;
Transmitter comprises FPGA, system clock, high-speed DDS unit, radio-frequency (RF) local oscillator unit, frequency mixer, power amplifier, antenna;
FPGA drives high-speed DDS unit to produce chirp code signal, the local oscillation signal that radio-frequency (RF) local oscillator unit produces, chirp code signal and local oscillation signal carry out Frequency mixing processing through frequency mixer, Frequency mixing processing by the frequency spectrum shift of chirp code signal to 2-4GHz frequency range, send into power amplifier after Frequency mixing processing to amplify, the signal after amplification is by antenna transmission;
FPGA, carries out encoding according to User Defined data demand system and selects transmitted bandwidth and frequency range interval; User Defined data comprise digital system, encoded bandwidth, encoded segment interval and transmit frequency band;
System clock provides clock frequency to high-speed DDS unit and FPGA;
Receiver comprises pre-low-noise amplifier, one-level band pass filter, one-level frequency mixer, one-level radio-frequency (RF) local oscillator, multichannel medium frequency reception unit and signal acquiring processing system;
Pre-low-noise amplifier amplifies to the received signal, one-level band pass filter does filtering process to amplifying signal, the local oscillation signal that signal after filtering process and radio-frequency (RF) local oscillator produce is carried out mixing by one-level frequency mixer, and the signal of Frequency mixing processing is reduced to 10MHz-1GHZ frequency; Signal multi-system as required through Frequency mixing processing carries out selection and process along separate routes by multichannel medium frequency reception unit;
Described multichannel medium frequency reception unit comprise some roads intermediate frequency amplifying unit, wherein arbitrary road intermediate frequency amplifying unit is made up of secondary band pass filter, amplifier, secondary frequency mixer, intermediate frequency local oscillator unit, high-gain logarithmic amplifier; The passband of the secondary band pass filter of each intermediate frequency amplifying unit is different; The secondary band pass filter of different passband is split signal band, amplifier amplifies splitting signal, splitting signal through amplifying and the signal of intermediate frequency local oscillator unit do down conversion process through secondary frequency mixer, then are sent to signal acquiring processing system process through high-gain logarithmic amplifier; Signal acquiring processing system, adopts A/D conversion to carry out signals collecting, the signal after conversion is carried out demodulation, recovers the data that transmitter sends.
2. S-band segmented multi-system chirp modulation wireless commnication as claimed in claim 1, is characterized in that: described multichannel medium frequency reception unit adopts modularized design.
3. S-band segmented multi-system chirp modulation wireless commnication as claimed in claim 1, is characterized in that: the signal frequency that the intermediate frequency local oscillator unit of described each intermediate frequency amplifying unit produces is different.
4. S-band segmented multi-system chirp modulation wireless commnication as claimed in claim 1, is characterized in that: the radio-frequency (RF) local oscillator unit of described transmitter adopts ADF4350 chip, and the frequency mixer of transmitter adopts MAC-85L+ mixing chip.
5. S-band segmented multi-system chirp modulation wireless commnication as claimed in claim 1, is characterized in that: the pre-low-noise amplifier of described receiver adopts CMA-545+ chip, band pass filter, frequency mixer to adopt MAC-85L+ mixing chip, radio-frequency (RF) local oscillator employing ADF4350 chip.
6. S-band segmented multi-system chirp modulation wireless commnication as claimed in claim 1, its feature has: described amplifier adopts wide-band amplifier MAR-8A+ chip, amplifier amplifies as pre-IF, coordinate high-gain logarithmic amplifier to adopt AD8306 chip, high-gain logarithmic amplifier amplifies as rear class.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105656494A (en) * | 2015-10-19 | 2016-06-08 | 嘉兴国电通新能源科技有限公司 | S waveband segment-based multi-ary chirp modulated wireless communication system and communication method thereof |
| CN108536070A (en) * | 2018-05-16 | 2018-09-14 | 武汉纳谷微源物联科技有限公司 | A kind of shelf depreciation and temperature detection integral intelligent instrument |
| US10938440B2 (en) | 2018-05-17 | 2021-03-02 | Cisco Systems Canada Co. | Efficient methods for generating chirp spread spectrum signals |
-
2015
- 2015-10-19 CN CN201520807130.6U patent/CN205029651U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105656494A (en) * | 2015-10-19 | 2016-06-08 | 嘉兴国电通新能源科技有限公司 | S waveband segment-based multi-ary chirp modulated wireless communication system and communication method thereof |
| CN105656494B (en) * | 2015-10-19 | 2018-03-09 | 嘉兴国电通新能源科技有限公司 | S-band segmented multi-system chirp modulation wireless commnications and its communication means |
| CN108536070A (en) * | 2018-05-16 | 2018-09-14 | 武汉纳谷微源物联科技有限公司 | A kind of shelf depreciation and temperature detection integral intelligent instrument |
| US10938440B2 (en) | 2018-05-17 | 2021-03-02 | Cisco Systems Canada Co. | Efficient methods for generating chirp spread spectrum signals |
| US11362700B2 (en) | 2018-05-17 | 2022-06-14 | Cisco Systems Canada Co. | Efficient methods for generating chirp spread spectrum signals |
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