CN205028663U - Solid state hard drives with erase safely with wrong protect function - Google Patents
Solid state hard drives with erase safely with wrong protect function Download PDFInfo
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- CN205028663U CN205028663U CN201520754541.3U CN201520754541U CN205028663U CN 205028663 U CN205028663 U CN 205028663U CN 201520754541 U CN201520754541 U CN 201520754541U CN 205028663 U CN205028663 U CN 205028663U
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Abstract
The utility model relates to a solid state hard drives especially relates to a solid state hard drives with erase safely with wrong protect function. Its hardware button that includes power module, main control chip, GPIO interface, two DRAM chips, NAND flash memory array and produce level signal, power module connects with main control chip, a DRAM chip, the 2nd DRAM chip, NAND flash memory array respectively, and main control chip connects with a DRAM chip, the 2nd DRAM chip, NAND flash memory array respectively, and main control chip still connects through GPIO interface and hardware button. This solid state hard drives not only can erase the data among the solid state hard drives safely, but also can prevent that wrong data from writing in solid state hard drives into.
Description
Technical field
The utility model relates to solid state hard disc, relates to a kind of solid state hard disc with secure erase and error protection function in particular.
Background technology
Solid state hard disc becomes the memory device that people generally use day by day, and it is fast that it has speed, and the life-span is long, the advantage that power is low, solid state hard disc is that its volume is little, and memory space is large by high-capacity flash memory by dress in the circuit board, easy to use, and Portable computer assembling, thus obtain the welcome of user.In real operation, main control chip, while deletion solid state hard disc physical layer link table data, often also can be deleted some user data, cause user data by unreasonable deletion.And when toward solid state hard disc write data, often also can, the data of some mistakes write solid state hard disc, cause the space utilisation of solid state hard disc not high.
Utility model content
The utility model is in order to overcome the deficiencies in the prior art; object aims to provide a kind of solid state hard disc with secure erase and error protection function; this solid state hard disc not only can data safely in erasing solid state disk, but also can prevent the data write solid state hard disc of mistake.
In order to solve above-mentioned technical matters, the basic technical scheme that the utility model proposes is:
There is a solid state hard disc for secure erase and error protection function, it hardware button comprising power module, main control chip, GPIO interface, two dram chips, nand flash memory array and produce level signal; Described power module is connected with main control chip, the first dram chip, the second dram chip, nand flash memory array respectively, main control chip respectively with the first dram chip, the second dram chip, nand flash memory array are connected, and main control chip is also connected with hardware button by GPIO interface.
Further, described power module comprises four power supply chips, nand flash memory array has flash memory input and output power interface and flash memory storage power interface, first power supply chip produces the first voltage and the first voltage is inputted the first dram chip and the second dram chip respectively, second source chip produces the second voltage and the second voltage is inputted main control chip, 3rd power supply chip produces tertiary voltage and tertiary voltage is inputted nand flash memory array by flash memory storage power interface, 4th power supply chip produces the 4th voltage and the 4th voltage is inputted nand flash memory array by flash memory input and output power interface.
Further, described first voltage is 1.5V, and the second voltage is 1.2V, and tertiary voltage is 1.8V, and the 4th voltage is 3.3V.
The beneficial effects of the utility model are:
1, hardware button is by GPIO interface toward the pulse of main control chip incoming level, and main control chip is by the action of the triggering generation secure erase nand flash memory array of level pulse signal.Therefore user carries out secure erase by hardware button to nand flash memory array.
2, the utility model is provided with two dram chips, avoids adopting single DRAM and main control chip circuit design and causes the data writing NAND to occur the situation of mistake, and main control chip is more reliable and high efficiency writes correct data to NAND.
Accompanying drawing explanation
A kind of solid state hard disc electrical block diagram with secure erase and error protection function that Fig. 1 provides for the present embodiment.
Fig. 2 is the treatment scheme of the present embodiment solid state hard disk secure erasing.
Fig. 3 is the treatment scheme of the present embodiment solid state hard disc error in data protection.
Embodiment
Be described further below with reference to accompanying drawing 1 to 3 pair of the utility model, but protection domain of the present utility model should do not limited with this.For convenience of description and understand the technical solution of the utility model, below illustrate that the orientation that the noun of locality used all is shown with accompanying drawing is as the criterion.
As shown in Figure 1, a kind of solid state hard disc with secure erase and error protection function that the present embodiment provides comprises power module, main control chip, GPIO interface, two dram chips, nand flash memory array and produces the hardware button of level signal.Power module is connected with main control chip, the first dram chip, the second dram chip, nand flash memory array respectively, main control chip respectively with the first dram chip, the second dram chip, nand flash memory array are connected, and main control chip is also connected with hardware button by GPIO interface.
Preferably, the power module of the present embodiment comprises four power supply chips, nand flash memory array has flash memory input and output power interface and flash memory storage power interface, first power supply chip produces the first voltage and the first voltage is inputted the first dram chip and the second dram chip respectively, second source chip produces the second voltage and the second voltage is inputted main control chip, 3rd power supply chip produces tertiary voltage and tertiary voltage is inputted nand flash memory array by flash memory storage power interface, 4th power supply chip produces the 4th voltage and the 4th voltage is inputted nand flash memory array by flash memory input and output power interface.Wherein, the first voltage is 1.5V, and the second voltage is 1.2V, and tertiary voltage is 1.8V, and the 4th voltage is 3.3V.
As shown in Figure 2, the treatment scheme of solid state hard disk secure erasing is as described below: hardware button passes through GPIO interface toward the pulse of main control chip incoming level, main control chip is by the action of the triggering generation secure erase nand flash memory array of level pulse signal, wherein, level pulse signal can be that high level is effective, also can be Low level effective, choose one or the other of these two.On the one hand, the physical logic link table in main control chip erasing nand flash memory array, on the other hand, main control chip also wipes the data of user area.Certainly, main control chip not only can secure erase nand flash memory array, and the utility model also makes main control chip carry out fast erase or senior erasing by the level pulse signal input of external hardware button.Therefore user carries out secure erase or fast erase or senior erasing by hardware button to nand flash memory array.
As shown in Figure 3, the treatment scheme of solid state hard disc error in data protection is as described below:
First the data of npairpage are write, and by this data in advance with n-1, n-2, n-3, n=1, n+2, the form of n+3 is loaded into the second dram chip, and main control chip analyzes the data mode of the second dram chip, on the one hand, if mistake does not appear in the data mode of the second dram chip, then main control chip wipes the data be stored in dram chip; On the other hand, if mistake appears in the data mode of the second dram chip, again write the dram chip data being configured to nand flash memory array.After completing the process of data, turn back to the first step, namely first write this step of data of npairpage, until correct data all write nand flash memory array.First dram chip stores physical logic link table, and main control chip can according to the storage data manipulation nand flash memory array of the first dram chip.Traditional solid state hard disc does not have error protection function; and circuit design only adopts single dram chip; therefore the utility model is provided with two dram chips; second dram chip store both program data; whether main control chip is analyzed the second dram chip in advance exists misdata and determines that the second dram chip is the need of re-writing data, and main control chip can write data respectively by the first dram chip and the second dram chip to nand flash memory array afterwards.Therefore, adopt the circuit design of this structure, avoid adopting single DRAM and main control chip circuit design and cause the data writing NAND to occur the situation of mistake, and main control chip is more reliable and high efficiency writes correct data to NAND.
The announcement of book and instruction according to the above description, the utility model those skilled in the art can also change above-mentioned embodiment and revise.Therefore, the utility model is not limited to embodiment disclosed and described above, also should fall in the protection domain of claim of the present utility model modifications and changes more of the present utility model.In addition, although employ some specific terms in this instructions, these terms just for convenience of description, do not form any restriction to the utility model.
Claims (3)
1. there is a solid state hard disc for secure erase and error protection function, it is characterized in that: comprise power module, main control chip, GPIO interface, two dram chips, nand flash memory array and produce the hardware button of level signal; Described power module is connected with main control chip, the first dram chip, the second dram chip, nand flash memory array respectively, main control chip respectively with the first dram chip, the second dram chip, nand flash memory array are connected, and main control chip is also connected with hardware button by GPIO interface.
2. a kind of solid state hard disc with secure erase and error protection function according to claim 1, it is characterized in that: described power module comprises four power supply chips, nand flash memory array has flash memory input and output power interface and flash memory storage power interface, first power supply chip produces the first voltage and the first voltage is inputted the first dram chip and the second dram chip respectively, second source chip produces the second voltage and the second voltage is inputted main control chip, 3rd power supply chip produces tertiary voltage and tertiary voltage is inputted nand flash memory array by flash memory storage power interface, 4th power supply chip produces the 4th voltage and the 4th voltage is inputted nand flash memory array by flash memory input and output power interface.
3. a kind of solid state hard disc with secure erase and error protection function according to claim 2, it is characterized in that: described first voltage is 1.5V, the second voltage is 1.2V, and tertiary voltage is 1.8V, and the 4th voltage is 3.3V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520754541.3U CN205028663U (en) | 2015-09-28 | 2015-09-28 | Solid state hard drives with erase safely with wrong protect function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520754541.3U CN205028663U (en) | 2015-09-28 | 2015-09-28 | Solid state hard drives with erase safely with wrong protect function |
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| Publication Number | Publication Date |
|---|---|
| CN205028663U true CN205028663U (en) | 2016-02-10 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520754541.3U Expired - Fee Related CN205028663U (en) | 2015-09-28 | 2015-09-28 | Solid state hard drives with erase safely with wrong protect function |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115309346A (en) * | 2022-10-10 | 2022-11-08 | 苏州浪潮智能科技有限公司 | Server data erasing method, device, equipment and readable storage medium |
-
2015
- 2015-09-28 CN CN201520754541.3U patent/CN205028663U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115309346A (en) * | 2022-10-10 | 2022-11-08 | 苏州浪潮智能科技有限公司 | Server data erasing method, device, equipment and readable storage medium |
| CN115309346B (en) * | 2022-10-10 | 2023-02-28 | 苏州浪潮智能科技有限公司 | Server data erasing method, device, equipment and readable storage medium |
| WO2024077847A1 (en) * | 2022-10-10 | 2024-04-18 | 苏州元脑智能科技有限公司 | Server data erasing method, apparatus and device, and readable storage medium |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20180911 Address after: 243000 standardization plant 7 of Zhengpu New District and state Avenue Pu, Ma'anshan, Anhui. Patentee after: Ma'anshan Chuang long Polytron Technologies Inc Address before: 518000 F1.65C-1, Tianfa building, Tianan Che Kung Temple Industrial Zone, Futian District, Shenzhen, Guangdong. Patentee before: Shenzhen Chuangjiu Tech. Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160210 Termination date: 20190928 |