CN205003599U - Communications facilities frame of simplifying - Google Patents
Communications facilities frame of simplifying Download PDFInfo
- Publication number
- CN205003599U CN205003599U CN201520798556.XU CN201520798556U CN205003599U CN 205003599 U CN205003599 U CN 205003599U CN 201520798556 U CN201520798556 U CN 201520798556U CN 205003599 U CN205003599 U CN 205003599U
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- Prior art keywords
- programmable logic
- logic device
- smi
- backplate
- integrated circuit
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Abstract
The utility model discloses a communications facilities frame of simplifying, including the main control panel, backplate and a plurality of integrated circuit board, last CPU of being equipped with of the main control panel and the FPGA programmable logic device who is connected through AD BUS module and CPU, be equipped with 16 privately owned SMI management communication interface on the backplate, be equipped with CPLD programmable logic device on the integrated circuit board, a plurality of integrated circuit boards are all through each the privately owned SMI management communication interface on the CPLD programmable logic device that is equipped with and the backplate, each privately owned SMI management communication interface all with the main control panel on FPGA programmable logic device is connected, this connection structure backplate line is few, thus lay wire area and connector pin quantity reduction equipment cost's advantage of backplate sparingly, do not have interrelated disturbance between the integrated circuit board, stability is high, and the phenomenon of integrated circuit board mutual interference appears in bus mode easily, and equipment cost is low.
Description
Technical field
The utility model relates to a kind of communication apparatus machine frame of simplification, belongs to domain of communication equipment.
Background technology
Existing communication equipment, as MSTP, MSAP, OLT, PTN, SDH, IP-RAN etc., all adopt card insert type design, the way to manage of board adopts data bus or Ethernet mode to realize mostly, core bus mode mainly exist backboard line many, easily the shortcoming such as to interfere with each other; And Ethernet mode intercoms so there is high in cost of production shortcoming due to needs CPU phase.
Summary of the invention
For solving the problem, the utility model proposes a kind of line few, equipment does not interfere with each other the communication apparatus machine frame of the simplification low with cost.
The technical scheme that the utility model adopts is: a kind of communication apparatus machine frame of simplification, comprises master control board, backboard and multiple board; The FPGA programmable logic device (PLD) that described master control board is provided with CPU and is connected with CPU by A/DBUS module; Described backboard is provided with 16 privately owned SMI management communication interfaces; Described board is provided with CPLD programmable logic device (PLD); Described multiple board is all by each privately owned SMI management communication interface in the CPLD programmable logic device (PLD) that is provided with and backboard, and each privately owned SMI management communication interface is all connected with the FPGA programmable logic device (PLD) in master control board.
Compared with prior art, it has following beneficial effect to the utility model:
1, to have backboard line few for this programme, saves backboard wiring area and connector pin quantity thus reduce the advantage of equipment cost;
2, this programme adopts point-to-multipoint star-like connection, and there is not relevant interference between board, stability is high;
3, this programme adopts programmable logic device (PLD) cost low, and on board, CPLD chip cost is usually within 10 yuan, and Ethernet connected mode adopts CPU to carry out message communication usually, supports that the cpu system cost of Ethernet is about about 70 yuan.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
1-master control board; 2-backboard; 3-board; 4-CPU; 5-A/D-BUS module; 6-FPGA programmable logic device (PLD); 7-privately owned SMI management communication interface; 8-CPLD programmable logic device (PLD).
Embodiment
Clearly understand to make the purpose of this utility model, technical scheme and advantage, below in conjunction with drawings and the embodiments, the utility model is further elaborated, should be understood to, embodiment described herein only in order to explain the utility model, and is not used in restriction the utility model.
The communication apparatus machine frame of a kind of simplification as shown in Figure 1, comprises master control board 1, backboard 2 and multiple board 3; The FPGA programmable logic device (PLD) 6 that described master control board 1 is provided with CPU4 and is connected with CPU4 by A/DBUS module 5; Described backboard 2 is provided with 16 privately owned SMI management communication interfaces 7; Described board 3 is provided with CPLD programmable logic device (PLD) 9; Described multiple board 3 is all connected with each privately owned SMI management communication interface 7 on backboard 2 by the CPLD programmable logic device (PLD) 9 be provided with, and each privately owned SMI management communication interface 7 is all connected with the FPGA programmable logic device (PLD) 6 in master control board 1.
Master control board is the control monitoring unit of communication facilities, the status information of each board of real time monitoring and the relevant action of each board of control.This programme adopts FPGA and CPLD to realize privately owned SMI interface, for passing status information and the control information of board mutually.SMI interface is made up of CLK, SDI, SDO3 root line, adopts synchronous mode mutual data transmission, and data encoding is 4B/5B coding, and transfer rate can up to 50Mbps.The Frame of transmission is fixing frame length 64 byte, and every frame period is fixed as 2 bytes.
The up direction of SMI is that board reports this board relevant information and state to master control board, and content comprises: 2 byte board id informations, 2 byte board versions, 4 byte interrupt information, 8 byte warning information, 32 byte status information, and 16 bytes are reserved.
The down direction of SMI is that master control board sends relevant control operation to board, and content comprises: 1 byte control word, 32 byte control informations, 31 bytes are reserved.
Realize SMI communication interface in FPGA, the related content of communication is stored into respectively in 16 groups of condition managing registers and 16 groups of control registers, for CPU access and operation.FPGA is by the saltus step of monitoring each board SMI reported data simultaneously, draws the state in place of each board.FPGA also monitors the interrupting information that each board reports in addition, when there being interruption to produce, reports CPU immediately by interrupt pin.
The condition managing register of definition 16 boards in FPGA, associated plate card-like state and alarm is obtained for master cpu real time access, in FPGA, the control register of definition 16 boards, controls each board for master cpu, controls result by a relevant status register feedback CPU.Realize SMI communication interface in CPLD, become SMI dataframe to the FPGA of main controller the Information Organization required for SMI up direction.By receiving the information distribution of SMI down direction to related hardware control end, realize hardware controls.
Embodiment recited above is only be described preferred implementation of the present utility model, not limits design of the present utility model and scope.Under the prerequisite not departing from the utility model design concept; the various modification that this area ordinary person makes the technical solution of the utility model and improvement; protection domain of the present utility model all should be dropped into; the technology contents of the utility model request protection, all records in detail in the claims.
Claims (1)
1. the communication apparatus machine frame simplified, is characterized in that: comprise master control board, backboard and multiple board; The FPGA programmable logic device (PLD) that described master control board is provided with CPU and is connected with CPU by A/DBUS module; Described backboard is provided with 16 privately owned SMI management communication interfaces; Described board is provided with CPLD programmable logic device (PLD); Described multiple board is all by each privately owned SMI management communication interface in the CPLD programmable logic device (PLD) that is provided with and backboard, and each privately owned SMI management communication interface is all connected with the FPGA programmable logic device (PLD) in master control board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520798556.XU CN205003599U (en) | 2015-10-16 | 2015-10-16 | Communications facilities frame of simplifying |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520798556.XU CN205003599U (en) | 2015-10-16 | 2015-10-16 | Communications facilities frame of simplifying |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205003599U true CN205003599U (en) | 2016-01-27 |
Family
ID=55160477
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520798556.XU Expired - Fee Related CN205003599U (en) | 2015-10-16 | 2015-10-16 | Communications facilities frame of simplifying |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205003599U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681220A (en) * | 2017-01-13 | 2017-05-17 | 上海蔚来汽车有限公司 | Battery swap action control system based on central processing unit and programmable logic device |
-
2015
- 2015-10-16 CN CN201520798556.XU patent/CN205003599U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106681220A (en) * | 2017-01-13 | 2017-05-17 | 上海蔚来汽车有限公司 | Battery swap action control system based on central processing unit and programmable logic device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160127 Termination date: 20191016 |