CN204993694U - Single -chip four ways HD -CVI high definition video optical transmitter and receiver - Google Patents
Single -chip four ways HD -CVI high definition video optical transmitter and receiver Download PDFInfo
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- CN204993694U CN204993694U CN201520671529.6U CN201520671529U CN204993694U CN 204993694 U CN204993694 U CN 204993694U CN 201520671529 U CN201520671529 U CN 201520671529U CN 204993694 U CN204993694 U CN 204993694U
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Abstract
The utility model discloses a single -chip four ways HD -CVI high definition video optical transmitter and receiver, including power module, transmitting terminal module, receiving terminal module, filter circuit, the transmitting terminal module includes signal input module, first control ware, first optical module, the first control ware includes AD converting circuit, first control circuit, serializing ware circuit, the receiving terminal module includes signal output module, the second controllor, second optical module, the second controllor includes DA converting circuit, the 2nd control circuit, deseriallizer circuit. The utility model discloses a chip of NULL, serializing ware circuit and deseriallizer circuit adopts the chip of same model, has reduced the area that the chip took the circuit board, has reduced the manufacturing cost and the maintenance degree of difficulty of product hardware, has also improved video transmission's accuracy through using two clock sources of passive crystal oscillator and 8 doubling of frequency chips.
Description
Technical field
The utility model relates to a kind of HD video R-T unit, particularly relates to a kind of single-chip four road HD-CVI HD video optical transmitter and receiver.
Background technology
Video optical multiplexer is a kind of R-T unit of vision signal Optical Fiber Transmission, is divided into transmitting terminal and receiving terminal.At present, known conventional 4 road HD-CVI HD video optical transmitter and receivers are all, at transmitting terminal four high-speed a/d conversion chips, 4 road CVI high resolution video signal collectives are become data-signal, then the data-signal collected is sent in processor, parallel signal is converted into serial signal according to time-division principle by serializer by signal after treatment, then serial signal is sent into optical module and is converted into light signal, and light signal is sent by optical fiber; At receiving terminal, light signal changes into the signal of telecommunication by optical module, then the signal of telecommunication unstrings as parallel data through deserializer, parallel data is sent into processor and is carried out time division data reduction treatment, then the signal after process is sent into 4 high-speed d/a conversion chips and carry out corresponding CVI signals revivification, and exported by signal output apparatus.
Usually, the transmitting terminal of CVI video optical multiplexer adopts 4 high-speed a/d conversion chips to gather four tunnel high definition CVI vision signals, receiving terminal adopts 4 high-speed d/a conversion chip reduction CVI signals, too much chip can be used in the whole transmitting procedure of signal, a large amount of board area will be taken like this, add hardware cost and the maintenance difficulty of product.And the deserializer of the serializer of transmitting terminal and receiving terminal adopts the chip without model respectively, cannot unify to produce, add the hardware production cost of product.
Summary of the invention
The purpose of this utility model overcomes the deficiencies in the prior art, design a kind of single-chip four road HD-CVI HD video optical transmitter and receiver, solve too much chip and take the circuit board of larger area and chip model disunity and cause the problem that hardware production cost increases.
For achieving the above object, the technical scheme that the utility model adopts is:
A kind of single-chip four road HD-CVI HD video optical transmitter and receiver, comprise power module, transmitting terminal module, receiving terminal module, also comprise the filter circuit for filtering external interference ripple and stabilization signal be connected with power module, described transmitting terminal module comprises for carrying out filtering and amplifying signal input module to 4 road CVI high-definition video signals, for 4 road CVI high-definition video signals being converted into the first controller of high-speed differential signal, for high-speed differential signal being converted into the first optical module of light signal, described first controller comprises the A/D change-over circuit for 4 road CVI high resolution video signal collectives being become 4 tunnel 8 bit data signals, 8 bit data signals are comprised for being converted into by 4 tunnel 8 bit data signals, the first control circuit of 10 parallel-by-bit signals of 1 bit clock signal and 1 gating signal, for 10 parallel-by-bit train of signals being turned to the serializer circuit of high-speed differential signal, described receiving terminal module comprises the second optical module for light signal being reduced to high-speed differential signal, for high-speed differential signal being reduced to the second controller of 4 road CVI high-definition video signals, for carrying out filtering and amplifying signal output module to 4 road CVI high-definition video signals, it is the deserializer circuits of 10 parallel-by-bit signals that described second controller comprises for being unstringed by high-speed differential signal, for 10 parallel-by-bit signals being converted into the second control circuit of 4 tunnel 8 bit data signals, for 4 tunnel 8 bit data signals being converted into the D/A change-over circuit of 4 road CVI high-definition video signals, the chip of described serializer circuit and deserializer circuits is same model chip.
The signal output port of described serializer circuit and the signal input port of deserializer circuits are all connected to the resistance of coupling and stable difference signal.
Described first control circuit is connected an external clock reference respectively with the clock pins of second control circuit, described external clock reference comprises a passive crystal oscillator (Y1) and 8 frequency multiplication chips (U10), and the OUT pin of described 8 frequency multiplication chips (U10) is connected with the clock pins of first control circuit and second control circuit respectively by resistance (U226).
Described signal input module and signal output module all adopt SC6363 chip, and serializer circuit and deserializer circuits all adopt TLK2201 model chip.
The high-speed a/d conversion chip of described A/D change-over circuit is single channel A/D conversion chip, and model is SC9082; The high-speed d/a conversion chip of D/A change-over circuit is single channel D/A conversion chip, and model is SC9518.
Positive beneficial effect of the present utility model: the utility model passes through A/D change-over circuit, first control circuit, serializer circuit is integrated into the first controller, deserializer circuits, second control circuit, D/A conversion circuit is integrated into second controller, reduce the area that chip takies circuit board, reduce hardware cost and the maintenance difficulty of product, and the chip of serializer circuit and deserializer circuits adopts the chip of same model, also reduce the production cost of products-hardware, and by arranging filter circuit, better can filter extraneous interference, vision signal is stablized, simultaneously by passive crystal oscillator and these two clock sources of 8 frequency multiplication chips be whole system circuit improve pulse signal, improve the accuracy of transmission of video.
Accompanying drawing explanation
Fig. 1 is theory diagram of the present utility model
Fig. 2 is power circuit of the present utility model
Fig. 3 is signal input circuit and the A/D change-over circuit of the utility model transmitting terminal
Fig. 4 is the first control circuit of the utility model transmitting terminal
Fig. 5 is the serializer circuit of the utility model transmitting terminal
Fig. 6 is the first optical module circuit of the utility model transmitting terminal
Fig. 7 is the second optical module reconciliation circuit string device circuit of the utility model receiving terminal
Fig. 8 is the second control circuit of the utility model receiving terminal
Fig. 9 is signal output apparatus and the D/A change-over circuit of the utility model receiving terminal
Figure 10 is filter circuit of the present utility model
Embodiment
Specific embodiment of the utility model is illustrated below in conjunction with accompanying drawing.
As Figure 1-10 shows, a kind of single-chip four road HD-CVI HD video optical transmitter and receiver, comprise power module, transmitting terminal module, receiving terminal module, also comprise the filter circuit for filtering external interference ripple and stabilization signal be connected with power module, described transmitting terminal module comprises for carrying out filtering and amplifying signal input module to 4 road CVI high-definition video signals, for 4 road CVI high-definition video signals being converted into the first controller of high-speed differential signal, for high-speed differential signal being converted into the first optical module of light signal, described first controller comprises the A/D change-over circuit for 4 road CVI high resolution video signal collectives being become 4 tunnel 8 bit data signals, 8 bit data signals are comprised for being converted into by 4 tunnel 8 bit data signals, the first control circuit of 10 parallel-by-bit signals of 1 bit clock signal and 1 gating signal, for 10 parallel-by-bit train of signals being turned to the serializer circuit of high-speed differential signal, described receiving terminal module comprises the second optical module for light signal being reduced to high-speed differential signal, for high-speed differential signal being reduced to the second controller of 4 road CVI high-definition video signals, for carrying out filtering and amplifying signal output module to 4 road CVI high-definition video signals, it is the deserializer circuits of 10 parallel-by-bit signals that described second controller comprises for being unstringed by high-speed differential signal, for 10 parallel-by-bit signals being converted into the second control circuit of 4 tunnel 8 bit data signals, for 4 tunnel 8 bit data signals being converted into the D/A change-over circuit of 4 road CVI high-definition video signals.The chip of described serializer circuit and deserializer circuits is same model chip.
The signal input port of described serializer circuit and the signal output port of deserializer circuits are all connected to the resistance of coupling and stable difference signal.Described first control circuit is connected an external clock reference respectively with the clock pins of second control circuit, described external clock reference comprises a passive crystal oscillator (Y1) and 8 frequency multiplication chips (U10), and the OUT pin of described 8 frequency multiplication chips (U10) is connected with the clock pins of first control circuit and second control circuit respectively by resistance (U226).
Described signal input module and signal output module all adopt SC6363 chip, and serializer circuit and deserializer circuits all adopt TLK2201 model chip.
The high-speed a/d conversion chip of described A/D change-over circuit is single channel A/D conversion chip, and model is SC9082; The high-speed d/a conversion chip of D/A change-over circuit is single channel D/A conversion chip, and model is SC9518.
HD-CVI video optical multiplexer of the present utility model, at signal transmitting terminal, HD video is through the amplification of signal input circuit and filtration, be input in the first controller, process in the inside of the first controller, it is light signal by transform electrical signals that signal after treatment sends into the first optical module circuit, then is sent by fiber channel.Signal receiving end is an inverse process, and light signal sends into the second optical module by fiber channel, then sends into second controller, after the inter-process of second controller, send into signal output apparatus, exports after amplifying.
Transmitting terminal and receiving terminal all have a power circuit to provide the direct current of 3.3V and 2.5V for each circuit.For CVI single-chip of the present utility model, the clock frequency of A/D and D/A conversion chip is 58.9824MSPS, and the conversion rate of serializer is up to 1.6G, and the bandwidth of optical module is 2.0G, the utility model can gather high definition CVI video, can process HD video.For common simulation single-chip, the sample frequency of A/D conversion chip is the sample frequency of 13MSPS, D/A conversion chip is 20MSPS, and the conversion rate of serializer is up to 900M, and the bandwidth of optical module is 155M.
At transmitting terminal, signal input circuit adopts 2 SC6363 chips, 4 road high-definition video signals are filtered and amplified, 4 road high-definition video signals after filtering and amplifying input 23 pins of the A/D conversion chip of 4 SC9082 models of A/D change-over circuit respectively, from AA0-AA7 after the process of 4 A/D conversion chips, BB0-BB7, CC0-CC7 and DD0-DD7 pin exports 4 tunnel 8 bit data signals, this 4 tunnel 8 bit data signal is from the AB0-AB7 of the control chip of the EPM240 model of first control circuit, BC0-BC7, CD0-CD7 and DC0-DC7 pin inputs, 10 parallel-by-bit signals are exported from TXD0-TXD9 after control chip process, this 10 parallel-by-bit signal sends into the TD0-TD9 pin of the serializer of TLK2201 model, from TXN after serializer process, TXP pin exports, then signal sends into 7 of the first optical module chip, 8 pins, after the first optical module process, be converted into light signal send into fiber channel.
At receiving terminal, light signal inputs the second optical module, after treatment from 2 of optical module chip, 3 pins export, be input to deserializer 52 pin, the chip of deserializer circuits and serializer circuit be same model chip, also be TLK2201 model, signal exports 10 parallel-by-bit signals from RXD0-RXD9 pin after deserializer process, then the TXD0-TXD7 pin of the control chip of the EPM240 model of this 10 parallel-by-bit signal input second control circuit, after second control circuit process, from the AA0-AA7 of second control circuit, BB0-BB7, CC0-CC7 and DD0-DD7 pin exports 4 tunnel 8 bit data signals, then this 4 tunnel 8 bit data signal inputs the 2-9 pin of 4 D/A conversion chip SC9518 models respectively, the 4 road high-definition video signals obtained after the process of 4 D/A conversion chips send into 1 and 3 pins of 2 SC6363 chips of signal output apparatus respectively, final video signal exports from output.
Finally should be noted that: above embodiment is only in order to illustrate that the technical solution of the utility model is not intended to limit; Although be described in detail the utility model with reference to preferred embodiment, those of ordinary skill in the field have been to be understood that; Still can modify to embodiment of the present utility model or equivalent replacement is carried out to portion of techniques feature; And not departing from the spirit of technical solutions of the utility model, it all should be encompassed in the middle of the technical scheme scope of the utility model request protection.
Claims (5)
1. a single-chip four road HD-CVI HD video optical transmitter and receiver, comprise power module, transmitting terminal module, receiving terminal module, it is characterized in that: also comprise the filter circuit for filtering external interference ripple and stabilization signal be connected with power module, described transmitting terminal module comprises for carrying out filtering and amplifying signal input module to 4 road CVI high-definition video signals, for 4 road CVI high-definition video signals being converted into the first controller of high-speed differential signal, for high-speed differential signal being converted into the first optical module of light signal, described first controller comprises the A/D change-over circuit for 4 road CVI high resolution video signal collectives being become 4 tunnel 8 bit data signals, 8 bit data signals are comprised for being converted into by 4 tunnel 8 bit data signals, the first control circuit of 10 parallel-by-bit signals of 1 bit clock signal and 1 gating signal, for 10 parallel-by-bit train of signals being turned to the serializer circuit of high-speed differential signal, described receiving terminal module comprises the second optical module for light signal being reduced to high-speed differential signal, for high-speed differential signal being reduced to the second controller of 4 road CVI high-definition video signals, for carrying out filtering and amplifying signal output module to 4 road CVI high-definition video signals, it is the deserializer circuits of 10 parallel-by-bit signals that described second controller comprises for being unstringed by high-speed differential signal, for by 10 parallel-by-bit signals revivification being the second control circuit of 4 tunnel 8 bit data signals, for by 4 tunnel 8 bit data signals revivification being the D/A change-over circuit of 4 road CVI high-definition video signals, the chip of described serializer circuit and deserializer circuits is same model chip.
2. single-chip four road according to claim 1 HD-CVI HD video optical transmitter and receiver, is characterized in that: the signal output port of described serializer circuit and the signal input port of deserializer circuits are all connected to the resistance of coupling and stable difference signal.
3. single-chip four road according to claim 1 HD-CVI HD video optical transmitter and receiver, it is characterized in that: described first control circuit is connected an external clock reference respectively with the clock pins of second control circuit, described external clock reference comprises a passive crystal oscillator (Y1) and 8 frequency multiplication chips (U10), and the OUT pin of described 8 frequency multiplication chips (U10) is connected with the clock pins of first control circuit and second control circuit respectively by resistance (U226).
4. single-chip four road according to claim 1 HD-CVI HD video optical transmitter and receiver, it is characterized in that: described signal input module and signal output module all adopt SC6363 chip, serializer circuit and deserializer circuits all adopt TLK2201 model chip.
5. single-chip four road according to claim 1 HD-CVI HD video optical transmitter and receiver, is characterized in that: the high-speed a/d conversion chip of described A/D change-over circuit is single channel A/D conversion chip, and model is SC9082; The high-speed d/a conversion chip of D/A change-over circuit is single channel D/A conversion chip, and model is SC9518.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520671529.6U CN204993694U (en) | 2015-09-01 | 2015-09-01 | Single -chip four ways HD -CVI high definition video optical transmitter and receiver |
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| CN201520671529.6U CN204993694U (en) | 2015-09-01 | 2015-09-01 | Single -chip four ways HD -CVI high definition video optical transmitter and receiver |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577632A (en) * | 2017-09-27 | 2018-01-12 | 郑州云海信息技术有限公司 | A kind of circuit board signal transmission system, method and programmable integrated circuit |
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2015
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107577632A (en) * | 2017-09-27 | 2018-01-12 | 郑州云海信息技术有限公司 | A kind of circuit board signal transmission system, method and programmable integrated circuit |
| CN107577632B (en) * | 2017-09-27 | 2020-11-20 | 苏州浪潮智能科技有限公司 | Circuit board signal transmission system and method and programmable integrated circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20160120 Termination date: 20200901 |
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| CF01 | Termination of patent right due to non-payment of annual fee |