CN204993266U - Variable gain amplifier in radiofrequency signal transceiver chip - Google Patents
Variable gain amplifier in radiofrequency signal transceiver chip Download PDFInfo
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- CN204993266U CN204993266U CN201520598433.1U CN201520598433U CN204993266U CN 204993266 U CN204993266 U CN 204993266U CN 201520598433 U CN201520598433 U CN 201520598433U CN 204993266 U CN204993266 U CN 204993266U
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Abstract
The utility model provides a variable gain amplifier can be applied to big dynamic incoming signal's receiver and the control of the point -device gain step -length of realization to it receives influence of temperature less. This variable gain amplifier in radiofrequency signal transceiver chip includes at least one low triad variable gain amplifying unit, at least one two high column binary system variable gain amplifying unit for the bias circuit of enable signal and the same tail current is provided to low triad variable gain amplifying unit, two high column binary system variable gain amplifying units, two way signals of quadrature carry on exporting after variable gain enlargies through low triad variable gain amplifying unit and two high column binary system variable gain amplifying units in proper order, or two way signals of quadrature carry on exporting after variable gain enlargies through two high column binary system variable gain amplifying units and low triad variable gain amplifying unit in proper order.
Description
Technical field
The present invention relates to a kind of for the variable gain amplifier in radiofrequency signal transceiving chip, be specially adapted to the single-chip integration radio frequency chip applied in GPS and Big Dipper wideband radio receiver.
Background technology
Along with the difference of Signal transmissions condition that radio-frequency transmitter receives, the power of the useful signal that antenna receives can change in a very large scope, and the power of interference that antenna receives simultaneously also likely changes.
In order to finally can the signal that receives of demodulation antenna, the desired signal of the different capacity needing gain-changeable amplifier circuit to be received by antenna be amplified to base band analog to digital converter quantize needed for optimal power.Farthest can reduce the quantizing noise that base band analog-to-digital conversion device is introduced like this, thus provide optimum signal to noise ratio, to reach the minimum error rate for demodulator.
High performance gain-changeable amplifier circuit is extremely important to realizing high performance radio-frequency transmitter: the gain-changeable amplifier circuit of great dynamic range can improve the input signal dynamic range of radio-frequency transmitter; The gain-changeable amplifier circuit of low-power consumption can reduce the total power consumption of radio-frequency transmitter; The gain-changeable amplifier circuit of quick lock in can help the environment of radio-frequency transmitter switching channels and Adaptive change rapidly.
Existing variable gain amplifier control precision is lower, the different capacity signal being difficult to antenna to receive is amplified to the power quantized and needed for demodulation, and in receiving course easy temperature influence, therefore needing badly provides a kind of and can realize accurately controlling and adapt to the variable gain amplifier of various environment.
Summary of the invention
The object of the invention is mainly to solve the problem that the different capacity signal received by antenna is amplified to quantification and demodulation power demand.Variable gain amplifier of the present invention can be applied to the receiver of great dynamic range input signal and realize the control of point-device gain step size, and its impact by temperature is less.
Concrete technical solution of the present invention is as follows:
Variable gain amplifier in this radiofrequency signal transceiver chip comprises at least one low triad variable gain amplifying unit, at least one high two binary system variable gain amplifying unit, for providing the biasing circuit of enable signal with identical tail current to low triad variable gain amplifying unit, high two binary system variable gain amplifying units; Orthogonal two paths of signals exports successively after low triad variable gain amplifying unit and high two binary system variable gain amplifying units carry out variable gain amplification; Or orthogonal two paths of signals exports successively after high two binary system variable gain amplifying units and low triad variable gain amplifying unit carry out variable gain amplification.
If described variable gain amplifying unit be two and two or more time, cascade between multiple variable gain amplifying units of low triad, cascade between high two binary multiple variable gain amplifying units.
Above-mentioned low triad variable gain amplifying unit and high two binary system variable gain amplifying units are the variable gain amplifier adopting ohmic load as trans-impedance amplifier.
Above-mentioned biasing circuit comprises and door AND2X2, NMOS tube (M3, M17), two inverter INVX2, enable signal EN and mode select signal MODE is first by producing signal ENN with door AND2X2, signal ENN receives the grid of NMOS tube M17, enable signal EN and mode select signal MODE produces signal ENB by inverter INVX2 again, and signal ENB receives the grid of NMOS tube M3; Under the effect that enable signal EN and mode select signal MODE opens, and signal EN, signal MODE, signal ENN are when being high level, first input signal IB25 sends into IB, the digital controlled signal BI<2:0> of input is first by two inverter INVX2, and then the output signal IB2 of biasing circuit is controlled together with input IB25 signal, IB1, IB0.
Above-mentioned high two binary system variable gain amplifying units comprise inverter INVX2, NMOS tube (M0, M4, M21, M74), PMOS (M13, M17, M80, M81) and electric resistance array module RES2, enable signal EN produces signal BENB through inverter INVX2, and signal BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in high two binary system variable gain amplifying units, BENB produces signal BEN through an inverter again, and signal BEN receives the grid of NMOS tube M4, input digital controlled signal B<4>, the colleague of B<3> in input signal port B<4> and B<3> of electric resistance array RES2 delivering to VGA2, input digital controlled signal B<4>, B<3> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M81, signal S2 delivers to the grid of PMOS M13 and M80, an electric resistance array module RES2 is comprised in high two binary system variable gain amplifying units, the input A port of electric resistance array module RES2 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M74, by regulating the resistance size of RES2 input signal B<4> and B<3> control RES2, and then control the gain size of high two binary system variable gain amplifying units.
The input digital controlled signal B<4> of above-mentioned electric resistance array module RES2, B<3> is first by 2 line-4 line encoders, produce the coding control signal S1 of 4 kinds of states, S2, S3, S4, by coding control signal S1, the resistance value size of cut-offfing between control input end A and output B of S2, S3, S4.
Above-mentioned low triad variable gain amplifying unit comprises inverter INVX2, NMOS tube (M0, M4), PMOS (M13, M17, M21, M26, M43, M44) NAND gate NAND2X1, NOR gate NOR2X1, electric resistance array module RES1; Enable signal EN produces signal BENB through inverter INVX2, and signal BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in low triad variable gain amplifying unit; Signal BENB produces signal BEN through inverter again, and signal BEN receives the grid of NMOS tube M4; Input digital controlled signal B<2>, B<1> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M44, and signal S2 delivers to the grid of PMOS M13 and M43; The input A port of described electric resistance array module RES1 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M26, digital controlled signal B<2> is inputted by regulating RES1, B<1>, B<0> just can the resistance size of control RES1, and then controls the gain size of low triad variable gain amplifying unit.
The input digital controlled signal B<2> of above-mentioned electric resistance array module RES1, B<1>, B<0>, first by 3 line-8 line encoders, produce the coding control signal S1 of 8 kinds of states, S2, S3, S4, S5, S6, S7, S8, by coding control signal S1, S2, S3, S4, S5, the resistance value size of cut-offfing between control input end A and output B of S6, S7, S8.
The invention has the advantages that:
Present invention employs by three grades of variable gain amplifiers of five bit binary number signal controlling (two variable gain amplifiers 2 and a variable gain amplifier 1), every grade all adopts ohmic load as the variable gain amplifier of trans-impedance amplifier.The invention has the beneficial effects as follows can receive great dynamic range input signal, achieve point-device gain step size control and the control of gain less by the impact of temperature, structure is simple, be easy to the feature that realizes, there is good Social and economic benef@, be applicable to large-scale promotion application.
Accompanying drawing explanation
Fig. 1 is the overall structure figure of variable gain amplifier;
Fig. 2 is biasing circuit schematic diagram in Fig. 1;
Fig. 3 is the generation module of digital controlled signal in Fig. 1;
Fig. 4 is variable gain amplifier 2 schematic diagram in Fig. 1;
Fig. 5 is the generation module of digital controlled signal in Fig. 4;
Fig. 6 is part of module in Fig. 4;
Fig. 7 is part of module in Fig. 4;
Fig. 8 is part of module in Fig. 4;
Fig. 9 is electric resistance array RES2 and logic schematic diagram thereof in Fig. 4;
Figure 10 is the digital module (2-4 encoder) in Fig. 9;
Figure 11 is the electric resistance array in Fig. 9;
Figure 12 is variable gain amplifier 1 schematic diagram in Fig. 1;
Figure 13 is the generation module of digital controlled signal in Figure 12;
Figure 14 is part of module in Figure 12;
Figure 15 is part of module in Figure 12;
Figure 16 is part of module in Figure 12;
Figure 17 is electric resistance array RES1 and logic schematic diagram thereof in Figure 12;
Figure 18 is digital module in Figure 17 (3-8 encoder);
Figure 19 is electric resistance array in Figure 17;
Embodiment
The concrete principle of variable gain amplifier in radiofrequency signal transceiver chip provided by the invention is:
Comprise a variable gain amplifier 1, adopt low its gain of triad Digital Signals, according to the assignment of three position digital signals, the gain of variable gain amplifier 1 can change thereupon.
Comprise a variable gain amplifier 2, adopt high two its gains of bit binary number signal controlling, according to the assignment of two digits signal, the gain of variable gain amplifier 2 can change thereupon.Have employed the form of two variable gain amplifiers 2 cascade here, and they are all with high two its gains of bit binary number signal controlling.
Also comprise a biasing circuit, biasing circuit provides identical tail current for variable gain amplifier 1 and two variable gain amplifiers 2, and for they provide enable signal.Biasing circuit is variable tail current source, adopts triad digital signal to control.
The orthogonal two paths of signals exported through frequency mixer enters first variable gain amplifier 2, and the value according to high two digits control signal B4, B3 carries out corresponding gain control to it; The two-pass DINSAR output signal of first variable gain amplifier 2 enters second variable gain amplifier 2, and the value according to high two digits control signal B<4>, B<3> carries out corresponding gain control to it; The two-pass DINSAR output signal of second variable gain amplifier 2 enters variable gain amplifier 1, and variable gain amplifier 1 carries out corresponding gain control according to the value of low three bit digital control signal B<2>, B<1>, B<0> to this two paths of signals; Finally, the two-pass DINSAR output signal of variable gain amplifier 2 is given analog to digital converter and is processed.Meanwhile, biasing circuit under the control of triad digital signal BI<2:0> for two variable gain amplifiers 2 provide enable signal and identical bias current with a variable gain amplifier 1.
Below in conjunction with accompanying drawing, content of the present invention is described further:
With reference to shown in Fig. 1, variable gain amplifier is made up of two variable gain amplifiers 2 (VGA2), a variable gain amplifier 1 (VGA1) and a biasing circuit (VGA_Bias).
Through the orthogonal two paths of signals VIN that frequency mixer exports, VIP sends into first VGA2, VGA2 carries out variable gain amplification to input signal under the control of control signal B<4>, B<3>; The output signal VON of first VGA2, VOP sends into second VGA2 input VIN and VIP, second VGA2 carries out variable gain amplification to input signal under the control of control signal B<4>, B<3> afterwards; The output signal VON of second VGA2, VOP sends into input VIN and VIP of VGA1, afterwards, VGA1 is at control signal B<2>, B<1>, under the control of B<0>, variable gain amplification is carried out to input signal, and output signal VON, a VOP are delivered to and processed in analog to digital converter.In the processing procedure of whole signal, biasing circuit VGA_Bias is at input signal IB25, enable signal EN, corresponding bias current and enable signal is provided to VGA1 and VGA2 under the effect of mode select signal MODE and three bit digital control signal BI<2:0>, the output signal ENN of VGA_Bias delivers to the Enable Pin EN of VGA1 and VGA2, output signal IB0 delivers to the IB25 port of first VGA2, output signal IB1 delivers to the IB25 port of second VGA2, and output signal IB2 delivers to the IB25 port of VGA1.
Core of the present invention is to adopt five digit number control signal, the different capacity signal that antenna can be received is amplified to quantification and demodulation power demand supplies analog to digital converter process, and has the receiver that can be applied to great dynamic range input signal, the feature realizing the control of point-device gain step size and be subject to the impact of temperature less.
Figure 2 shows that biasing circuit schematic diagram.Enable signal EN and mode select signal MODE first produces signal ENN by one with door AND2X2, and ENN receives the grid of NMOS tube M17; Produce signal ENB by an inverter INVX2 again, ENB receives the grid of NMOS tube M3; Under the effect that enable signal EN and mode select signal MODE opens (when and if only if here EN and MODE is high level, ENN is high level), first input signal IB25 sends into IB, the digital controlled signal BI<2:0> of input is first by two inverter INVX2, and then the output signal IB2 of biasing circuit is controlled together with input IB25 signal, IB1, IB0.Other modules that biasing circuit is variable gain amplifier provide identical bias current and enable signal.
Biasing circuit specifically can adopt following frame mode: biasing circuit VGA_Bias module comprises the transistor M1 that type is pmos2v, M8, M11, M12, M13, M14, M18, type is the transistor M0 of nmos2v, M2, M3, M4, M5, M6, M7, M9, M15, M16, M17, and the inverter (INVX2) identical with seven with door (AND2X2) of one two input.
Two input with door AND2X2 inside comprise the transistor 1 that three types are pmos2v, 2, 3 and type be the transistor 0 of noms2v, 4, 5 totally six transistors, transistor 3 and transistor 5 grid link together as input A, and the source electrode of collective's pipe 3 and transistor 2 is connected in the drain electrode of transistor 5, the source electrode of transistor 5 is connected in the drain electrode of transistor 4, transistor 0 is received on the source electrode of transistor 2 together with the grid of transistor 1, and the drain electrode of the source electrode of transistor 1 and transistor 0 is connected together as output port Y, transistor 2 and transistor 4 grid link together as input B, transistor 1, 2, the drain electrode of 3 is all connected on VDD, transistor 0, 4, the source electrode equal 4 of 5 is connected on VSS.
Inverter INVX2 inside comprises the transistor 1__1 that two types are pmos2v, 1__2 and one type is transistor 0 totally three transistors of nmos2v, transistor 1__1, the grid of 1__2 and the grid of transistor 0 are connected together as input A, their source electrode and the drain electrode of transistor 0 are connected together as output port Y, their drain electrode is connected together and follows power vd D to be connected together, and source electrode and the VSS of transistor 0 are connected together.
Input signal MODE and input enable signal EN delivers to input port A and B of two inputs and door respectively, produces the input port A that output signal ENN, signal ENN deliver to an inverter again, produces output signal ENB through inverter.
Three bit digital control signal BI<2:0> of input, respectively by two inverters, produce three output digit signals BNN<2:0>.
Input signal IB delivers to the drain electrode of transistor M17, the grid of M17 receives ENN, the drain and gate of its source electrode and transistor M0, transistor M2, M5, M6, the grid of M7, the drain electrode of transistor M3, the grid of transistor M4 is connected together, the grid of transistor M3 receives ENB, transistor M0, M2, M3, M5, M6, the grid of M7, the source electrode of transistor M4 and drain electrode and substrate are all connected on GND, transistor M5, M6, the drain electrode of M7 receives M9 respectively, M15, on the source electrode of M16, the grid of M9 meets BNN<2>, the grid of M15 meets BNN<1>, the grid of M16 meets BNN<0>, their drain electrode be connected together and with the drain electrode of M2, the grid of M1 and drain electrode, the grid of M14, the grid of M18, the grid of M13, the grid of M8, the grid of M11, the grid of M12 is connected together, the source electrode of M1, the source electrode of M14 and drain electrode, the source electrode of M18 and drain electrode, the source electrode of M13 and drain electrode, the source electrode of M8, the source electrode of M11, the source electrode of M12 is all connected together with VDD, M8, M11, the drain electrode of M12 is connected respectively to output port IB2, IB1, IB0, transistor M1, M14, M18, M13, M8, M11, the substrate of M12 all meets VDD, transistor M17, M0, M2, M3, M5, M6, M7, M9, M15, the substrate of M16 all meets SUB, the substrate of transistor M4 meets GND.
Figure 4 shows that variable gain amplifier 2 schematic diagram.Enable signal EN produces signal BENB through an inverter INVX2, and BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in VGA2, BENB produces signal BEN through an inverter again, and BEN receives the grid of NMOS tube M4, input digital controlled signal B<4>, B<3> mono-delivers to aspect in input signal port B<4> and B<3> of the electric resistance array RES2 of VGA2, on the other hand, input digital controlled signal B<4>, B<3> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M81, signal S2 delivers to the grid of PMOS M13 and M80.An electric resistance array module RES2 is comprised in variable gain amplifier VGA2, wherein the input A port of RES2 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M74, by regulating RES2 input signal B<4> and B<3>, just can the resistance size of control RES2, and then the gain size of control VGA2.
Variable gain amplifier specifically can adopt following frame mode:
Variable gain amplifier VGA2 comprises the transistor M6 that type is pmos2v, M1, M7, M10, M15, M12, M13, M17, M9, M19, M18, M20, M21, M79, M78, M77, M76, M80, M81, M82, M83, M74, M75, M65, M66, M67, M68, M69, M71; Type is the transistor M0 of noms2v, M2, M3, M4, M5, M7, M8, M11, M14, M16, M22, M23, M70, M88, M85, M86, M87, M84, M72, M73; Type is the resistance R0 of rphpoly, R1, R2, R3, R4, R7, R6, R14, R11, R13, mimcap electric capacity C0, C1, two inverters (inverter in its configuration biases circuit is identical), two input and door (in its structure and biasing circuit two input identical with door), one two input XOR gate NOR2X1, an electric resistance array RES2.
Two input XOR gate NOR2X1 comprise two pmos2v transistors 0, 1 (their substrate is connected on VDD) and two nmos2v transistors 2, 3 (their substrate is connected on VSS), wherein the grid of transistor 0 and transistor 2 is connected together as input port B, the grid of transistor 1 and transistor 3 is connected together as input port A, the drain electrode of transistor 0 is connected on VDD, source electrode is received in the drain electrode of transistor 1, the source electrode of transistor 1, transistor 2 drains, the drain electrode of transistor 3 is connected together as output port Y, the source electrode of transistor 2 and transistor 3 is all received on VSS.
Input enable signal EN produces output signal BENB, signal BENB by an inverter and produces output signal BEN by an inverter again, and the BENB of generation receives the grid of M4, and BEN receives the grid of M0.Input signal B3 and B4 receives input port B and the A of two inputs and door respectively, produces output signal S1, the S1 of generation and receives the grid of transistor M17 and M81.
Input signal B3 and B4 receives input port B and the A of two input XOR gate respectively, produces output signal S2, the S2 of generation and receives the grid of transistor M13 and M80.
Input differential signal VIP and VIN is connected on C0 and C1 respectively, the grid of other end connecting resistance R4 and M11 of electric capacity C0, the grid of other end connecting resistance R7 and M88 of electric capacity C1, the other end of resistance R4 and resistance R7 is connected together, and be connected with one end of resistance R1 with resistance R0, another termination R3 of another termination VDD, the R1 of R0 and one end of R2, the grid of another termination transistor M68 and M69 of resistance R3, another termination GND of resistance R2.
Input signal IB25 receives the drain electrode of M0, the source electrode of M0 and the drain and gate of M2, the drain electrode of M4, the grid of M3, the grid of M5, the grid of M16, the grid of M22, the grid of M85, the grid of M86 is connected together, M2, M4, M3, M5, the source electrode of M8 meets GND, the drain electrode of M3 and the drain and gate of M6, the grid of M1, the grid of M9, the grid of M76, the grid of M65, the grid of M66 is connected together, M6, the source electrode of M1 and M7 all meets VDD, the grid of M7 and drain electrode be connected together and with the drain electrode of M5, the grid of M20 and M21, the grid of M74 and M75 is connected together, the drain electrode of M1 and the grid of M6 and drain electrode, the grid of M14, the grid of M87 links together, M10, M15, the drain electrode of M12 and source electrode are all connected on VDD, and the grid of M10 connects the source electrode of M13, and the grid of M15 connects the source electrode of M17, and the drain electrode of M13 and M17 and the grid of M12 are connected together, and are connected with one end of resistance R6, the other end of R6 and the drain electrode of M9, the grid of M18, the grid of M19, the drain electrode of M11 links together, and the source electrode of M9 meets VDD, and the source electrode of M19 and M18 meets VDD, and their drain electrode connects the source electrode of M20 and M21 respectively, and the drain electrode of M20 meets output port VOP, and with the drain electrode of M14, one end of resistance R11 is connected, the grid of another termination M70 of resistance R11, and the source electrode of M14 connects the drain electrode of M23, and the grid of M23 follows the grid of M84, the grid of M73 and drain electrode, the drain electrode of M69 and M68 is connected together, and the source electrode of M23 meets GND, and the drain electrode of M21 meets the input port A of RES2, and with the source electrode of M11, the drain electrode of M16, the drain electrode of M22 is connected together, and the source electrode of M16 and M22 meets GND, M79, M78, source electrode and the drain electrode of M77 all meet VDD, and the grid of M78 connects the source electrode of M81, and the grid of M77 connects the source electrode of M80, and their drain electrode and the grid of M79 are connected together, and are connected with one end of resistance R14, the other end of R14 and the drain electrode of M76, the grid of M82 and M83, the drain electrode of M88 is connected together, the source electrode of M76 meets VDD, and the source electrode of M82 and M83 meets VDD, and their drain electrode connects the source electrode of M74 and M75 respectively, the drain electrode of M75 meets output port VON, and be connected with one end of resistance R13 with the drain electrode of M87, the other end of R13 is connected with the grid of M70, and source electrode and the drain electrode of M70 link together, the source electrode of M87 is connected with the drain electrode of M84, the source electrode of M84 meets GND, and the drain electrode of M74 meets the output port B of RES2, and with the drain electrode of M85, the source electrode of M88, the drain electrode of M86 is connected, the source electrode of M85 and M86 meets GND, the source electrode of M65 and M66 meets VDD, and the drain electrode of M65 connects the source electrode of M67 and M69, and the drain electrode of M66 connects the source electrode of M68 and M71, the drain electrode of M67 is connected with the drain electrode of M71, and be connected with drain electrode with the grid of M72, the source electrode of M72 and M73 meets GND, and the grid of M67 meets VOP, the grid of M71 meets VON, B3 and B4 receives B4 and the B3 port of RES2 respectively.The substrate of M67, M69, M68, M71, M11, M88 is connected respectively at their source electrode, and the substrate of remaining pmos2v all meets VDD, and nmos2v meets SUB, and VSS meets GND.
Figure 9 shows that electric resistance array RES2 and logic schematic diagram thereof.Input digital controlled signal B<4>, B<3>, first by 2 line-4 line encoders, produces the coding control signal S1 of 4 kinds of states, S2, S3, S4, its state relation provides in the drawings.Just can resistance value size between control input end A and output B by cut-offfing of these four control signals.Its breaker in middle adopts NMOS tube to realize.
Electric resistance array RES2 specifically can adopt following frame mode:
Electric resistance array RES2 comprises one and inputs with 4 two the 2-4 encoder, the resistance R0 that form with door (inverter in its structure and biasing circuit is identical) by 4 inverters (its structure is identical with the inverter in biasing circuit), R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R17, R18, R19, R21, R23, R32, R33, R25, R26, R24, R27, R28, R28, type are the transistor M0 of nmos2v, M2, M3, M4.Input signal exports S1 through a common 2-4 encoder, S2, S3, S4 tetra-control signals, S1, S2, S3, S4 is connected respectively to M0, M2, M3, the grid of M4, the source electrode of M0 connects one end of R2, one end of another termination R0 of R2, another termination input port A of R0, the drain electrode of M0 connects one end of R4, one end of another termination R3 of R4, another termination output port B of R3, the source electrode of M2 connects one end of R7 and R8, the other end of R7 with R8 is connected, and connect with one end of R6, another termination R5 of R6, another termination A of R5, the drain electrode of M2 connects one end of R9 and R10, the other end of R9 and R10 connects, and connect with one end of R11, another termination R12 of R11, another termination B of R12, the source electrode of M3 connects one end of R17 and R19, another termination R18 of R17, the other end of R18 is connected with the other end of R19, and be connected with R13, the other end of R13 connects with A, the drain electrode of M3 connects one end of R21 and R32, another termination R33 of R32, the other end of R33 is connected with the other end of R21, and be connected with one end of R23, the other end of R23 is connected with B, the source electrode of M4 meets R24 and R26, another termination R25 of R26, the other end of another termination R24 of R25, and be connected with A, the drain electrode of M4 meets R28 and R29, another termination R27 of R28, the other end of another termination R29 of R27, and be connected with B, VSS meets GND, M0, M2, M3, the substrate of M4 meets SUB.
Figure 12 shows that variable gain amplifier 1 schematic diagram.Enable signal EN produces signal BENB through an inverter INVX2, and BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in VGA1; BENB produces signal BEN through an inverter again, and BEN receives the grid of NMOS tube M4; Input digital controlled signal B<2>, B<1> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M44, and signal S2 delivers to the grid of PMOS M13 and M43.An electric resistance array module RES1 is comprised in variable gain amplifier VGA1, wherein the input A port of RES1 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M26, digital controlled signal B<2> is inputted by regulating RES1, B<1>, B<0> just can the resistance size of control RES1, and then the gain size of control VGA1.
Variable gain amplifier VGA1 specifically can adopt following frame mode:
Variable gain amplifier VGA1 comprises the transistor M6 that type is pmos2v, M1, M7, M10, M15, M12, M13, M17, M9, M19, M18, M20, M21, M40, M41, M42, M39, M43, M44, M32, M33, M26, M27, M65, M66, M67, M68, M69, M71, type is the transistor M0 of noms2v, M2, M3, M4, M5, M7, M8, M11, M14, M16, M22, M23, M70, M38, M34, M36, M35, M7, M72, M73, type is the resistance R0 of rphpoly, R1, R2, R3, R4, R5, R6, R8, R11, R12, mimcap electric capacity C0, C1, two inverters (its structure is identical with the inverter in biasing circuit), one two input and door (in its structure and biasing circuit two input identical with door), one two input XOR gate NOR2X1, an electric resistance array RES1 (it specifically describes in claim 8).
Two input XOR gate NOR2X1 comprise two pmos2v transistors 0, 1 (their substrate is connected on VDD) and two nmos2v transistors 2, 3 (their substrate is connected on VSS), wherein the grid of transistor 0 and transistor 2 is connected together as input port B, the grid of transistor 1 and transistor 3 is connected together as input port A, the drain electrode of transistor 0 is connected on VDD, source electrode is received in the drain electrode of transistor 1, the source electrode of transistor 1, transistor 2 drains, the drain electrode of transistor 3 is connected together as output port Y, the source electrode of transistor 2 and transistor 3 is all received on VSS.
Input enable signal EN produces output signal BENB, signal BENB by an inverter and produces output signal BEN by an inverter again, and the BENB of generation receives the grid of M4, and BEN receives the grid of M0.Input signal B<1> and B<2> receives input port B and the A of two inputs and door respectively, produces output signal S1, the S1 of generation and receives the grid of transistor M17 and M44.Input signal B<1> and B<2> receives input port B and the A of two input XOR gate respectively, produces output signal S2, the S2 of generation and receives the grid of transistor M13 and M43.
Input differential signal VIP and VIN is connected on C0 and C1 respectively, the grid of other end connecting resistance R4 and M11 of electric capacity C0, the grid of other end connecting resistance R5 and M38 of electric capacity C1, the other end of resistance R4 and resistance R5 is connected together, and be connected with one end of resistance R1 with resistance R0, another termination R3 of another termination VDD, the R1 of R0 and one end of R2, the grid of another termination transistor M68 and M69 of resistance R3, another termination GND of resistance R2.Input signal IB25 receives the drain electrode of M0, the source electrode of M0 and the drain and gate of M2, the drain electrode of M4, the grid of M3, the grid of M5, the grid of M16, the grid of M22, the grid of M34, the grid of M35 is connected together, M2, M4, M3, M5, the source electrode of M8 meets GND, the drain electrode of M3 and the drain and gate of M6, the grid of M1, the grid of M9, the grid of M39, the grid of M65, the grid of M66 is connected together, M6, the source electrode of M1 and M7 all meets VDD, the grid of M7 and drain electrode be connected together and with the drain electrode of M5, the grid of M20 and M21, the grid of M26 and M27 is connected together, the drain electrode of M1 and the grid of M6 and drain electrode, the grid of M14, the grid of M37 links together, M10, M15, the drain electrode of M12 and source electrode are all connected on VDD, and the grid of M10 connects the source electrode of M13, and the grid of M15 connects the source electrode of M17, and the drain electrode of M13 and M17 and the grid of M12 are connected together, and are connected with one end of resistance R6, the other end of R6 and the drain electrode of M9, the grid of M18, the grid of M19, the drain electrode of M11 links together, and the source electrode of M9 meets VDD, and the source electrode of M19 and M18 meets VDD, and their drain electrode connects the source electrode of M20 and M21 respectively, and the drain electrode of M20 meets output port VOP, and with the drain electrode of M14, one end of resistance R11 is connected, the grid of another termination M70 of resistance R11, and the source electrode of M14 connects the drain electrode of M23, and the grid of M23 follows the grid of M36, the grid of M73 and drain electrode, the drain electrode of M69 and M68 is connected together, and the source electrode of M23 meets GND, and the drain electrode of M21 meets the input port I of RES1, and with the source electrode of M11, the drain electrode of M16, the drain electrode of M22 is connected together, and the source electrode of M16 and M22 meets GND, M40, M41, source electrode and the drain electrode of M42 all meet VDD, and the grid of M40 connects the source electrode of M43, and the grid of M41 connects the source electrode of M44, and their drain electrode and the grid of M42 are connected together, and are connected with one end of resistance R8, the other end of R8 and the drain electrode of M39, the grid of M32 and M33, the drain electrode of M38 is connected together, the source electrode of M76 meets VDD, and the source electrode of M32 and M33 meets VDD, and their drain electrode connects the source electrode of M26 and M27 respectively, the drain electrode of M27 meets output port VON, and be connected with one end of resistance R12 with the drain electrode of M37, the other end of R12 is connected with the grid of M70, and source electrode and the drain electrode of M70 link together, the source electrode of M37 is connected with the drain electrode of M36, the source electrode of M36 meets GND, and the drain electrode of M26 meets the output port O of RES1, and with the drain electrode of M34, the source electrode of M38, the drain electrode of M35 is connected, the source electrode of M34 and M35 meets GND, the source electrode of M65 and M66 meets VDD, and the drain electrode of M65 connects the source electrode of M67 and M69, and the drain electrode of M66 connects the source electrode of M68 and M71, the drain electrode of M67 is connected with the drain electrode of M71, and be connected with drain electrode with the grid of M72, the source electrode of M72 and M73 meets GND, and the grid of M67 meets VOP, the grid of M71 meets VON, and B<2:0> connects the B<2:0> port of RES1.The substrate of M67, M69, M68, M71, M11, M38 is connected respectively at their source electrode, and the substrate of remaining pmos2v all meets VDD, and nmos2v meets SUB, and VSS meets GND.
Figure 17 shows that electric resistance array RES1 and logic schematic diagram thereof.Input digital controlled signal B<2>, B<1>, B<0>, first by 3 line-8 line encoders, produce the coding control signal S1 of 8 kinds of states, S2, S3, S4, S5, S6, S7, S8, its state relation provides in the drawings.Just can resistance value size between control input end A and output B by cut-offfing of these 8 control signals.Its breaker in middle adopts NMOS tube to realize.
Electric resistance array RES1 specifically can adopt following frame mode:
This array comprises one by 6 inverters (its structure is identical with the inverter in biasing circuit), 8 three value and gates, 3-8 encoder, the resistance R0 of one two input or door and two three inputs or door formation, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37; Type is the transistor M0 of nmos2v, M1, M2, M3, M4, M5, M6, M7.
Input signal B<2:0> exports S1 through a common 3-8 encoder, S2, S3, S4, S5, S6, S7, S8 eight control signals, S1, S2, S3, S4, S5, S6, S7, S8 is connected respectively to M0, M1, M2, M3, M4, M5, M6, the grid of M7, the source electrode of M0 connects one end of R1 and R2, one end of another termination R0 of R1 and R2, another termination input port I of R0, the drain electrode of M0 connects one end of R4 and R5, one end of another termination R3 of R4 and R5, another termination output port O of R3, the source electrode of M1 connects one end of R9 and R8, the other end of R9 with R8 is connected with one end of R6 with R7 respectively, another termination port I of R6 and R7, the drain electrode of M1 connects one end of R11 and R10, the other end of R11 and R10 connects respectively at R12 and R13, another termination port O of R12 and R13, the source electrode of M2 meets R15, another termination R14 of R15, the other end of R14 connects with I, the drain electrode of M2 meets R16, another termination R17 of R16, the other end of R17 is connected with B, the source electrode of M3 meets R18, another termination R19 of R218, another termination A of R19, the drain electrode of M3 meets R21, another termination R21 of R21, the other end of R21 is connected with O, the source electrode of M4 meets R23, another termination R22 of R23, the other end of R22 connects with I, the drain electrode of M4 meets R24, another termination R25 of R24, the other end of R25 is connected with O, the source electrode of M5 meets R26, the other end of R26 connects with I, the drain electrode of M5 meets R27, the other end of R27 is connected with B, the source electrode of M6 connects one end of R29 and R28, another termination input port I of R29 and R28, the drain electrode of M6 connects one end of R30 and R31, another termination output port of R30 and R31 O, the source electrode of M7 meets R34, another termination R33 of R234, another termination R32 of R33, another termination I of R32, the drain electrode of M7 meets R35, another termination R36 of R235, another termination R37 of R35, another termination I of R37, VSS meets GND, M0, M1, M2, M3, M4, M5, M6, the substrate of M7 meets SUB.
The present invention can be applied in GPS and Big Dipper radio-frequency transmitter, adopts 0.18 micron of germanium silicon technology design to produce, and tests successfully.
Claims (8)
1. the variable gain amplifier in a radiofrequency signal transceiver chip, it is characterized in that: comprise at least one low triad variable gain amplifying unit, at least one high two binary system variable gain amplifying unit, for providing the biasing circuit of enable signal with identical tail current to low triad variable gain amplifying unit, high two binary system variable gain amplifying units; Orthogonal two paths of signals exports successively after low triad variable gain amplifying unit and high two binary system variable gain amplifying units carry out variable gain amplification; Or orthogonal two paths of signals exports successively after high two binary system variable gain amplifying units and low triad variable gain amplifying unit carry out variable gain amplification.
2. the variable gain amplifier in radiofrequency signal transceiver chip according to claim 1, it is characterized in that: if described variable gain amplifying unit be two and two or more time, cascade between multiple variable gain amplifying units of low triad, cascade between high two binary multiple variable gain amplifying units.
3. the variable gain amplifier in radiofrequency signal transceiver chip according to claim 1, is characterized in that: described low triad variable gain amplifying unit and high two binary system variable gain amplifying units are the variable gain amplifier adopting ohmic load as trans-impedance amplifier.
4. according to the variable gain amplifier in the arbitrary described radiofrequency signal transceiver chip of claims 1 to 3, it is characterized in that: described biasing circuit comprises and door AND2X2, NMOS tube (M3, M17), two inverter INVX2, enable signal EN and mode select signal MODE is first by producing signal ENN with door AND2X2, signal ENN receives the grid of NMOS tube M17, enable signal EN and mode select signal MODE produces signal ENB by inverter INVX2 again, and signal ENB receives the grid of NMOS tube M3; Under the effect that enable signal EN and mode select signal MODE opens, and signal EN, signal MODE, signal ENN are when being high level, first input signal IB25 sends into IB, the digital controlled signal BI<2:0> of input is first by two inverter INVX2, and then the output signal IB2 of biasing circuit is controlled together with input IB25 signal, IB1, IB0.
5. the variable gain amplifier in radiofrequency signal transceiver chip according to claim 1, is characterized in that: described high two binary system variable gain amplifying units comprise inverter INVX2, NMOS tube (M0, M4, M21, M74), PMOS (M13, M17, M80, M81) and electric resistance array module RES2, enable signal EN produces signal BENB through inverter INVX2, and signal BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in high two binary system variable gain amplifying units, BENB produces signal BEN through an inverter again, and signal BEN receives the grid of NMOS tube M4, input digital controlled signal B<4>, the colleague of B<3> in input signal port B<4> and B<3> of electric resistance array RES2 delivering to VGA2, input digital controlled signal B<4>, B<3> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M81, signal S2 delivers to the grid of PMOS M13 and M80, an electric resistance array module RES2 is comprised in high two binary system variable gain amplifying units, the input A port of electric resistance array module RES2 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M74, by regulating the resistance size of RES2 input signal B<4> and B<3> control RES2, and then control the gain size of high two binary system variable gain amplifying units.
6. the variable gain amplifier in radiofrequency signal transceiver chip according to claim 5, it is characterized in that: the input digital controlled signal B<4> of described electric resistance array module RES2, B<3> is first by 2 line-4 line encoders, produce the coding control signal S1 of 4 kinds of states, S2, S3, S4, by coding control signal S1, S2, the resistance value size of cut-offfing between control input end A and output B of S3, S4.
7., according to the variable gain amplifier in the arbitrary described radiofrequency signal transceiver chip of claims 1 to 3, it is characterized in that: described low triad variable gain amplifying unit comprises inverter INVX2, NMOS tube (M0, M4), PMOS (M13, M17, M21, M26, M43, M44) NAND gate NAND2X1, NOR gate NOR2X1, electric resistance array module RES1; Enable signal EN produces signal BENB through inverter INVX2, and signal BENB receives the grid of NMOS tube M0, and when BENB is high level, bias current IB25 is input in low triad variable gain amplifying unit; Signal BENB produces signal BEN through inverter again, and signal BEN receives the grid of NMOS tube M4; Input digital controlled signal B<2>, B<1> is by a NAND gate NAND2X1 and NOR gate NOR2X1, produce signal S1 and S2 respectively, signal S1 delivers to the grid of PMOS M17 and M44, and signal S2 delivers to the grid of PMOS M13 and M43; The input A port of described electric resistance array module RES1 is connected in the drain electrode of PMOS M21, exporting B port is connected in the drain electrode of PMOS M26, digital controlled signal B<2> is inputted by regulating RES1, B<1>, B<0> just can the resistance size of control RES1, and then controls the gain size of low triad variable gain amplifying unit.
8. the variable gain amplifier in radiofrequency signal transceiver chip according to claim 7, it is characterized in that: the input digital controlled signal B<2> of described electric resistance array module RES1, B<1>, B<0> is first by 3 line-8 line encoders, produce the coding control signal S1 of 8 kinds of states, S2, S3, S4, S5, S6, S7, S8, by coding control signal S1, S2, S3, S4, S5, S6, S7, the resistance value size of cut-offfing between control input end A and output B of S8.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048982A (en) * | 2015-08-10 | 2015-11-11 | 西安邮电大学 | Variable gain amplifier in radio-frequency signal transceiver chip |
| CN109150113A (en) * | 2018-08-23 | 2019-01-04 | 西安邮电大学 | A kind of image-reject mixer in radiofrequency signal transceiver chip |
| CN109150116A (en) * | 2018-08-09 | 2019-01-04 | 西安邮电大学 | A kind of low-noise amplifier in video receiver chip |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105048982A (en) * | 2015-08-10 | 2015-11-11 | 西安邮电大学 | Variable gain amplifier in radio-frequency signal transceiver chip |
| CN105048982B (en) * | 2015-08-10 | 2018-09-07 | 西安邮电大学 | Variable gain amplifier in radiofrequency signal transceiver chip |
| CN109150116A (en) * | 2018-08-09 | 2019-01-04 | 西安邮电大学 | A kind of low-noise amplifier in video receiver chip |
| CN109150113A (en) * | 2018-08-23 | 2019-01-04 | 西安邮电大学 | A kind of image-reject mixer in radiofrequency signal transceiver chip |
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