CN204990301U - 8 high -speed synchronizing data collection system of passageway - Google Patents

Abstract

The utility model relates to a 8 high -speed synchronizing data collection system of passageway belongs to civil engineering field, is applied to structure safety and health monitoring trade. The input interface is connected with programmable amplifier, and programmable amplifier is connected with the anti -aliasing filter ware, and the anti -aliasing filter ware is connected with 24 independent adc, and 24 independent adc are connected with the FPGA controller, the quick -witted interface of mcASP follow in the FPGA controller is connected with the mcASP host interface among the flush bonding processor, EDMA module in the FPGA controller is connected with the mcASP host interface, flush bonding processor is connected with programmable amplifier through the IO expander, flush bonding processor is connected with data cache module, gigabit ethernet interface respectively.

Description

A kind of 8 passage high-speed synchronous data acquiring systems

Technical field

The utility model relates to a kind of 8 passage high-speed synchronous data acquiring systems, belongs to field of civil engineering, is applied to structural safety health monitoring industry.

Background technology

The framework that current high-speed synchronous data acquiring system adopts is FPGA+ flush bonding processor framework, SPI interface is adopted between FPGA and flush bonding processor, most high-speed synchronous data acquiring system adopts conventional SPI interface, because the upper limit by SPI interface transmission speed affects, therefore the speed of Channels Synchronous Data Acquisition System be restricted.Flush bonding processor adopts interrupt mode when data streams in addition, and the kernel resources occupying flush bonding processor makes the efficiency such as data-handling efficiency, digital filtering, data transmission extremely low.

Utility model content

For above-mentioned problem, the utility model patent object is to provide a kind of 8 passage high-speed synchronous data acquiring systems, thus solve the transmission bottleneck realizing high-speed data acquisition, McASP interface is used to substitute SPI interface, flush bonding processor utilizes EMDA technology the data of McASP interface directly to be carried out buffering and the process of data by flush bonding processor kernel backstage simultaneously, do not take the resource of processor, make processor can process other tasks more efficiently.Whole system is to the processing speed significant increase of data, and whole data acquisition process Procedure embedding formula processor cores stays out of, can the data processing speed of overall improved system.

Note: enhancement mode direct memory access (EDMA), EnhancedDirectMemoryAccess is the important technology for fast data exchange in high-speed data process, has the ability of the backstage bulk data transfer independent of CPU;

McASP: be called multiple channel audio access interface, this is a kind of general audio interface incoming interface.What adopt is time-multiplexed data-stream form.

To achieve these goals, the utility model adopts following technical scheme:

A kind of 8 passage high-speed synchronous data acquiring systems, it comprises input interface, programmable amplifier, frequency overlapped-resistable filter, independent 24 analog to digital converters, FPGA controller, power management module, McASP from machine interface, McASP host interface, I/O extender, EDMA module, flush bonding processor, data cache module, gigabit ethernet interface;

Input interface is connected with programmable amplifier, and programmable amplifier is connected with frequency overlapped-resistable filter, and frequency overlapped-resistable filter is connected with independent 24 analog to digital converters, and independent 24 analog to digital converters are connected with FPGA controller;

McASP in FPGA controller is connected from machine interface with the McASP host interface flush bonding processor;

EDMA module in FPGA controller is connected with McASP host interface;

Flush bonding processor is connected with programmable amplifier by I/O extender;

Flush bonding processor is connected with data cache module, gigabit ethernet interface respectively.

A kind of 8 passage high-speed synchronous data acquiring methods:

FPGA controller converts the digital interface data of independent 24 analog to digital converters to McASP sequential, and the McASP host interface transferred data to from machine interface by McASP flush bonding processor, McASP host interface again by data directly by EMDA module by data stored in data cache module, taken out by flush bonding processor filtering and a little and after protocol packing through gigabit ethernet interface, data sent.

The signal of input interface amplifies by programmable amplifier.

The signal that programmable amplifier exports by frequency overlapped-resistable filter carries out filtering, ensures signal not aliasing.

The signal of frequency overlapped-resistable filter carries out sampling and converting digital signal to by independent 24 analog to digital converters.

The utility model realizes principle: first system adopts 8 independently analog to digital converter kernel (A/D), 8 independently analog signal processing links (amplify, anti-aliasing filter), for realizing the true synchronous acquisition of 8 passage of system;

FPGA controller is used for logic control and the timing conversion of whole system, as controlled the enlargement factor, the sequential timing conversion of analog to digital converter being become McASP, control I/O extender etc. of programmable amplifier (PGA);

Analog to digital converter sends the data to FPGA by digital interface, FPGA converts data to McASP sequential and sends to flush bonding processor, data are directly deposited to data buffer storage by EMDA by McASP interface by flush bonding processor, and carry out digital filtering to data, take out point, according to work such as protocol packing;

Data after packing send data to PC end by gigabit Ethernet, display data and waveform.

The beneficial effects of the utility model:

The utility model realizes 8 Channel Synchronous data acquisition system (DAS)s of low speed to be increased to 200 ~ 500Ksps from 10 ~ 100Ksps, and the system that achieves is applied from building industry to the gamut of machinery industry, has expanded the applicable industry wide of product.

Accompanying drawing explanation

Fig. 1 is system chart of the present utility model;

Fig. 2 is data flow diagram of the present utility model.

Embodiment

Be described in detail below in conjunction with accompanying drawing 1,2 pairs of the utility model:

A kind of 8 passage high-speed synchronous data acquiring systems, it comprises input interface 1, programmable amplifier 2, frequency overlapped-resistable filter 3, independent 24 analog to digital converters 4, FPGA controller 5, power management module 6, McASP from machine interface 7, McASP host interface 8, I/O extender 9, EDMA module 10, flush bonding processor 11, data cache module 12, gigabit ethernet interface 13;

Input interface 1 is connected with programmable amplifier 2, and programmable amplifier 2 is connected with frequency overlapped-resistable filter 3, and frequency overlapped-resistable filter 3 is connected with independent 24 analog to digital converters 4, and independent 24 analog to digital converters 4 are connected with FPGA controller 5;

McASP in FPGA controller 5 is connected from machine interface 7 with the McASP host interface 8 flush bonding processor 11;

EDMA module 10 in FPGA controller 5 is connected with McASP host interface 8;

Flush bonding processor 11 is connected with programmable amplifier 2 by I/O extender 9;

Flush bonding processor 11 is connected with data cache module 12, gigabit ethernet interface 13 respectively.

A kind of 8 passage high-speed synchronous data acquiring methods:

FPGA controller 5 converts the digital interface data of independent 24 analog to digital converters 4 to McASP sequential, and the McASP host interface 8 transferred data to from machine interface 7 by McASP flush bonding processor 11, McASP host interface 8 again by data directly by EMDA module 10 by data stored in data cache module 12, take out a little by flush bonding processor 11 filtering and through gigabit ethernet interface 13, data sent after protocol packing.

The signal of input interface 1 amplifies by programmable amplifier 2.

The signal that programmable amplifier 2 exports by frequency overlapped-resistable filter 3 carries out filtering, ensures signal not aliasing.

The signal of frequency overlapped-resistable filter 3 carries out sampling and converting digital signal to by independent 24 analog to digital converters 4.

Illustrate:

The programmable amplifier (PGA) of configurable gain has 1,10,100,1,000 four gears, for measuring the signal type of Different Dynamic scope; Signal, after tentatively amplifying process, enters frequency overlapped-resistable filter, and the design of frequency overlapped-resistable filter will meet the minimum requirements of sampling thheorem, according to the design that sampling rate selects the cut-off frequecy of passband of suitable frequency overlapped-resistable filter to carry out wave filter; The analog to digital converter of each passage independent kernel is adopted to make the data of 8 passages by real synchronous process; The data converted are connected to FPGA by digital interface, and data are carried out timing conversion by FPGA, convert McASP protocol frame format to, and send to flush bonding processor, and flush bonding processor can adopt the cortex-A8 scheme of current TI company main flow to realize; Data buffer storage implementation does the circular treatment of a Double buffer, ensures the continuity of data; Power management module powers independently to digital circuit, mimic channel, ensures the pure of marking current loop and not by the impact of digital circuit.I/O extender is the I/O quantity in order to save flush bonding processor, with the I/O extender of an IIC communication mode, I/O quantity is expanded to 16 tunnels, for controlling 4 gears of the programmable amplifier of 8 passages.

Claims (1)

1. 8 passage high-speed synchronous data acquiring systems, is characterized in that: it comprises input interface (1), programmable amplifier (2), frequency overlapped-resistable filter (3), independent 24 analog to digital converters (4), FPGA controller (5), power management module (6), McASP from machine interface (7), McASP host interface (8), I/O extender (9), EDMA module (10), flush bonding processor (11), data cache module (12), gigabit ethernet interface (13);

Input interface (1) is connected with programmable amplifier (2), programmable amplifier (2) is connected with frequency overlapped-resistable filter (3), frequency overlapped-resistable filter (3) is connected with independent 24 analog to digital converters (4), and independent 24 analog to digital converters (4) are connected with FPGA controller (5);

McASP in FPGA controller (5) is connected from machine interface (7) with the McASP host interface (8) flush bonding processor (11);

EDMA module (10) in FPGA controller (5) is connected with McASP host interface (8);

Flush bonding processor (11) is connected with programmable amplifier (2) by I/O extender (9);

Flush bonding processor (11) is connected with data cache module (12), gigabit ethernet interface (13) respectively.