CN204948031U - Electronic installation and class-D amplifier - Google Patents
Electronic installation and class-D amplifier Download PDFInfo
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- CN204948031U CN204948031U CN201520297094.3U CN201520297094U CN204948031U CN 204948031 U CN204948031 U CN 204948031U CN 201520297094 U CN201520297094 U CN 201520297094U CN 204948031 U CN204948031 U CN 204948031U
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Abstract
The disclosure relates to electronic installation and class-D amplifier.Electronic installation comprises: the first and second comparators, and analogue audio frequency input signal is converted to audio frequency square wave, logic chunk, receive the first and second audio frequency square waves from the first and second comparators and generate when the duty ratio of the first audio frequency square wave is greater than the duty ratio of the second audio frequency square wave the first processed audio signal representing difference between first and second audio frequency square wave, the the first processed audio signal had with reference to DC level is generated when the duty ratio of the first audio frequency square wave is less than the duty ratio of the second audio frequency square wave, the second processed audio signal of difference between expression second and first audio frequency square wave is generated when the duty ratio of the second audio frequency square wave is greater than the duty ratio of the first audio frequency square wave, and generate when the duty ratio of the second audio frequency square wave is less than the duty ratio of the first audio frequency square wave the second processed audio signal had with reference to DC level, and first and second output stages, generate the first and second audio output signals.
Description
Technical field
The disclosure relates to the technical field of D audio frequency amplifier, and relates more specifically to a kind of class-D amplifier design compared with conventional class D amplifiers with the EMI of minimizing.
Background technology
The portable electron device of such as smart phone and panel computer and so on is subject to client and welcomes.These portable electron devices can plays back audio, and therefore have employed audio frequency amplifier.Because these portable electron devices are battery-powered, reducing energy consumption is business demand, and can be applicable to these electronic installations potentially than the more efficient D audio frequency amplifier of AB class audio amplifier.
Class-D amplifier is that wherein amplifying device (being generally MOSFET) operation is as electronic switch instead of the electron-amplifier as the linear gain device in other amplifiers.Analog signal to be amplified is converted to the sequence of square pulse before being in application to amplifying device.Because signal to be amplified is the sequence of constant amplitude pulse, amplifying device switches back and forth fast between conduction and non-conductive state.After zooming, output pulse train can by by its through passive low ventilating filter converted back into analog signal.
As mentioned above, the advantage of class-D amplifier is that it can be more efficient than other amplifiers, this is because less power is distributed in active device as heat.But the switching of active device causes the EMI increased, its in smart phone and panel computer special undesirably.Thus, the improvement class-D amplifier reducing EMI is commercial needs.
Utility model content
There is provided this utility model content part to propose the selection to the concept further described in following detail specifications.This utility model content part is also not intended to the key or the essential feature that identify claimed theme, also and the scope be not intended to for the claimed theme of auxiliary restriction.
According to an aspect of the present disclosure, a kind of electronic installation is provided, comprises: the first comparator and the second comparator, be configured for and the first analogue audio frequency input signal and the second analogue audio frequency input signal are converted to the first audio frequency square wave and the second audio frequency square wave respectively, logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and be configured for: generate when the duty ratio of described first audio frequency square wave is greater than the duty ratio of described second audio frequency square wave the first processed audio signal representing difference between described first audio frequency square wave and described second audio frequency square wave, the described first processed audio signal had with reference to DC level is generated when the duty ratio of described first audio frequency square wave is less than the duty ratio of described second audio frequency square wave, the the second processed audio signal representing difference between described second audio frequency square wave and described first audio frequency square wave is generated when the duty ratio of described second audio frequency square wave is greater than the duty ratio of described first audio frequency square wave, and the described second processed audio signal with described reference DC level is generated when the duty ratio of described second audio frequency square wave is less than the duty ratio of described first audio frequency square wave, and first output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
Alternatively, described first comparator arrangement is used for, by described first analogue audio frequency input signal and triangular wave being compared, described first analogue audio frequency input signal is converted to the first audio frequency square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and triangular wave being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
Alternatively, described first comparator arrangement is used for, by described first analogue audio frequency input signal and sawtooth waveforms being compared, described first analogue audio frequency input signal is converted to the first audio frequency square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and described sawtooth waveforms being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
Alternatively, described logic chunk comprises: the first inverter and the second inverter, is configured for and receives described first audio frequency square wave and described second audio frequency square wave and export the anti-phase of described first audio frequency square wave and described second audio frequency square wave; First and door, be configured for and generate the described first processed audio signal with described first logic level based on the anti-phase of the described second audio frequency square wave with the first logic level and described first audio frequency square wave; And second and door, be configured for and generate the described second processed audio signal with described first logic level based on the anti-phase of the described first audio frequency square wave with described first logic level and described second audio frequency square wave.
Alternatively, described first output stage comprises: the first amplifier, be configured for receive described first processed audio signal and generate first and amplify audio signal, first PMOS transistor, there is drain electrode, be coupled to the source electrode of supply voltage, and for receiving the grid that described first has amplified audio signal, and first nmos pass transistor, there is the source electrode being coupled to ground connection, be coupled to the drain electrode of described first PMOS transistor drain electrode, and for receiving the grid that described first has amplified audio signal, wherein said first PMOS transistor cooperates to generate described first audio output signal with described first nmos pass transistor, and wherein said second output stage comprises: the second amplifier, be configured for receive described second processed audio signal and generate second and amplify audio signal, second PMOS transistor, there is drain electrode, be coupled to the source electrode of supply voltage, and for receiving the grid that described second has amplified audio signal, and second nmos pass transistor, there is the source electrode being coupled to ground connection, be coupled to the drain electrode of described second PMOS transistor drain electrode, and for receiving the grid that described second has amplified audio signal, wherein said second PMOS transistor and described second nmos pass transistor cooperation are to generate described second audio output signal.
Alternatively, this electronic installation comprises load further, is coupled for receiving described first audio output signal and described second audio output signal.
Alternatively, described second analogue audio frequency input signal is the anti-phase of described first analogue audio frequency input signal; And wherein said first analogue audio frequency input signal and described second analogue audio frequency input signal are differential signals.
According to another aspect of the present disclosure, provide a kind of class-D amplifier, comprise: signal transacting chunk, be configured for: generate when the duty ratio of the first differential signal is greater than the duty ratio of the second differential signal the first processed signal representing difference between described first differential signal and described second differential signal, described first processed signal represented with reference to DC level is generated when the duty ratio of described first differential signal is less than the duty ratio of described second differential signal, the second processed signal representing difference between described second differential signal and described first differential signal is generated when the duty ratio of described second differential signal is greater than the duty ratio of described first differential signal, and described second processed signal representing described reference DC level is generated when the duty ratio of described second differential signal is less than the duty ratio of described first differential signal.
Alternatively, class-D amplifier comprises the first output stage and the second output stage further, is coupled to described signal transacting chunk and is configured for generate the first output signal and the second output signal respectively based on described first processed signal and described second processed signal.
Alternatively, described signal transacting chunk comprises: the first inverter and the second inverter, is configured for and receives described first differential signal and described second differential signal and export the anti-phase of described first differential signal and described second differential signal; First and door, be configured for and generate described first processed signal with described first logic level based on the anti-phase of described second differential signal with the first logic level and described first differential signal; And second and door, be configured for and generate described second processed signal with described first logic level based on the anti-phase of described first differential signal with described first logic level and described second differential signal.
Alternatively, described second differential signal is the complement code of described first differential signal.
According to another aspect of the present disclosure, a kind of electronic installation is provided, comprises: the first comparator and the second comparator, be configured for and the first analogue audio frequency input signal and the second analogue audio frequency input signal are converted to the first audio frequency square wave and the second audio frequency square wave respectively; logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and be configured for: generate the first processed audio signal with following pulse when the duty ratio of described first audio frequency square wave is greater than the duty ratio of described second audio frequency square wave, this pulse represents the twice from the rising edge of described first audio frequency square wave to the time cycle of the rising edge of described second audio frequency square wave, the described first processed audio signal had with reference to DC level is generated when the duty ratio of described first audio frequency square wave is less than the duty ratio of described second audio frequency square wave, the second processed audio signal with following pulse is generated when the duty ratio of described second audio frequency square wave is greater than the duty ratio of described first audio frequency square wave, this pulse represents the twice from the rising edge of described second audio frequency square wave to the time cycle of the rising edge of described first audio frequency square wave, and the described second processed audio signal with described reference DC level is generated when the duty ratio of described second audio frequency square wave is less than the duty ratio of described first audio frequency square wave, and first output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
Alternatively, described first comparator arrangement is used for, by described first analogue audio frequency input signal and triangular wave being compared, described first analogue audio frequency input signal is converted to the first square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and triangular wave being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
Alternatively, described first output stage comprises: the first amplifier, be configured for receive described first processed audio signal and generate first and amplify audio signal, first PMOS transistor, there is drain electrode, be coupled to the source electrode of supply voltage, and for receiving the grid that described first has amplified audio signal, and first nmos pass transistor, there is the source electrode being coupled to ground connection, be coupled to the drain electrode of described first PMOS transistor drain electrode, and for receiving the grid that described first has amplified audio signal, wherein said first PMOS transistor and described first nmos pass transistor cooperation are for generating described first audio output signal, and wherein said second output stage comprises: the second amplifier, be configured for receive described second processed audio signal and generate second and amplify audio signal, second PMOS transistor, there is drain electrode, be coupled to the source electrode of supply voltage, and for receiving the grid that described second has amplified audio signal, and second nmos pass transistor, there is the source electrode being coupled to ground connection, be coupled to the drain electrode of described second PMOS transistor drain electrode, and for receiving the grid that described second has amplified audio signal, wherein said second PMOS transistor and described second nmos pass transistor cooperation are for generating described second audio output signal.
According to another aspect of the present disclosure, a kind of electronic installation is provided, comprise: the first comparator and the second comparator, be configured for, by the first analogue audio frequency input signal and the second analogue audio frequency input signal being compared with first waveform and the second waveform with the reference cycle, described first analogue audio frequency input signal and described second analogue audio frequency input signal be converted to the first audio frequency square wave and the second audio frequency square wave, described first analogue audio frequency input signal and described second analogue audio frequency input signal are all changed twice during the described reference cycle; Logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and be configured for and generate the first processed audio signal and the second processed audio signal based on described first audio frequency square wave and described second audio frequency square wave, in described first processed audio signal and described second processed audio signal only one change twice during the described reference cycle; First output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
By using according to technical scheme of the present disclosure, the EMI of electronic installation and class-D amplifier can be reduced.
Accompanying drawing explanation
Fig. 1 is the schematic diagram according to class-D amplifier of the present disclosure.
Fig. 2 is that wherein signal generator is the sequential chart of the class-D amplifier of Fig. 1 in the operation of saw-toothed wave generator.
Fig. 3 is that wherein signal generator is the schematic diagram of the embodiment of the logic chunk of the class-D amplifier of Fig. 1 of saw-toothed wave generator.
Fig. 4 is that wherein signal generator is the flow chart of the operation of the class-D amplifier of Fig. 1 of triangular-wave generator.
Fig. 5 is that wherein signal generator is the sequential chart of the class-D amplifier of Fig. 1 in the operation of triangular-wave generator.
Embodiment
Below one or more embodiment will be described.Embodiment described in these is only the example of the execution mode technology as being only defined by the following claims.Extraly, in order to provide the description of focusing, the uncorrelated features of true execution mode can not be described in the description.
With reference to Fig. 1, the class-D amplifier 100 with bridging load 160 is described now.First will describe the structure of class-D amplifier 100, and its operation will be described subsequently.
Class-D amplifier 100 comprises the first analogue audio frequency input channel 110a and the second analogue audio frequency input channel 110b.First and second analogue audio frequency input channel 110a, 110b include identical fully-differential amplifier 112.Fully-differential amplifier 112 comprises input resistor Rin and feedback resistor R1, and it is provided with gain.The output of fully-differential amplifier 112 feeds back to another fully-differential amplifier 114, and it has input resistor R2 and feedback condenser C.The noninverting output of fully-differential amplifier 114 is fed to the noninverting input of comparator 120a, and the anti-phase output of fully-differential amplifier 114 is fed to the noninverting input of comparator 120b.Signal generator 130 is coupled to the inverting input of comparator 120a and comparator 120b.
Logic chunk 140 is delivered in the output of comparator 120a and comparator 120b, and it has the output being fed to output stage 150a and output stage 150b.Output stage 150a comprises driver 152a, has the input being coupled to logic chunk 140 output.Output stage 150a also comprises the first PMOS transistor P1 and the first nmos pass transistor N1.First PMOS transistor P1 has the source electrode being coupled to power Vcc, and is coupled to the grid of the first output of driver 152a.Diode D1 is coupling between the source electrode of the first PMOS transistor P1 and drain electrode.First nmos pass transistor N1 has the source electrode being coupled to the first PMOS transistor P1 drain electrode, is coupled to the drain electrode of ground connection GND, and is coupled to the grid of the second output of driver 152a.Diode D2 is coupling between the source electrode of the first nmos pass transistor N1 and drain electrode.
Output stage 150b comprises driver 152b, has the input being coupled to logic chunk 140 output.Output stage 150b also comprises the second PMOS transistor P2 and the second nmos pass transistor N2.Second PMOS transistor P2 has the source electrode being coupled to power Vcc, and is coupled to the grid of driver 150b first output.Diode D3 is coupling between the source electrode of the second PMOS transistor P2 and drain electrode.Second nmos pass transistor N2 has the source electrode being coupled to the second PMOS transistor P2 drain electrode, is coupled to the drain electrode of ground connection GND, and is coupled to the grid of driver 152b second output.Diode D4 is coupling between the source electrode of the second nmos pass transistor N2 and drain electrode.
Load 160 has the first input end of the source electrode of drain electrode and the first nmos pass transistor N1 being coupled to the first PMOS transistor P1, and has second input of source electrode of drain electrode and the second nmos pass transistor N2 being coupled to the second PMOS transistor P2.Resistor Rfb is coupling between the input of load 160 and fully-differential amplifier 114.Load 160 such as can comprise analog speakers.
With reference to Fig. 3, now by the structure of description logic chunk 140.Logic chunk 140 comprises the first inverter 202a, and it has the input of the output CMPp being coupled to comparator 120b and is coupled to the output with the first input end of door 204a.With door 204a, there is the second input being coupled to comparator 120a output, and be coupled to the output Vp of the first output stage 150a.
Logic chunk 140 also comprises the second inverter 202b, and it has the input of the output CMPn being coupled to comparator 120a, and is coupled to the output with door 204b first input end.With door 204b, there is the second input being coupled to comparator 120b output, and be coupled to the output Vn of the second output stage 150b.
The operation of class-D amplifier 100 is described now with reference to Fig. 1-Fig. 3.The input of fully-differential amplifier 112 receives the first and second analogue audio frequency input signals respectively.Fully-differential amplifier 112 removes the common-mode noise in the first and second analogue audio frequency input signals, and exports as the first and second differential signals the first and second analogue audio frequency input signals removing common-mode noise to offset for removing unwanted DC from the first and second analogue audio frequency input signals fully-differential amplifier 114.In some applications, the first and second analogue audio frequency input signals can be discrete single input signal and not be differential signals, as is known in the art.
First analogue audio frequency output signal Vdn delivers to comparator 120a from fully-differential amplifier 114 subsequently, and the first analogue audio frequency input signal and the sawtooth waveforms generated by signal source or waveform generator 130 compare by it.This causes generating the first audio frequency square wave CMPp, has the duty ratio with the amplitude scaled versions of the first analogue audio frequency input signal.First analogue audio frequency input signal is shown in Figure 2 for after label SWATOOTH sawtooth waveforms with the waveform to be generated by waveform generator 130, and after the first audio frequency square wave is shown in label CMPP.
Similar, the second audio output signal Vdp is fed to comparator 120b from fully-differential amplifier 114, and the second analogue audio frequency input signal and the triangular wave generated by waveform generator 130 or sawtooth waveforms also compare by it.This also causes generating the second audio frequency square wave CMPn, and it has the duty ratio with the amplitude scaled versions of the second analogue audio frequency input signal.Second audio frequency square wave is shown in Figure 2 on label CMPN side.
Logic chunk 140 receives the first audio frequency square wave and generates the first processed audio signal Vp by it.Logic chunk 140 generates the first processed audio signal Vp by itself and door 204a to the anti-phase actuating logic of the first audio frequency square wave and the second audio frequency square wave and operation.When the duty ratio of the first audio frequency square wave is greater than the duty ratio of the second audio frequency square wave (Reference numeral 300), the first processed audio signal represents the difference between the first audio frequency square wave and the second audio frequency square wave thus.When the duty ratio of the first audio frequency square wave is less than the duty ratio of the second audio frequency square wave (Reference numeral 302), the first processed audio signal represents thus with reference to DC level or common-mode voltage.
Logic chunk 140 also generates the second processed audio signal Vn by the second audio frequency square wave.Logic chunk 140 generates the second processed audio signal Vn by itself and door 204b to the anti-phase of the first audio frequency square wave and the second audio frequency square wave actuating logic and operation.When the duty ratio of the second audio frequency square wave is greater than the duty ratio of the first audio frequency square wave (Reference numeral 302), the second processed audio signal represents the difference between the second audio frequency square wave and the first audio frequency square wave thus.When the duty ratio of the second audio frequency square wave is less than the duty ratio of the first audio frequency square wave (Reference numeral 300), the second processed audio signal Vn represents thus with reference to DC level or common-mode voltage.
As shown in by the processed audio signal of observation first and the second processed audio signal Vp, Vn, first processed audio signal and the second processed audio signal are not high simultaneously, and only an audio signal is high during the single cycle of triangular wave or sawtooth waveforms, and this audio signal be once only height during this single cycle.Therefore, switch at single period in cycle P1 and N2, or switch at this single period in cycle P2 and N2, but not two pairings of transistor are all like this.
Adopt conventional class D amplifiers, the first processed audio signal and the second processed audio signal can be high simultaneously.Therefore, in conventional class D amplifiers, transistor P1, N2 and P2, N2 all switch twice by during the single cycle of triangular wave or sawtooth waveforms.Therefore class-D amplifier described herein decreases 50% amount of switched compared with traditional design, thus causes the EMI that greatly reduces.
Driver 152a receives the first processed audio signal and is amplified.When the first processed audio signal Vp is in logic height, the first nmos pass transistor N2 turns off, and the first PMOS transistor P1 conducting and be generated as the first high audio output signal OUTp.When the first processed audio signal Vp is in logic low, the first PMOS transistor P1 turns off, and the first nmos pass transistor N1 conducting and being dragged down by the first audio output signal OUTp.
Driver 152b receives the second processed audio signal and driving power MOS device P2, N2 equally.When the second processed audio signal Vn is in logic height, the second nmos pass transistor N2 turns off, and the second PMOS transistor P1 conducting and be generated as the second high audio output signal OUTn.When the second processed audio signal Vn is in logic low, the second PMOS transistor P2 turns off, and the second nmos pass transistor N2 conducting and being dragged down by the second audio output signal OUTn.
The signal of load place being labeled as LOAD in Fig. 2 is drawn high by the first audio output signal OUTp.On the other hand, the load place signal being designated as LOAD in Fig. 2 draws as negative by the second audio output signal OUTn.Difference between load place signal indication first audio output signal and second audio output signal OUTp, OUTn.Therefore, if the first audio output signal and second audio output signal OUTp, OUTn are high and lack overlapping conversion as conventional class D amplifiers is possible simultaneously, then load place signal will change four times during cycle preset time.But as shown in Figure 2, as the result of the operation performed by logic chunk 140, the first audio output signal and second audio output signal OUTp, OUTn can not be high simultaneously.Therefore, load place signal only will change twice during identical cycle preset time, with in legacy system four times contrary.Load place signal number of transitions reduces by half by this.
Be appreciated that waveform generator 130 can generate triangular wave and substitute sawtooth waveforms.This can cause not had by CMPp and CMPn of comparator 120a and 120b output changing simultaneously.In this case, logic chunk 140 generates Vp and Vn as described now with reference to the flow chart 300 of Fig. 4-Fig. 5.
Because differential amplifier 112, Vdp and Vdn are fully differential output signals, and triangle wave frequency is higher than the frequency of analogue audio frequency input signal.Therefore, the width of P1 equals the width of P2, and the width of P3 equals the width of P4 in Fig. 5.
Logic chunk 140 monitoring CMP p and CMPn is to sense the first rising edge (step 302).If CMPp had rising edge (step 304a) before CMPn, then logic chunk 140 samples (step 306a) from the rising edge of CMPp to the rising edge of CMPn.This illustrates in the sequential chart of Fig. 5, and this time cycle is called P1.Logic chunk 140 starts to export the Vp (step 308a) for high in sampling beginning, and Vp is changed into low (step 310a) at the time elapse place of 2*P1, also as shown in Figure 5.Logic chunk 140 is back to monitoring CMP p and CMPn (step 302) subsequently.Load finally receives output signal for 2*P1=P1+P2=CMPP-CMPN.
If CMPn had the first rising edge (step 304b) before CMPp, then logic chunk 140 samples (step 306b) from the rising edge of CMPn to the rising edge of CMPp.Logic chunk 140 starts in sampling beginning to export Vn for high (step 308b), and is after this changed into low (step 310b) by Vn at the time elapse equaling the time span twice from CMPn rising edge to CMPp rising edge.Logic chunk 140 is back to monitoring CMP p and CMPn (step 302) subsequently.
When CMPp and CMPn rises simultaneously wherein (step 305), logic chunk 140 is held fire, Vp and Vn is left low (step 307), and continues monitoring CMP p and CMPn (step 302).
Although describe the disclosure with reference to finite population embodiment, the those skilled in the art being subject to disclosure instruction will know other embodiments can predicted and not depart from as said disclosure scope.Therefore, the scope of the present disclosure should only have claims to limit.
Claims (15)
1. an electronic installation, is characterized in that, comprising:
First comparator and the second comparator, be configured for and the first analogue audio frequency input signal and the second analogue audio frequency input signal be converted to the first audio frequency square wave and the second audio frequency square wave respectively;
Logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and is configured for:
The the first processed audio signal representing difference between described first audio frequency square wave and described second audio frequency square wave is generated when the duty ratio of described first audio frequency square wave is greater than the duty ratio of described second audio frequency square wave,
The described first processed audio signal had with reference to DC level is generated when the duty ratio of described first audio frequency square wave is less than the duty ratio of described second audio frequency square wave,
The the second processed audio signal representing difference between described second audio frequency square wave and described first audio frequency square wave is generated when the duty ratio of described second audio frequency square wave is greater than the duty ratio of described first audio frequency square wave, and
Generate when the duty ratio of described second audio frequency square wave is less than the duty ratio of described first audio frequency square wave and there is the described described second processed audio signal with reference to DC level; And
First output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
2. electronic installation according to claim 1, is characterized in that, described first comparator arrangement is used for, by described first analogue audio frequency input signal and triangular wave being compared, described first analogue audio frequency input signal is converted to the first audio frequency square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and triangular wave being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
3. electronic installation according to claim 1, is characterized in that, described first comparator arrangement is used for, by described first analogue audio frequency input signal and sawtooth waveforms being compared, described first analogue audio frequency input signal is converted to the first audio frequency square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and described sawtooth waveforms being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
4. electronic installation according to claim 3, is characterized in that, described logic chunk comprises:
First inverter and the second inverter, be configured for and receive described first audio frequency square wave and described second audio frequency square wave and export the anti-phase of described first audio frequency square wave and described second audio frequency square wave;
First and door, be configured for and generate the described first processed audio signal with described first logic level based on the anti-phase of the described second audio frequency square wave with the first logic level and described first audio frequency square wave; And
Second and door, be configured for and generate the described second processed audio signal with described first logic level based on the anti-phase of the described first audio frequency square wave with described first logic level and described second audio frequency square wave.
5. electronic installation according to claim 1, is characterized in that, described first output stage comprises:
First amplifier, is configured for receive described first processed audio signal and generate first and amplifies audio signal,
First PMOS transistor, having drain electrode, being coupled to the source electrode of supply voltage and for receiving the grid that described first has amplified audio signal, and
First nmos pass transistor, have be coupled to ground connection source electrode, be coupled to described first PMOS transistor drain electrode drain electrode and for receiving the grid that described first has amplified audio signal,
Wherein said first PMOS transistor cooperates to generate described first audio output signal with described first nmos pass transistor;
And wherein said second output stage comprises:
Second amplifier, is configured for receive described second processed audio signal and generate second and amplifies audio signal,
Second PMOS transistor, having drain electrode, being coupled to the source electrode of supply voltage and for receiving the grid that described second has amplified audio signal, and
Second nmos pass transistor, have be coupled to ground connection source electrode, be coupled to described second PMOS transistor drain electrode drain electrode and for receiving the grid that described second has amplified audio signal,
Wherein said second PMOS transistor and described second nmos pass transistor cooperation are to generate described second audio output signal.
6. electronic installation according to claim 5, is characterized in that, comprises load further, is coupled for receiving described first audio output signal and described second audio output signal.
7. electronic installation according to claim 1, is characterized in that, described second analogue audio frequency input signal is the anti-phase of described first analogue audio frequency input signal; And wherein said first analogue audio frequency input signal and described second analogue audio frequency input signal are differential signals.
8. a class-D amplifier, is characterized in that, comprising:
Signal transacting chunk, is configured for:
The first processed signal representing difference between described first differential signal and described second differential signal is generated when the duty ratio of the first differential signal is greater than the duty ratio of the second differential signal,
Described first processed signal represented with reference to DC level is generated when the duty ratio of described first differential signal is less than the duty ratio of described second differential signal,
The second processed signal representing difference between described second differential signal and described first differential signal is generated when the duty ratio of described second differential signal is greater than the duty ratio of described first differential signal, and
Generate when the duty ratio of described second differential signal is less than the duty ratio of described first differential signal and represent described described second processed signal with reference to DC level.
9. class-D amplifier according to claim 8, it is characterized in that, comprise the first output stage and the second output stage further, be coupled to described signal transacting chunk and be configured for based on described first processed signal and described second processed signal generate respectively the first output signal and second output signal.
10. class-D amplifier according to claim 8, is characterized in that, described signal transacting chunk comprises:
First inverter and the second inverter, be configured for and receive described first differential signal and described second differential signal and export the anti-phase of described first differential signal and described second differential signal;
First and door, be configured for and generate described first processed signal with described first logic level based on the anti-phase of described second differential signal with the first logic level and described first differential signal; And
Second and door, be configured for and generate described second processed signal with described first logic level based on the anti-phase of described first differential signal with described first logic level and described second differential signal.
11. class-D amplifier according to claim 8, is characterized in that, described second differential signal is the complement code of described first differential signal.
12. 1 kinds of electronic installations, is characterized in that, comprising:
First comparator and the second comparator, be configured for and the first analogue audio frequency input signal and the second analogue audio frequency input signal be converted to the first audio frequency square wave and the second audio frequency square wave respectively;
Logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and is configured for:
The first processed audio signal with following pulse is generated when the duty ratio of described first audio frequency square wave is greater than the duty ratio of described second audio frequency square wave, this pulse represents the twice from the rising edge of described first audio frequency square wave to the time cycle of the rising edge of described second audio frequency square wave
The described first processed audio signal had with reference to DC level is generated when the duty ratio of described first audio frequency square wave is less than the duty ratio of described second audio frequency square wave,
The second processed audio signal with following pulse is generated when the duty ratio of described second audio frequency square wave is greater than the duty ratio of described first audio frequency square wave, this pulse represents the twice from the rising edge of described second audio frequency square wave to the time cycle of the rising edge of described first audio frequency square wave, and
Generate when the duty ratio of described second audio frequency square wave is less than the duty ratio of described first audio frequency square wave and there is the described described second processed audio signal with reference to DC level; And
First output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
13. electronic installations according to claim 12, is characterized in that, described first comparator arrangement is used for, by described first analogue audio frequency input signal and triangular wave being compared, described first analogue audio frequency input signal is converted to the first square wave; And wherein said second comparator arrangement is used for, by described second analogue audio frequency input signal and triangular wave being compared, described second analogue audio frequency input signal is converted to the second audio frequency square wave.
14. electronic installations according to claim 12, is characterized in that, described first output stage comprises:
First amplifier, is configured for receive described first processed audio signal and generate first and amplifies audio signal,
First PMOS transistor, having drain electrode, being coupled to the source electrode of supply voltage and for receiving the grid that described first has amplified audio signal, and
First nmos pass transistor, have be coupled to ground connection source electrode, be coupled to described first PMOS transistor drain electrode drain electrode and for receiving the grid that described first has amplified audio signal,
Wherein said first PMOS transistor and described first nmos pass transistor cooperation are for generating described first audio output signal;
And wherein said second output stage comprises:
Second amplifier, is configured for receive described second processed audio signal and generate second and amplifies audio signal,
Second PMOS transistor, having drain electrode, being coupled to the source electrode of supply voltage and for receiving the grid that described second has amplified audio signal, and
Second nmos pass transistor, have be coupled to ground connection source electrode, be coupled to described second PMOS transistor drain electrode drain electrode and for receiving the grid that described second has amplified audio signal,
Wherein said second PMOS transistor and described second nmos pass transistor cooperation are for generating described second audio output signal.
15. 1 kinds of electronic installations, is characterized in that, comprising:
First comparator and the second comparator, be configured for, by the first analogue audio frequency input signal and the second analogue audio frequency input signal being compared with first waveform and the second waveform with the reference cycle, described first analogue audio frequency input signal and described second analogue audio frequency input signal be converted to the first audio frequency square wave and the second audio frequency square wave, described first analogue audio frequency input signal and described second analogue audio frequency input signal are all changed twice during the described reference cycle;
Logic chunk, coupling is used for receiving described first audio frequency square wave and described second audio frequency square wave from described first comparator and described second comparator, and be configured for and generate the first processed audio signal and the second processed audio signal based on described first audio frequency square wave and described second audio frequency square wave, in described first processed audio signal and described second processed audio signal only one change twice during the described reference cycle;
First output stage and the second output stage, be coupled to described logic chunk, and be configured for and generate the first audio output signal and the second audio output signal respectively based on described first processed audio signal and described second processed audio signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520297094.3U CN204948031U (en) | 2015-05-08 | 2015-05-08 | Electronic installation and class-D amplifier |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520297094.3U CN204948031U (en) | 2015-05-08 | 2015-05-08 | Electronic installation and class-D amplifier |
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| CN204948031U true CN204948031U (en) | 2016-01-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201520297094.3U Withdrawn - After Issue CN204948031U (en) | 2015-05-08 | 2015-05-08 | Electronic installation and class-D amplifier |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106208991A (en) * | 2015-05-08 | 2016-12-07 | 意法半导体研发(深圳)有限公司 | There is the efficient class-D amplifier that the EMI of minimizing generates |
| CN106788291A (en) * | 2016-12-16 | 2017-05-31 | 深圳市生微电子有限公司 | High-power amplifier integrated circuit |
| CN114421906A (en) * | 2022-03-14 | 2022-04-29 | 深圳市汇顶科技股份有限公司 | class-D amplifier and related chip and electronic device |
-
2015
- 2015-05-08 CN CN201520297094.3U patent/CN204948031U/en not_active Withdrawn - After Issue
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106208991A (en) * | 2015-05-08 | 2016-12-07 | 意法半导体研发(深圳)有限公司 | There is the efficient class-D amplifier that the EMI of minimizing generates |
| CN106208991B (en) * | 2015-05-08 | 2019-12-03 | 意法半导体研发(深圳)有限公司 | The efficient class-D amplifier that EMI with reduction is generated |
| CN106788291A (en) * | 2016-12-16 | 2017-05-31 | 深圳市生微电子有限公司 | High-power amplifier integrated circuit |
| CN114421906A (en) * | 2022-03-14 | 2022-04-29 | 深圳市汇顶科技股份有限公司 | class-D amplifier and related chip and electronic device |
| CN114421906B (en) * | 2022-03-14 | 2023-05-02 | 深圳市汇顶科技股份有限公司 | Class D amplifier, related chip and electronic device |
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Granted publication date: 20160106 Effective date of abandoning: 20191203 |