CN204945681U - A kind of SOC module with sequential control - Google Patents
A kind of SOC module with sequential control Download PDFInfo
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- CN204945681U CN204945681U CN201520681258.2U CN201520681258U CN204945681U CN 204945681 U CN204945681 U CN 204945681U CN 201520681258 U CN201520681258 U CN 201520681258U CN 204945681 U CN204945681 U CN 204945681U
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Abstract
The utility model discloses a kind of SOC module with sequential control, comprise SOC and a RC time delay power module, a described RC time delay power module comprises: the first power module, and the first delay circuit be made up of the first resistance and the first electric capacity; One end of described first resistance connects feeder ear, and the other end of the first resistance connects the power enable end of the first power module, also by the first capacity earth, the output terminal of described first power module connects the first power input of SOC.The utility model only increases the power supply sequential that a resistance and electric capacity carry out time delay SOC, meets SOC system to the requirement of different electrical power module timing Design.
Description
Technical field
The utility model relates to power circuit design, particularly a kind of SOC module with sequential control.
Background technology
Circuit designer is all known, in an electronic product, comparatively two modules of core are SOC(SystemonChip, system level chip) module and power module, the Energy control required by general SOC module has stricter timing requirements.The general GPIO that uses carries out sequential control (namely by the sequential of software control power module) to power module at present, although the variation of the variation of product, function is much by software simulating, major part also can by hardware implementing.For example: have the SOC of timing requirements when not having enough GPIO mouths to do the sequential control of software, general by increasing extended chip or replacing SOC solves this problem.And this two schemes all can increase cost and the complicacy of hardware design, it is not best solution.
Thus prior art need to improve.
Utility model content
In view of above-mentioned the deficiencies in the prior art part, the purpose of this utility model is to provide a kind of SOC module with sequential control, can control under the prerequisite of lower cost to the power supply sequential of SOC.
In order to achieve the above object, the utility model takes following technical scheme:
Have a SOC module for sequential control, comprise SOC, a RC time delay power module, a described RC time delay power module comprises: the first power module, and the first delay circuit be made up of the first resistance and the first electric capacity; One end of described first resistance connects feeder ear, and the other end of the first resistance connects the power enable end of the first power module, also by the first capacity earth, the output terminal of described first power module connects the first power input of SOC.
Described has in the SOC module of sequential control, described first power module comprises the first power supply chip, second resistance, 3rd resistance, second electric capacity and the 3rd electric capacity, the Enable Pin of described first power supply chip is the power enable end of the first power module, connect the other end of described first resistance, the IN end of described first power supply chip connects described feeder ear, also by the second capacity earth, the FB/OUT end of described first power supply chip is the output terminal of the first power module, connect one end of the second resistance and the first power input of SOC, also by the 3rd capacity earth, the BP of described first power supply chip holds the other end of connection second resistance, also by the 3rd resistance eutral grounding.
Described has in the SOC module of sequential control, and described first power supply chip is the integrated chip of SGM2019-ADJ series.
Described has in the SOC module of sequential control, and the resistance of described first resistance is 30K Ω, and the capacitance of the first electric capacity is 0.1UF.
The described SOC module with sequential control, also comprises the 2nd RC time delay power module, and described 2nd RC time delay power module comprises: second source module, and the second delay circuit be made up of the 4th resistance and the 4th electric capacity; One end of described 4th resistance connects feeder ear, and the other end of the 4th resistance connects the power enable end of second source module, also by the 4th capacity earth, the output terminal of described second source module connects the second source input end of SOC.
The described SOC module with sequential control, described second source module comprises second source chip, 5th resistance, 6th resistance, 5th electric capacity and the 6th electric capacity, the Enable Pin of described second source chip is the power enable end of second source module, connect the other end of described 4th resistance, the IN end of described second source chip connects described feeder ear, also by the 5th capacity earth, the FB/OUT end of described second source chip is the output terminal of second source module, connect one end of the 5th resistance and the second source input end of SOC, also by the 6th capacity earth, the BP of described second source chip holds the other end of connection the 5th resistance, also by the 6th resistance eutral grounding.
The described SOC module with sequential control, described second source chip is the integrated chip of SGM2019-ADJ series.
The described SOC module with sequential control, the resistance of described 4th resistance is 15K Ω, and the capacitance of the 4th electric capacity is 0.1UF.
The described SOC module with sequential control, the first power input of described SOC is the LOG power input of SOC, and the second source input end of SOC is the ARM power input of SOC.
Compared to prior art, the SOC module of sequential control that what the utility model provided have, comprise SOC and a RC time delay power module, a described RC time delay power module comprises: the first power module, and the first delay circuit be made up of the first resistance and the first electric capacity; One end of described first resistance connects feeder ear, and the other end of the first resistance connects the power enable end of the first power module, also by the first capacity earth, the output terminal of described first power module connects the first power input of SOC.The utility model only increases the power supply sequential that a resistance and electric capacity carry out time delay SOC, meets SOC system to the requirement of different electrical power module timing Design.
Accompanying drawing explanation
Fig. 1 is the structured flowchart that the utility model has the SOC module of sequential control;
Fig. 2 is the circuit diagram that the utility model has a RC time delay power module in the SOC module of sequential control;
Fig. 3 is the circuit diagram that the utility model has the 2nd RC time delay power module in the SOC module of sequential control;
Fig. 4 is the electrifying timing sequence schematic diagram that the utility model has SOC in the SOC module of sequential control.
Embodiment
The utility model provides a kind of SOC module with sequential control, utilize the time-delay characteristics of RC circuit to solve in Power Management Design and meet the requirement of SOC system to sequential control, and different RC circuit can be adopted for different power modules, thus meet the requirement of SOC system to different electrical power module timing Design.
For making the purpose of this utility model, technical scheme and effect clearly, clearly, referring to the accompanying drawing embodiment that develops simultaneously, the utility model is further described.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Refer to Fig. 1 and Fig. 2, the SOC module of sequential control that what the utility model provided have comprises SOC U1 and a RC time delay power module 10, a described RC time delay power module 10 comprises: the first power module 101, and the first delay circuit 102 be made up of the first resistance R1 and the first electric capacity C1; One end of described first resistance R1 connects feeder ear VSYS, the other end of the first resistance R1 connect the first power module 101 power enable end, also by the first electric capacity C1 ground connection, the output terminal of described first power module 101 connects the first power input VLOG of SOC U1.
When a RC time delay power module 10 powers on, carry out time delay first to the first electric capacity C1 charging, according to the characteristic of RC delay circuit, can by time delay by the enable signal of RC electric current, its delay time obtains especially by following formula:
T1=-R1×C1×ln((E-V)/E)
Wherein, R1 is the resistance of the first resistance R1, and C1 is the capacitance of the first electric capacity C1, and E is the voltage of feeder ear VSYS, the effective voltage of V to be the first power module be power enable end.Therefore, only need adjust the value of the first resistance R1 and the first electric capacity C1 to meet the requirement of different electric power source pair of module sequential, thus reach the problem not using the software-controlled manner of GPIO also can solve electric power source pair of module timing requirements, and owing to have employed simple RC circuit design, make the hardware design of whole circuit and LAYOUT design all fairly simple.
Please continue to refer to Fig. 1 and Fig. 2, described first power module 101 comprises the first power supply chip U2, the second resistance R2, the 3rd resistance R3, the second electric capacity C2 and the 3rd electric capacity C3.The Enable Pin of described first power supply chip U2 (namely
end) be the first power module 101 power enable end, connect the other end of described first resistance R1, the IN end of described first power supply chip U2 connects described feeder ear VSYS, also by the second electric capacity C2 ground connection, the FB/OUT end of described first power supply chip U2 be the output terminal of the first power module 101, the one end connecting the second resistance R2 and SOC U1 the first power input VLOG, also by the 3rd electric capacity C3 ground connection, the BP of described first power supply chip U2 holds the other end of connection second resistance R2, also by the 3rd resistance R3 ground connection.
Wherein, described second resistance R2 is current-limiting resistance, the 3rd resistance R3 is pull down resistor, and the second electric capacity C2 and the 3rd electric capacity C3 is filter capacitor.First power supply chip U2 is integrated chip or other power supply chip of SGM2019-ADJ series.The resistance of described first resistance R1 is 30K Ω, and the capacitance of the first electric capacity C1 is 0.1UF, supposes that the voltage of feeder ear VSYS is 4V, and the first power module is the effective voltage of power enable end is 3V, thus the delay time of a RC time delay power module 10 is 4mS.
See also Fig. 3, the SOC module with sequential control of the present utility model also comprises the 2nd RC time delay power module 20, described 2nd RC time delay power module 20 comprises: second source module 201, and the second delay circuit 202 be made up of the 4th resistance R4 and the 4th electric capacity C4; One end of described 4th resistance R4 connects feeder ear VSYS, the other end of the 4th resistance R4 connect second source module 201 power enable end, also by the 4th electric capacity C4 ground connection, the output terminal of described second source module 201 connects the second source input end VARM of SOC U1, due to the second delay circuit 202 circuit form and principle of work identical with the first delay circuit 102, repeat no more herein.
Correspondingly, described second source module 201 comprises second source chip U3, 5th resistance R5, 6th resistance R6, 5th electric capacity C5 and the 6th electric capacity C6, the Enable Pin of described second source chip U3 is the power enable end of second source module 201, connect the other end of described 4th resistance R4, the IN end of described second source chip U3 connects described feeder ear VSYS, also by the 5th electric capacity C5 ground connection, the FB/OUT end of described second source chip U3 is the output terminal of second source module 201, connect one end of the 5th resistance R5 and the second source input end VARM of SOC U1, also by the 6th electric capacity C6 ground connection, the BP of described second source chip U3 holds the other end of connection the 5th resistance R5, also by the 6th resistance R6 ground connection.
Wherein, described second source chip U3 is the integrated chip of SGM2019-ADJ series, or other power supply chip, and the resistance of described 4th resistance R4 is 15K Ω, and the capacitance of the 4th electric capacity C4 is 0.1UF.Suppose that the voltage of feeder ear VSYS is 4V, first power module is the effective voltage of power enable end is 3V, thus the delay time of the 2nd RC time delay power module 20 is 2mS, thus achieve the requirement of different sequential according to the value of the 4th resistance R4 and the 4th electric capacity C4.
In order to better understand the utility model, the sequential control mode this practicality below in conjunction with Fig. 1 to Fig. 4 to the SOC module of sequential control is described in detail:
Be provided with 4 power supplys in described SOC U1, therefore it has 4 power inputs, is respectively: VCC1.8V, VCCIO3.3V, LOG and RAM.Wherein, the first power input VLOG of described SOC U1 is the LOG power input of SOC U1, and the second source input end VARM of SOC U1 is the ARM power input of SOC U1.
According to Fig. 4, ARM power input 2mS faster than LOG power input power up requirement, known according to computing formula T=-R*C*ln ((E-V)/E), at E=4V, V=3V, the resistance of the first resistance R1 is 30K Ω, the capacitance of the first electric capacity C1 is 0.1UF, the resistance of the 4th resistance R4 is 15K Ω, when the capacitance of the 4th electric capacity C4 is 0.1UF, the delay time that LOG power input powers on is 4mS, the delay time that ARM power input powers on is 2mS, i.e. ARM power supply 2mS faster than LOG power supply electrifying sequential, thus by setting corresponding RC parameter to meet the timing requirements of SOC system.
Compared with present technology, the utility model has following beneficial effect:
1, prior art generally adopts the software control of GPIO mouth, when the GPIO mouth of SOC is inadequate, adopt to increase GPIO extended chip or change SOC mode and realize, and the utility model only need increase a resistance in corresponding power module and an electric capacity can change electrifying timing sequence, its implementation is simple, adds the convenience of design.
2, because prior art needs increase extended chip or upgrade SOC, hardware cost and circuit must be increased like this and change that LAYOUT must be brought to design is more complicated, and this scheme only adopts RC circuit, the increase of hardware cost is almost negligible.
Be understandable that; for those of ordinary skills; can be equal to according to the technical solution of the utility model and utility model design thereof and replace or change, and all these change or replace the protection domain that all should belong to the claim appended by the utility model.
Claims (9)
1. have a SOC module for sequential control, comprise SOC, it is characterized in that, also comprise a RC time delay power module, a described RC time delay power module comprises: the first power module, and the first delay circuit be made up of the first resistance and the first electric capacity; One end of described first resistance connects feeder ear, and the other end of the first resistance connects the power enable end of the first power module, also by the first capacity earth, the output terminal of described first power module connects the first power input of SOC.
2. the SOC module with sequential control according to claim 1, it is characterized in that, described first power module comprises the first power supply chip, second resistance, 3rd resistance, second electric capacity and the 3rd electric capacity, the Enable Pin of described first power supply chip is the power enable end of the first power module, connect the other end of described first resistance, the IN end of described first power supply chip connects described feeder ear, also by the second capacity earth, the FB/OUT end of described first power supply chip is the output terminal of the first power module, connect one end of the second resistance and the first power input of SOC, also by the 3rd capacity earth, the BP of described first power supply chip holds the other end of connection second resistance, also by the 3rd resistance eutral grounding.
3. the SOC module with sequential control according to claim 2, is characterized in that, described first power supply chip is the integrated chip of SGM2019-ADJ series.
4. the SOC module with sequential control according to claim 2, is characterized in that, the resistance of described first resistance is 30K Ω, and the capacitance of the first electric capacity is 0.1UF.
5. the SOC module with sequential control according to claim 2, it is characterized in that, also comprise the 2nd RC time delay power module, described 2nd RC time delay power module comprises: second source module, and the second delay circuit be made up of the 4th resistance and the 4th electric capacity; One end of described 4th resistance connects feeder ear, and the other end of the 4th resistance connects the power enable end of second source module, also by the 4th capacity earth, the output terminal of described second source module connects the second source input end of SOC.
6. the SOC module with sequential control according to claim 5, it is characterized in that, described second source module comprises second source chip, 5th resistance, 6th resistance, 5th electric capacity and the 6th electric capacity, the Enable Pin of described second source chip is the power enable end of second source module, connect the other end of described 4th resistance, the IN end of described second source chip connects described feeder ear, also by the 5th capacity earth, the FB/OUT end of described second source chip is the output terminal of second source module, connect one end of the 5th resistance and the second source input end of SOC, also by the 6th capacity earth, the BP of described second source chip holds the other end of connection the 5th resistance, also by the 6th resistance eutral grounding.
7. the SOC module with sequential control according to claim 6, is characterized in that, described second source chip is the integrated chip of SGM2019-ADJ series.
8. the SOC module with sequential control according to claim 6, is characterized in that, the resistance of described 4th resistance is 15K Ω, and the capacitance of the 4th electric capacity is 0.1UF.
9. the SOC module with sequential control according to claim 6, is characterized in that, the first power input of described SOC is the LOG power input of SOC, and the second source input end of SOC is the ARM power input of SOC.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520681258.2U CN204945681U (en) | 2015-09-06 | 2015-09-06 | A kind of SOC module with sequential control |
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| CN201520681258.2U CN204945681U (en) | 2015-09-06 | 2015-09-06 | A kind of SOC module with sequential control |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838790A (en) * | 2018-08-15 | 2020-02-25 | 鸿富锦精密工业(武汉)有限公司 | Power supply control circuit and mainboard applying same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110838790A (en) * | 2018-08-15 | 2020-02-25 | 鸿富锦精密工业(武汉)有限公司 | Power supply control circuit and mainboard applying same |
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