CN204945383U - A kind of Beidou II navigation message harvester - Google Patents
A kind of Beidou II navigation message harvester Download PDFInfo
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- CN204945383U CN204945383U CN201520650972.5U CN201520650972U CN204945383U CN 204945383 U CN204945383 U CN 204945383U CN 201520650972 U CN201520650972 U CN 201520650972U CN 204945383 U CN204945383 U CN 204945383U
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Abstract
The utility model discloses a kind of Beidou II navigation message harvester, its inside comprises signal receiving unit, bit synchronization modulating unit, frame synchronization modulating unit and the signal output unit that signal is successively connected, and wherein signal receiving unit has multiple separate input channel; Described bit synchronization modulating unit is made up of jointly the first bit synchronization modulation component and second synchronous modulation assembly, and respectively to the D1 code in navigation message and D2 code execute bit synchronous modulation; The bit synchronization pulse that described frame synchronization modulating unit receives from bit synchronization modulating unit performs frame synchronization modulation, is then stored in units of subframe in fifo module by navigation message; Signal output unit then provides multiple signal Output rusults.By the utility model, the Fast synchronization to navigation message can be realized, alleviate the pressure of positioning calculation, possess compact conformation simultaneously, be convenient to manufacture, synchronous and testing accuracy advantages of higher.
Description
Technical field
The utility model belongs to satellite navigation relevant device technical field, more specifically, relates to a kind of Beidou II (BD2) navigation message harvester.
Background technology
GLONASS (Global Navigation Satellite System) mainly comprises the Galileo of the GPS of the U.S., Muscovite GLONASS, European Union, and the dipper system etc. of China.Wherein, Beidou II (BD2) system, as round-the-clock, the high precision of China from main control and the satellite navigation system of wide covering, possesses the station-keeping ability suitable with GPS, and confidence level and interference free performance performance excellent.
Navigation message be by Navsat with the streamed user of sending to of binary code for describing the text of running state parameter, comprise the content such as corrected parameter, satellite situation of system time, ephemeris, satellite clock.Different with structure according to speed, the navigation message of BD2 system is divided into D1 code navigation message and D2 code navigation message, wherein D1 code navigation message speed is 50bps, i.e. every 20ms a data position, and modulation has speed to be the secondary coding of 1kbps, D2 code navigation message speed is 500bps, i.e. every 2ms a data position.In the case, traditional navigation message is synchronous and verify and cannot apply to BD2 system preferably, easily causes extend or timing error lock in time, especially cannot judge the situation that multidigit navigation message is made mistakes.
Utility model content
For above defect or the Improvement requirement of prior art, the utility model provides a kind of Beidou II navigation message harvester, wherein by improving the concrete structure of its key component and circuit connecting mode thereof, the Fast synchronization to navigation message should be able to be realized mutually, alleviate the pressure of positioning calculation, possess compact conformation simultaneously, be convenient to manufacture, synchronous and testing accuracy advantages of higher, be thus particularly useful for the practical application of BD2 navigational system.
For achieving the above object, according to the utility model, provide a kind of Beidou II navigation message harvester, it is characterized in that, this harvester inside comprises signal receiving unit, bit synchronization modulating unit, frame synchronization modulating unit and the signal output unit that signal is successively connected, wherein:
Described signal receiving unit has multiple separate input channel, and respectively input comprise that clock, reset, satellite number, passage are enable, a series of signal of navigation message and pulse;
Described bit synchronization modulating unit is made up of jointly the first bit synchronization modulation component and second synchronous modulation assembly, these two bit synchronization modulation components all take the structure of shift register to perform synchronous modulation respectively to the D1 code in navigation message and D2 code, and have separately and pass into the corresponding interface be connected of channel signal with each of described signal receiving unit;
Described frame synchronization modulating unit comprises the frame synchronization modulation component taking shift register structure equally, and the bit synchronization pulse received from described bit synchronization modulating unit performs frame synchronization modulation, then navigation message is stored in fifo module in units of subframe;
Described signal output unit continues to be connected with described frame synchronization modulating unit signal, and exported by multiple output channel comprise frame pulse, frame synchronization completes mark, second in week, subframe numbers and navigation message FIFO output a series of signal.
As further preferably, described frame synchronization modulating unit also comprises BCH and verifies assembly, and it is connected with described frame synchronization modulation component signal, and carries out Error Correction of Coding based on BCH code.
As further preferably, above-mentioned navigation message harvester entirety is set up based on FPGA.
In general, the above technical scheme conceived by the utility model compared with prior art, by taking into full account structure and the processing feature of BD2 navigation message self, respective design meets the navigation message harvester of its user demand, and to its key component as the composition structure of bit synchronization modulating unit and frame synchronization modulating unit and and other unit between annexation improve, the synchronous processing time of navigation message can be significantly improved thus, accurate judgement error status also reduces timing error rate, thus the application scenario of BD2 navigational system is particularly useful for.
Accompanying drawing explanation
Fig. 1 is according to navigation message harvester entirety composition of the present utility model and the internal structure schematic diagram being interconnected mode for exemplary display;
Fig. 2 is the principle of work schematic diagram for showing device shown in Fig. 1;
Wherein, all identical Reference numerals are used for representing identical element or structure, wherein:
1-signal receiving unit 2-bit synchronization modulating unit 3-frame synchronization modulating unit 4-signal output unit 21-first bit synchronization modulation component 22-second synchronous modulation assembly 31-frame synchronization modulation component 32-BCH verifies assembly
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.In addition, if below in described each embodiment of the utility model involved technical characteristic do not form conflict each other and just can mutually combine.
Fig. 1 is for the schematic diagram of exemplary display according to navigation message harvester unitary construction of the present utility model and connected mode.As shown in fig. 1, this navigation message harvester for example can build based on the frame form of FPGA, and comprise signal receiving unit 1, bit synchronization modulating unit 2, frame synchronization modulating unit 3 and the signal output unit 4 that signal is connected successively therein, wherein by the construction itself of these assemblies and be interconnected configuration design, the corresponding object reaching the practical application request meeting BD2 navigational system better.
More specifically, as shown in Figure 2, this signal receiving unit 1 has multiple separate input channel, and respectively input comprise clock (clock), a series of signal of reset (reset), satellite number (star_num), passage enable (channel_start) and pulse (dump); In addition, understand ground as those skilled in the art, the clearing (FIFO_rdclk) of navigation message FIFO, 1ms original navigation text sign bit (Corr_I_sign) can also be comprised and read other data such as clock (FIFO_sclr);
Bit synchronization modulating unit 2 is jointly made up of the first bit synchronization modulation component 21 and second synchronous modulation assembly 22 in the utility model, these two bit synchronization modulation components are arranged independently of one another, and preferably all take the structure of shift register, they have separately and pass into the corresponding interface be connected of channel signal with each of described signal receiving unit, and respectively to the D1 code in navigation message and D2 code execute bit synchronous modulation; Specifically, first bit synchronization modulation component 21, second synchronous modulation assembly 22 comprise clock interface (clock), reseting interface (reset), passage enable (channel_start), dump interface, navigation message D1 code interface/navigation message D2 code interface (D1/D2_in) etc. separately, thus independently of each other to D1 code and D2 code execute bit synchronous modulation respectively, then its bit synchronization pulse (BIT_SYNC_D1, BIT_SYNC_D2) and navigation message accumulated value (I_INF_IN) etc. are sent to frame synchronization modulating unit 3 in the lump.
Frame synchronization modulating unit 3 comprises the frame synchronization modulation component 31 taking shift register structure equally, and the bit synchronization pulse (BIT_SYNC) received from two bit synchronization modulation components 21 and 22 performs frame synchronization modulation, then navigation message is stored in fifo module in units of subframe; Similarly, it equally also has multiple interfaces such as clock interface (clock), reseting interface (reset), passage enable (channel_start) except bit synchronization pulse interface (BIT_SYNC) and navigation message accumulated value interface (I_INF_IN).In addition, according to a preferred embodiment of the present utility model, this frame synchronization modulating unit 3 is preferably also equipped with BCH to verify assembly 32, it is connected with described frame synchronization modulation component 31 signal, and carry out Error Correction of Coding based on BCH code, not only realize the Fast synchronization of navigation message thus, also complete the same period BCH of navigation message is verified, the process such as Effective judgement.
Signal output unit 4 continues through multiple passage independent of each other and is connected with described frame synchronization modulating unit signal, and exported by multiple output channel comprise frame pulse (FRAME_SYNC), frame synchronization completes mark (FRAME_SYNC_flag), week in second (Sow_Cnt), subframe numbers (FrameNumber) and navigation message FIFO output (FIFO_qout) a series of signal.
Below by specific explanations according to the course of work of the present utility model.
First according to actual needs various signal is inputted with satellite type etc., the bit synchronization module selecting enable D1 or D2 code is carried out according to satellite number, and frame synchronization modulating unit is sent in bit synchronization pulse and navigation message accumulated value, frame synchronization modulating unit completes the frame synchronization of navigation message and other are as operations such as BCH decoding and judgements, then navigation message to be stored in FIFO to read for microprocessor in units of subframe, second and subframe numbers in the week of simultaneously latching present sub-frame.
After frame synchronization completes, the navigation message that can comprise BCH decoding checking according to the sequential storage of subframe in FIFO, after storing whole subframe, notice microprocessor carry out this subframe navigation message, subframe numbers and in week second information reading, and FIFO to be reset.
Those skilled in the art will readily understand; the foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all do within spirit of the present utility model and principle any amendment, equivalent to replace and improvement etc., all should be included within protection domain of the present utility model.
Claims (2)
1. a Beidou II navigation message harvester, is characterized in that, this harvester inside comprises signal receiving unit, bit synchronization modulating unit, frame synchronization modulating unit and the signal output unit that signal is successively connected, wherein:
Described signal receiving unit has multiple separate input channel, and respectively input comprise that clock, reset, satellite number, passage are enable, a series of signal of navigation message and pulse;
Described bit synchronization modulating unit is made up of jointly the first bit synchronization modulation component and second synchronous modulation assembly, these two bit synchronization modulation components all take the structure of shift register to perform synchronous modulation respectively to the D1 code in navigation message and D2 code, and have separately and pass into the corresponding interface be connected of channel signal with each of described signal receiving unit;
Described frame synchronization modulating unit comprises the frame synchronization modulation component taking shift register structure equally, and the bit synchronization pulse received from described bit synchronization modulating unit performs frame synchronization modulation, then navigation message is stored in fifo module in units of subframe;
Described signal output unit continues to be connected with described frame synchronization modulating unit signal, and exported by multiple output channel comprise frame pulse, frame synchronization completes mark, second in week, subframe numbers and navigation message FIFO output a series of signal.
2. Beidou II navigation message harvester as claimed in claim 1, is characterized in that, described frame synchronization modulating unit also comprises BCH and verifies assembly, and it is connected with described frame synchronization modulation component signal, and carries out Error Correction of Coding based on BCH code.
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108549096A (en) * | 2018-04-17 | 2018-09-18 | 中国科学院微电子研究所 | The method and device of GPS navigation message error-correcting decoding |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
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CN108549096A (en) * | 2018-04-17 | 2018-09-18 | 中国科学院微电子研究所 | The method and device of GPS navigation message error-correcting decoding |
CN108549096B (en) * | 2018-04-17 | 2021-10-01 | 中国科学院微电子研究所 | Method and device for error correction and decoding of GPS navigation message |
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