CN204945242U - A kind of CPLD frequency meter based on equal precision measurement method - Google Patents

Abstract

The utility model discloses a kind of CPLD frequency meter based on equal precision measurement method, comprise single-chip microcomputer and CPLD controller, single-chip microcomputer realizes being electrically connected with CPLD controller by SPI serial communication interface, CPLD controller comprises the first controllable counter unit, second controlled counting unit and d type flip flop, the counting clock end of the first controllable counter unit is connected with the signal output part of controllable frequency division unit, the counting clock end of the second controllable counter unit is measured signal input end, the data input pin of d type flip flop is connected with from device data input line SDI, the input end of clock of d type flip flop is connected with the counting clock end of the second controllable counter unit, the data output end of d type flip flop is connected with the counting Enable Pin of the second controllable counter unit with the counting Enable Pin of the first controllable counter unit simultaneously.The utility model has that job stability is strong, and measuring accuracy is high, and design difficulty is little, can the wide advantage of measured frequency scope.

Description

A kind of CPLD frequency meter based on equal precision measurement method

Technical field

The utility model relates to a kind of digital frequency meter realized based on equal precision measurement method, and specifically a kind of CPLD of employing controller carries out the frequency meter of frequency counting, belongs to observation and control technology field.

Background technology

The measuring principle that in prior art, digital frequency meter adopts is generally Measuring Frequency Method and measuring period method.Measuring Frequency Method is exactly in the gate time determined in Tg, and period of change number (or pulse number) Nx of record measured signal, then the frequency of measured signal is: fx=Nx/Tg.Measuring period method needs the frequency f s of standard signal, and in the one-period Tx of measured signal, the periodicity Ns of record standard frequency, then the frequency of measured signal is: fx=fs/Ns.The count value of these two kinds of methods can produce ± 1 word error, and measuring accuracy is relevant with the numerical value of N x recorded in counter or Ns.In order to ensure measuring accuracy, generally measuring period method is adopted for low frequency signal, Measuring Frequency Method is adopted for high-frequency signal.Obvious, no matter adopt any measuring principle completion system to design, the range of application of designed frequency meter all can be limited, and namely the versatility of instrument is not strong yet.

Which kind of realizing in the hardware structure of system: no matter be based on measuring principle realize measuring, in prior art there are two kinds of different technical schemes in the design of digital frequency meter usually: be that acp chip is measured with single-chip microcomputer, or be that core is measured with programmable logic device (PLD).Think that single-chip microcomputer is that core is measured, because single-chip microcomputer is in logical operation, Based Intelligent Control, there is good characteristic, therefore system hardware and software design is all simpler, debugging easily, but due to single-chip microcomputer functional reliability low, the reset of moment also can cause serious consequence in some cases, therefore systematic survey stability is not high, and the raising of measuring accuracy is limited.At present, adopt more scheme still with programmable logic device (PLD), namely CPLD or FPGA is that control core realizes measuring, although this mode system works stability is high, measuring accuracy is high, but adopt CPLD to carry out observing and controlling and also there is drawback: mainly CPLD underaction in Based Intelligent Control, this just causes CPLD internal logic design complexities high, design frequency measurement control module is also needed except needing the conventional counting unit of design, latch, the modules such as display decoding, particularly higher to the designing requirement of frequency measurement control module, therefore design difficulty is increased.

Utility model content

For prior art above shortcomings, the purpose of this utility model is: how to provide a kind of system works stability strong, measuring accuracy is high, and design difficulty is little, and debugging easily, and can the wide CPLD frequency meter of measured frequency scope.

To achieve these goals, the utility model have employed following technical scheme.A kind of CPLD frequency meter based on equal precision measurement method, it is characterized in that: comprise single-chip microcomputer and CPLD controller, described single-chip microcomputer realizes being electrically connected by SPI serial communication interface and CPLD controller: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD controller, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD controller, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD controller, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD controller, and connecting line is designated as from devices enable signal wire CS; Described CPLD controller comprises the first controllable counter unit, second controlled counting unit and d type flip flop, controllable frequency division unit, parallel serial conversion unit and serioparallel exchange unit, described parallel serial conversion unit has the first parallel input terminal, the second parallel input terminal and serial output terminal; The counting clock end of described first controllable counter unit is connected with the signal output part of controllable frequency division unit, the signal input part of controllable frequency division unit is connected with CPLD controller internal work clock signal terminal, the divide ratio control end of controllable frequency division unit is connected with the output terminal of serioparallel exchange unit, and the input end of serioparallel exchange unit is connected from device data input line SDI with described; The counting clock end of described second controllable counter unit is measured signal input end; The data input pin of described d type flip flop is connected from device data input line SDI with described, the input end of clock of d type flip flop is connected with the counting clock end of the second controllable counter unit, the data output end of d type flip flop is connected with the counting Enable Pin of the first controllable counter unit, and the data output end of d type flip flop is also connected with the counting Enable Pin of the second controllable counter unit; The described terminal count output of the first controllable counter unit is connected with the first parallel input terminal of parallel serial conversion unit, the described terminal count output of the second controllable counter unit is connected with the second parallel input terminal of parallel serial conversion unit, and the serial output terminal of parallel serial conversion unit is connected with from device data output line SDO.

Further, described CPLD controller is EPM7032S chip.

Compared to existing technology, the utility model tool has the following advantages: in the utility model, SPI serial communication interface is adopted to be electrically connected between single-chip microcomputer and CPLD controller, achieve the communication between single-chip microcomputer and CPLD controller, single-chip microcomputer can by from device data input line SDI to CPLD controller, transmission division ratio control signal and preset gate signal are used for CPLD controller internal control use as main equipment, be arranged so that two controlled counting units of CPLD controller inside count within same gate time due to d type flip flop, that is to say and adopt equal precision measurement principle, measured signal frequency is only relevant with standard signal frequency, because standard signal frequency is through inner frequency unit frequency division by CPLD internal clock signal, precision is higher, therefore the measured signal frequency accuracy recorded is also just higher.In addition, because the measuring processes such as inner count measurement utilize its abundant internal digital logic resource to realize by CPLD, owing to being totally digital circuit hardware implementing, working condition is stablized, the counting of the inner counting unit of CPLD exports and is then converted to after serial signal by transferring to single-chip microcomputer from device data output line SDO through inner parallel serial conversion unit, single-chip microcomputer converts data to the frequency values for display screen display, and this just takes full advantage of the advantage of single-chip microcomputer in intelligent computing again; Therefore with prior art in single CPLD or FPGA for control core realizes measuring, internal logic design is complicated, and the present situation of debug difficulties is compared, and it is little that the utility model has design difficulty, and debugging is easy to advantage; And with prior art in adopt single single-chip microcomputer to measure as core, the situation determining the relative pure hardware circuit difference of system works stability due to Single Chip Microcomputer (SCM) system self character is compared, it is strong that the utility model has system works stability, the advantage that measuring accuracy is high.

Accompanying drawing explanation

Fig. 1 is circuit structure diagram of the present utility model;

Embodiment

Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.CPLD frequency meter as shown in Figure 1 based on equal precision measurement method adopts following hardware architecture: the utility model frequency meter comprises: single-chip microcomputer and a CPLD controller, and single-chip microcomputer realizes being electrically connected with CPLD controller by SPI serial communication interface.The basis realizing above-mentioned communication connection is: single-chip microcomputer can simulate SPI Control timing sequence as a kind of intelligent control chip, modern and realize single-chip microcomputer spi bus and send data to CPLD controller and order carrys out control CPLD internal digital logic unit, physical circuit annexation is: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD controller, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD controller, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD controller, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD controller, and connecting line is designated as from devices enable signal wire CS.Four input/output ports of single-chip microcomputer and four input/output ports of CPLD controller are corresponding is respectively connected in a word, realize the SPI communication interface between single-chip microcomputer and CPLD controller by single-chip microcomputer generation SPI work schedule, thus complete the transmission of data between the two.Concrete single-chip microcomputer can select MCS51 series, and CPLD controller can adopt EPM7032S type CPLD controller to realize.

And the circuit connecting relation of CPLD controller internal digital logic circuit is: CPLD controller comprises the first controllable counter unit, second controlled counting unit and d type flip flop, controllable frequency division unit, parallel serial conversion unit and serioparallel exchange unit, described parallel serial conversion unit has the first parallel input terminal, the second parallel input terminal and serial output terminal; The counting clock end of the first controllable counter unit is connected with the signal output part of controllable frequency division unit, the signal input part of controllable frequency division unit is connected with CPLD controller internal work clock signal terminal, the divide ratio control end of controllable frequency division unit is connected with the output terminal of serioparallel exchange unit, and the input end of serioparallel exchange unit is connected from device data input line SDI with described; The counting clock end of the second controllable counter unit is measured signal input end; The data input pin of d type flip flop is connected from device data input line SDI with described, the input end of clock of d type flip flop is connected with the counting clock end of the second controllable counter unit, the data output end of d type flip flop is connected with the counting Enable Pin of the first controllable counter unit, and the data output end of d type flip flop is also connected with the counting Enable Pin of the second controllable counter unit; The terminal count output of the first controllable counter unit is connected with the first parallel input terminal of parallel serial conversion unit, the terminal count output of the second controllable counter unit is connected with the second parallel input terminal of parallel serial conversion unit, and the serial output terminal of parallel serial conversion unit is connected with from device data output line SDO.

Concrete controlled counting unit and principle diagram design mode can be utilized to call counter module for controllable frequency division unit and allocator module realizes.D type flip flop then directly can call d type flip flop Schematic blocks and realize.And parallel serial conversion unit concrete can call 8 registers with set end (call 8 registers be 1 byte for parallel input terminal data width), by this 8 head and the tail of the register with set end series connection, that is to say that first data with the register of set end export Q end and second data with the register of set end and input D and hold and be connected, second data with the register of set end export Q end and the 3rd data with the register of set end and input D and hold and be connected, input D and hold until the 7th data with the register of set end export Q end and the 8th data with the register of set end and be connected, 8th data with the register of set end export the output terminal that namely Q end is parallel serial conversion unit, and namely eight set ends with the register of set end are the input ends of parallel serial conversion unit, eight clock ends with the register of set end link together (above design adopts the principle diagram design mode in FPGA design to realize).Similar and obvious, serioparallel exchange unit is that output terminal is as input end using the input end of parallel serial conversion unit as output terminal.

Principle of work of the present utility model is: first introduce the Control on Communication how single-chip microcomputer realizes between CPLD, and how coordinating both then setting forth displays one's respective advantages realizes measuring.Control on Communication between single-chip microcomputer and CPLD: single-chip microcomputer generation SPI work schedule realizes the SPI communication interface between single-chip microcomputer and CPLD controller, this communication mode at least has root 4 line when one-way communication (only need 3 lines also can realize), concrete respectively: 1, from device data input line SDI, be also main equipment DOL Data Output Line; 2, from device data output line SDO, be also main equipment Data In-Line; 3, clock cable SCLK, clock signal is produced by main equipment; ; 4, from devices enable signal wire CS.

Main equipment and carry out synchronous serial-data transmission between equipment, under the shift pulse of main equipment, data step-by-step is transmitted, and high-order front, status, rear, is full-duplex communication, simply efficiently.The ultimate principle of SPI communication does not repeat here.

In the utility model, single-chip microcomputer is main equipment, and CPLD is from equipment, and CPLD can be first temporary after receiving the data of single-chip microcomputer, then for control or the data input of CPLD internal digital logic unit.On the one hand, EPM7032S chip has 36 I/O mouths, and removing is used for 4 ports with single chip communication, also has 32 ports to use, and this can meet the demand of major part for ports-Extending design completely; CPLD is extensive programmable digital integrated circuit on the other hand, inside has a large amount of digital logic unit, call design by hardware description language or schematic diagram and all can realize complicated stable Digital Logic, thus for whole system provide at a high speed, stable hardware foundation.In addition, following scheme can be adopted to solve about work clock: to utilize outer clock circuit to provide work clock for CPLD controller, CPLD controller internal work clock signal is supplied to single-chip microcomputer and uses as work clock after the inner frequency division module frequency division of CPLD, so just can simplify circuit design further.

The realization of concrete measurement: single-chip microcomputer can send division ratio control signal (yes after the inner serioparallel exchange cell translation of CPLD controller) by the divide ratio control end of the inside controllable frequency division unit from device data input line SDI to CPLD controller as main equipment, the inner controllable frequency division unit of CPLD with CPLD controller internal work clock signal for frequency division object obtains the standard signal of suitable frequency, this standard signal is as the counting clock signal of the first controllable counter unit, measured signal is then as the counting clock signal of the second controllable counter unit.And the counting Enable Pin of the first controllable counter unit and the second controllable counter unit all with the data output end of d type flip flop mutually repeatedly, the input end of clock of d type flip flop is connected with the counting clock end of the second controllable counter unit, that is to say that d type flip flop take measured signal as counting clock, the data input pin of d type flip flop is then by SPI serial communication interface and chip microcontroller Control on Communication, single-chip microcomputer is by sending to the data input pin of d type flip flop the enable control of counting that preset gate signal realizes two controlled counting units, basic controlling process is that single-chip microcomputer sends a lasting high level pulse (i.e. preset gate signal, also gate time is cried), then this high level gather by d type flip flop and export from the data output end of d type flip flop the Enable Pin delivering to two controlled counting units, counter starts counting, but the high level due to d type flip flop image data input end must be just can carry out when input end of clock rising edge arrives, therefore, be actually when the rising edge of measured signal arrives, two controlled counting units just start counting, first controlled counting unit counts the standard signal that frequency division obtains, second controlled counting unit counts measured signal, and at the end of single-chip microcomputer sends a lasting high level pulse (i.e. preset gate signal is also named gate time), preset gate signal is the rising edge due in that low level 0 also must occur in measured signal from high level 1 saltus step.To sum up, the actual gate time (i.e. the high level lasting time of d type flip flop data output end output) of obvious the utility model frequency meter is not fixed value, but the integral multiple in measured signal cycle, namely synchronous with measured signal, actual gate time and the single-chip microcomputer difference sent between preset gate signal high level lasting time is no more than a measured signal Cycle Length, and standard signal is also count within actual gate time, actual gate time is also also be the integral multiple in standard signal cycle, error also can not exceed one-period, namely measured signal and standard signal are all respectively by two controlled counting unit counts within same actual gate time, we call measuring principle described above " equal precision measurement ", if it is Ns that standard signal is counted the count value obtained, it is Nx that measured signal is counted the count value obtained, the frequency f s of standard signal, then fx=Nx × fs/Ns, measured signal frequency is only relevant with standard signal frequency, because standard signal frequency is through inner frequency unit frequency division by CPLD internal clock signal, frequency can higher than measured signal, precision is higher, therefore the measured signal frequency accuracy recorded is also just higher.

The terminal count output of two controllable counter unit exports and is parallel to serial conversion circuit conversion is serial signal, by being sent to this main equipment of single-chip microcomputer from device data output line SDO, single-chip microcomputer carries out conversion process (mainly aforementioned principles carries out frequency computation part and display decoding) to data and namely can be used for display, therefore the frequency measurement control module in pure CPLD frequency meter and data conversion module are just replaced by this powerful intelligent control chip of single-chip microcomputer, the design difficulty of system reduces, and measuring accuracy is not but affected.

What finally illustrate is, above embodiment is only in order to illustrate the technical solution of the utility model and unrestricted, although be described in detail the utility model with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can modify to the technical solution of the utility model or equivalent replacement, and not departing from aim and the scope of technical solutions of the utility model, it all should be encompassed in the middle of right of the present utility model.

Claims (2)

1. the CPLD frequency meter based on equal precision measurement method, it is characterized in that: comprise single-chip microcomputer and CPLD controller, described single-chip microcomputer realizes being electrically connected by SPI serial communication interface and CPLD controller: the first input/output port of single-chip microcomputer is connected with the first input/output port of CPLD controller, and connecting line is designated as from device data input line SDI; Second input/output port of single-chip microcomputer is connected with the second input/output port of CPLD controller, and connecting line is designated as from device data output line SDO; 3rd input/output port of single-chip microcomputer is connected with the 3rd input/output port of CPLD controller, and connecting line is designated as clock cable SCLK; 4th input/output port of single-chip microcomputer is connected with the 4th input/output port of CPLD controller, and connecting line is designated as from devices enable signal wire CS;

Described CPLD controller comprises the first controllable counter unit, second controlled counting unit and d type flip flop, controllable frequency division unit, parallel serial conversion unit and serioparallel exchange unit, described parallel serial conversion unit has the first parallel input terminal, the second parallel input terminal and serial output terminal;

The counting clock end of described first controllable counter unit is connected with the signal output part of controllable frequency division unit, the signal input part of controllable frequency division unit is connected with CPLD controller internal work clock signal terminal, the divide ratio control end of controllable frequency division unit is connected with the output terminal of serioparallel exchange unit, and the input end of serioparallel exchange unit is connected from device data input line SDI with described;

The counting clock end of described second controllable counter unit is measured signal input end;

The data input pin of described d type flip flop is connected from device data input line SDI with described, the input end of clock of d type flip flop is connected with the counting clock end of the second controllable counter unit, the data output end of d type flip flop is connected with the counting Enable Pin of the first controllable counter unit, and the data output end of d type flip flop is also connected with the counting Enable Pin of the second controllable counter unit;

The described terminal count output of the first controllable counter unit is connected with the first parallel input terminal of parallel serial conversion unit, the described terminal count output of the second controllable counter unit is connected with the second parallel input terminal of parallel serial conversion unit, and the serial output terminal of parallel serial conversion unit is connected with from device data output line SDO.

2. a kind of CPLD frequency meter based on equal precision measurement method according to claim 1, it is characterized in that, described CPLD controller is EPM7032S chip.