CN204906346U - Timing control chip and battery charging circuit - Google Patents
Timing control chip and battery charging circuit Download PDFInfo
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- CN204906346U CN204906346U CN201520699747.0U CN201520699747U CN204906346U CN 204906346 U CN204906346 U CN 204906346U CN 201520699747 U CN201520699747 U CN 201520699747U CN 204906346 U CN204906346 U CN 204906346U
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- timing controlled
- controlled chip
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Abstract
The utility model discloses a timing control chip and battery charging circuit. Wherein, the timing control chip includes: comparator, logical operation module and vibration module, the comparator compares external input signal voltage and inside reference voltage, and when external input signal voltage was greater than inside reference voltage, output control signal gave the logical operation module, opens the vibration module by the logical operation module to last the validity of judgment control signal, effectively then control the output of timing control chip as control signal and export, and at the beginning regularly, the judgment control signal is invalid or when regularly the time is arrived in during the timing, closes the output of vibration module and timing control chip, makes timing control chip entering state of dormancy, wherein, the "Frequency" of vibration module is adjusted by the external resistance, utilizes external resistance adjustment "Frequency" to change the regularly time, and can there be the deadlock risk in this timing control chip for dedicated chip in addition.
Description
Technical field
The utility model relates to timing chip designing technique, particularly timing controlled chip and battery charger.
Background technology
At present, a lot of need for environment uses timing function control chip, enables system use certain hour powered-down automatically, increases the fail safe of system.For example, charger needs a timing switch, can charge closing function automatically when ensureing to charge the battery certain hour, and preventing charges for a long time to battery causes cell damage, or charges for a long time to the battery damaged and cause blast equivalent risk.
At present, timing function is in most cases use single-chip microcomputer to realize, and utilizes the counter of single-chip microcomputer inside to count, calculates timing by frequency and count value, reaches timing effect.
But single-chip microcomputer exists certain deadlock risk, single-chip microcomputer internal counter can be caused to count, make timing out.And after single-chip microcomputer write-in program, timing is relatively fixing, when needs adjustment timing, need again to write Single Chip Microcomputer (SCM) program, this will cause the waste of resource.
In addition, the quiescent current of single-chip microcomputer is microampere up to a hundred, and the power consumption adding up when single-chip microcomputer is in resting state for a long time to consume can not be ignored.Single-chip microcomputer end detects voltage high (being greater than 1V), cannot adapt to more sensitive environment.
Thus prior art need to improve.
Utility model content
In view of above-mentioned the deficiencies in the prior art part, the purpose of this utility model is to provide timing controlled chip and battery charger, utilizes non-essential resistance to adjust frequency of oscillation to change timing, and can not there is deadlock risk.
In order to achieve the above object, the utility model takes following technical scheme:
A kind of timing controlled chip, it comprises: comparator, logical operation module and oscillation module, described comparator is by external input signal voltage and internal reference voltage compare, when external input signal voltage is greater than internal reference voltage, export control signal to logical operation module, open oscillation module by logical operation module, and continue the validity judging control signal; The output effectively then controlling timing controlled chip when control signal exports, and starts timing; When judging in during timing that control signal is invalid or timing arrives, close the output of oscillation module and timing controlled chip, make timing controlled chip enter resting state; Wherein, the frequency of oscillation of oscillation module is adjusted by non-essential resistance.
In described timing controlled chip, when described external input signal voltage is less than internal reference voltage, comparator output low level, closes oscillation module by logical operation module.
In described timing controlled chip, described internal reference voltage compare is 0.3V.
In described timing controlled chip, the positive input terminal of described comparator connects the external signal input terminals of timing controlled chip, oscillation module connects the outside oscillation resistance link of timing controlled chip, and the output of logical operation module connects the output of timing controlled chip.
In described timing controlled chip, the model of described timing controlled chip is LC3611.
A kind of battery charger, it comprises: the first resistance, the second resistance, the 3rd resistance, triode, battery interface and timing controlled chip as above; The outside oscillation resistance link of described timing controlled chip connects the positive pole of battery interface by the first resistance, the external signal input terminals of described timing controlled chip connects the negative pole of battery interface, the power input of described timing controlled chip connects the positive pole of battery interface, the output of described timing controlled chip passes through the base stage of the 3rd resistance connecting triode, the collector electrode of described triode connects the negative pole of battery interface, the grounded emitter of described triode by the second resistance.
Described battery charger, also comprises: the 4th resistance and light-emitting diode, and the output of described timing controlled chip also passes through the positive pole of the 4th resistance connecting luminous diode, the minus earth of light-emitting diode.
Compared to prior art, the timing controlled chip that the utility model provides and battery charger, its timing controlled chip comprises: comparator, logical operation module and oscillation module, described comparator is by external input signal voltage and internal reference voltage compare, when external input signal voltage is greater than internal reference voltage, export control signal to logical operation module, open oscillation module by logical operation module, and continue the validity judging control signal; The output effectively then controlling timing controlled chip when control signal exports, and starts timing; When judging in during timing that control signal is invalid or timing arrives, close the output of oscillation module and timing controlled chip, make timing controlled chip enter resting state; Wherein, the frequency of oscillation of oscillation module is adjusted by non-essential resistance, utilize non-essential resistance to adjust frequency of oscillation to change timing, and this timing controlled chip is that special chip can not exist deadlock risk.
Accompanying drawing explanation
The encapsulation figure of the timing controlled chip that Fig. 1 provides for the utility model embodiment.
The internal structure block diagram of the timing controlled chip that Fig. 2 provides for the utility model embodiment.
The flow chart of the control method of the timing controlled chip that Fig. 3 provides for the utility model embodiment.
The workflow diagram of the timing controlled chip that Fig. 4 provides for the utility model embodiment.
The circuit diagram of the battery charger that Fig. 5 provides for the utility model embodiment.
Embodiment
The utility model provides a kind of timing controlled chip and battery charger, for making the purpose of this utility model, technical scheme and effect clearly, clearly, further describes the utility model referring to the accompanying drawing embodiment that develops simultaneously.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Refer to Fig. 1 and Fig. 2, the timing controlled chip that the utility model provides comprises: comparator A1, logical operation module A2 and oscillation module A3, and it is a special regular chip, does not have the risk crashed.In the present embodiment, the model of described timing controlled chip is LC3611, and this chip comprises: power input VDD, outside oscillation resistance link OSC, test pattern selecting side T, power supply ground input GND; Output OUT and external signal input terminals BE.
Wherein, the positive input terminal of described comparator A1 connects the external signal input terminals BE of timing controlled chip, the output of comparator A1 connects logical operation module A2, first output of logical operation module A2 connects the output of timing controlled chip, second output of logical operation module A2 connects oscillation module, and oscillation module A3 connects the outside oscillation resistance link of timing controlled chip.Described logical operation module A2 and oscillation module A3 is the module used in the timing chip of routine.
Described comparator A1 is by external input signal voltage and internal reference voltage compare, when external input signal voltage is greater than internal reference voltage, export control signal to logical operation module, open oscillation module by logical operation module A2, and continue the validity judging control signal; The output effectively then controlling timing controlled chip when control signal exports, and starts timing; When judging in during timing that control signal is invalid or timing arrives, close the output of oscillation module A3 and timing controlled chip, make timing controlled chip enter resting state; Wherein, the frequency of oscillation of oscillation module A2 is adjusted by non-essential resistance, and its timing is directly adjusted by non-essential resistance, without the need to coding again.
When described external input signal voltage is less than internal reference voltage, comparator output low level, closes oscillation module by logical operation module.Wherein, described internal reference voltage compare is 0.3V, and namely applied signal voltage only need be greater than 0.3V, and this timing controlled chip gets final product work, and the input detection voltage of this chip is low as seen, can adapt to multiple applied environment.
The utility model is the corresponding control method providing a kind of timing controlled chip also, and refer to Fig. 3, it comprises:
S100, when there being external input signal, by external input signal voltage and internal reference voltage compare, when external input signal voltage is greater than internal reference voltage, export control signal to logical operation module, open oscillation module by logical operation module;
S200, described logical operation module continue to judge that whether control signal is effective; If so, then step S300 is performed; Otherwise, perform step S400;
The output that S300, described logical operation module control timing controlled chip exports, and starts timing;
The output of S400, closedown oscillation module and timing controlled chip exports, and makes timing controlled chip enter resting state.
Wherein, when judging that during timing control signal is invalid or timing arrives, step S400 is performed.
As shown in Figure 4, timing controlled chip powers on and is in resting state after internal reset, timing controlled chip closes oscillation module to reduce power consumption in the dormant state, judged by the voltage of comparator to external input signal: when not having external input signal, timing controlled chip remains on resting state; When external input signal being detected, timing controlled chip enable oscillation module.
After startup oscillating circuit, timing controlled chip carries out elimination dithering process by counting circuit to input signal, prevents the false triggering of input signal, guarantees the validity of input signal.After determining that input signal is useful signal, timing controlled chip signal output, and open internal timing; After detecting that the invalid or timing of input signal arrives, close output signal and oscillation module, and make timing controlled chip return to resting state.
The utility model is also corresponding provides a kind of battery charger, and as shown in Figure 5, described battery charger comprises: the first resistance R1, the second resistance R2, the 3rd resistance R3, triode Q1, battery interface B1 and timing controlled chip; The outside oscillation resistance link OSC of described timing controlled chip U1 connects the positive pole of battery interface B1 by the first resistance R1, the external signal input terminals BE of described timing controlled chip U1 connects the negative pole of battery interface B1, the power input VDD of described timing controlled chip U1 connects the positive pole of battery interface B1, the output OUT of described timing controlled chip U1 passes through the base stage of the 3rd resistance R3 connecting triode Q1, the collector electrode of described triode Q1 connects the negative pole of battery interface B1, the grounded emitter of described triode Q1 by the second resistance R2.
Please continue to refer to Fig. 5, the battery charger that the utility model provides also comprises: the 4th resistance R4 and light-emitting diode D1, the output OUT of described timing controlled chip U1 also passes through the positive pole of the 4th resistance R4 connecting luminous diode D1, the minus earth of light-emitting diode D1.
When not having battery in battery interface, the BE terminal voltage of timing controlled chip U1 is less than 0.1V, and timing controlled chip U1 can wait charged pool to connect; In battery interface B1, battery is housed, and during external power charging, the BE terminal voltage of timing controlled chip U1 is greater than 0.1V, the OUT end of timing controlled chip U1 exports high level, now light-emitting diode D1 lights instruction charged state, and triode Q1 conducting is charged to battery.
In sum, the utility model has following beneficial effect:
1, the input of timing controlled chip is low voltage test end, can adapt to multiple applied environment;
2, timing controlled chip can adjust frequency of oscillation by non-essential resistance, thus changes timing;
3, timing controlled chip is the risk that special chip does not crash;
4, when timing controlled chip be in resting state time, the closedown oscillator of timing controlled chip, reduce quiescent dissipation;
5, the application circuit structure of timing controlled chip is simple, is convenient to produce.
Be understandable that; for those of ordinary skills; can be equal to according to the technical solution of the utility model and utility model design thereof and replace or change, and all these change or replace the protection range that all should belong to the claim appended by the utility model.
Claims (7)
1. a timing controlled chip, it is characterized in that, comprise: comparator, logical operation module and oscillation module, described comparator is by external input signal voltage and internal reference voltage compare, when external input signal voltage is greater than internal reference voltage, export control signal to logical operation module, open oscillation module by logical operation module, and continue the validity judging control signal; The output effectively then controlling timing controlled chip when control signal exports, and starts timing; When judging in during timing that control signal is invalid or timing arrives, close the output of oscillation module and timing controlled chip, make timing controlled chip enter resting state; Wherein, the frequency of oscillation of oscillation module is adjusted by non-essential resistance.
2. timing controlled chip according to claim 1, is characterized in that, when described external input signal voltage is less than internal reference voltage, comparator output low level, closes oscillation module by logical operation module.
3. timing controlled chip according to claim 1, is characterized in that, described internal reference voltage compare is 0.3V.
4. timing controlled chip according to claim 1, it is characterized in that, the positive input terminal of described comparator connects the external signal input terminals of timing controlled chip, oscillation module connects the outside oscillation resistance link of timing controlled chip, and the output of logical operation module connects the output of timing controlled chip.
5. timing controlled chip according to claim 1, is characterized in that, the model of described timing controlled chip is LC3611.
6. a battery charger, is characterized in that, comprising: the first resistance, the second resistance, the 3rd resistance, triode, battery interface and the timing controlled chip as described in claim 1-5 any one; The outside oscillation resistance link of described timing controlled chip connects the positive pole of battery interface by the first resistance, the external signal input terminals of described timing controlled chip connects the negative pole of battery interface, the power input of described timing controlled chip connects the positive pole of battery interface, the output of described timing controlled chip passes through the base stage of the 3rd resistance connecting triode, the collector electrode of described triode connects the negative pole of battery interface, the grounded emitter of described triode by the second resistance.
7. battery charger according to claim 6, is characterized in that, also comprises: the 4th resistance and light-emitting diode, and the output of described timing controlled chip also passes through the positive pole of the 4th resistance connecting luminous diode, the minus earth of light-emitting diode.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520699747.0U CN204906346U (en) | 2015-09-10 | 2015-09-10 | Timing control chip and battery charging circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520699747.0U CN204906346U (en) | 2015-09-10 | 2015-09-10 | Timing control chip and battery charging circuit |
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| CN204906346U true CN204906346U (en) | 2015-12-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105141297A (en) * | 2015-09-10 | 2015-12-09 | 深圳市霍尔芯电子有限公司 | Timing control chip, control method thereof and battery charging circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105141297A (en) * | 2015-09-10 | 2015-12-09 | 深圳市霍尔芯电子有限公司 | Timing control chip, control method thereof and battery charging circuit |
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