CN204905262U - SOI device with asymmetric trap and back of body bars retreated - Google Patents

Abstract

The utility model provides a SOI device with asymmetric trap and back of body bars retreated. An example device can include: the SOI substrate is including basement substrate, buried insulating layer and SOI layer, the semiconductor device who forms on the SOI substrate, including the source region and the drain region that are arranged in the SOI layer and be located the source region and the drain region between the channel region, trap erroneous tendency source region or drain region one side are wherein retreated to the trap of retreating that is located the channel region below that forms in the SOI layer, and the out -of -the -way bars that form in the basement substrate, wherein, carry on the back bars and retreat the trap electric coupling. According to this disclosed embodiment, can form asymmetric RW in the SOI substrate. Utilize this kind of RW, can form thin barrier layer at the channel region, although the SOI layer maybe be thicker.

Description

There is the SOI device of asymmetric retrogressing trap and backgate

Technical field

The disclosure relates to semiconductor applications, more specifically, relates to semiconductor-on-insulator (SOI) device that one has asymmetric retrogressing trap (RetrogradeWell, RW) and backgate.

Background technology

Exhaust (FD) semiconductor-on-insulator (SOI) field-effect transistor (FET) device completely and there is some advantages, such as, reduce power consumption and reduce electric leakage etc.Due to warpage (Kink) effect can be eliminated, so FDSOI device can suppress short-channel effect well and realize close to desirable sub-threshold slope.

Such as, but FDSOI device needs very thin soi layer, and about 10-20nm, exhausting completely.This causes too responsive to for Si loss the difficulty of soi layer THICKNESS CONTROL in process.In addition, thin soi layer adds non-essential resistance, and because this reducing device performance.

Utility model content

Object of the present disclosure is to provide one to have the SOI device of asymmetric retrogressing trap (RW) and backgate at least in part.

According to an aspect of the present disclosure, provide a kind of SOI device with asymmetric retrogressing trap and backgate, comprising: SOI substrate, comprise base substrate, buried insulating layer and soi layer; The semiconductor device formed on soi substrates, comprises source region in soi layer and drain region and the channel region between source region and drain region; The retrogressing trap be positioned at below channel region formed in soi layer, wherein retreats trap deflection source region or side, drain region; And the backgate formed in base substrate, wherein, backgate and the electric coupling of retrogressing trap.

According to embodiment of the present disclosure, asymmetric RW can be formed in SOI substrate.Utilize this RW, thinner depletion layer can be formed in channel region, although soi layer may be thicker.On the other hand, by the backgate with RW electric coupling, can the threshold voltage of control device.And asymmetric RW can reduce the interband Tunneling leakage current of the drain region apart from each other with it or side, source region.

Accompanying drawing explanation

By referring to the description of accompanying drawing to disclosure embodiment, above-mentioned and other objects of the present disclosure, feature and advantage will be more clear, in the accompanying drawings:

Fig. 1-10 diagrammatically illustrates the sectional view manufactured according to the flow process of the SOI device of disclosure embodiment;

Figure 11 is the sectional view of the SOI device diagrammatically illustrated according to disclosure embodiment.

Embodiment

Below, with reference to the accompanying drawings embodiment of the present disclosure is described.But should be appreciated that, these describe just exemplary, and do not really want to limit the scope of the present disclosure.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present disclosure.

Various structural representations according to disclosure embodiment shown in the drawings.These figure not draw in proportion, wherein in order to the object of clear expression, are exaggerated some details, and may eliminate some details.The shape of the various regions shown in figure, layer and the relative size between them, position relationship are only exemplary, in reality may due to manufacturing tolerance or technical limitations deviation to some extent, and those skilled in the art can design the regions/layers with difformity, size, relative position in addition needed for actual.

In context of the present disclosure, when one deck/element is called be positioned at another layer/element " on " time, this layer/element can be located immediately on this another layer/element, or can there is intermediate layer/element between them.In addition, if one to be positioned at towards middle one deck/element another layer/element " on ", so when turn towards time, this layer/element can be positioned at this another layer/element D score.

Figure 11 is the sectional view of semiconductor-on-insulator (SOI) device diagrammatically illustrated according to disclosure embodiment.

As shown in figure 11, SOI substrate can be comprised according to the SOI device 100 of this embodiment.This SOI substrate can comprise base substrate 102, buried insulating layer 104 and soi layer 106 (see Fig. 1).Such as, base substrate 102 can comprise semi-conducting material as Si, and buried insulating layer 104 can comprise dielectric as SiO ₂, thickness is about 10-50nm, and soi layer 106 can comprise semi-conducting material as Si, and thickness is about 15-150nm.In this embodiment, the thickness of soi layer 106 is thicker, thus generally (such as, when not forming RW as described below) can not form FD device.At this, be described for silicon based material.But it is pointed out that the disclosure is not limited thereto.Base substrate 102 and soi layer 106 can comprise other semi-conducting materials outside Si, and both can comprise different semi-conducting materials.

This SOI device 100 can also be included in the semiconductor device that soi layer is formed, as FET.Particularly, this semiconductor device can comprise source region and the drain region 126 of the stacking and stacking relative both sides of soi layer grid of the grid be arranged on soi layer.Grid are stacking can comprise gate dielectric layer 132 and grid conductor layer 134.Such as, gate dielectric layer 132 can comprise high-K gate dielectric, as HfO ₂deng, thickness is about 1-4nm; Grid conductor layer 134 can comprise metal gate conductor, and as TiN etc., thickness is about 1-10nm.Work function regulating course (not shown) can also be set between gate dielectric layer 132 and grid conductor layer 134.Source region and drain region 126 can N-shaped doping (for N-shaped device) or p-types doping (for p-type device).In addition, soi layer itself (gently) can be doped to p-type (for N-shaped device) or N-shaped (for p-type device).Channel region (not shown) extends between source region and drain region.Stacking by grid, the conduction and cut-off of channel region can be controlled.

In the following embodiments, be described for p-type device.But it is pointed out that the disclosure is not limited thereto, by suitably changing doping type, going for N-shaped device equally.

(particularly, in soi layer 106) below channel region (in other words, the stacking below of grid) in SOI substrate, can be formed and retreat trap (RW) 130.The doping type of RW130 can be contrary with source/drain region doping type.Particularly, RW130 can comprise p-type doped region (for N-shaped device) in soi layer or N-shaped doped region (for p-type device), and doping content is such as about 5 × 10 ¹⁶/ cm ³-5 × 10 ¹⁹/ cm ³.Due to the existence of RW130, although soi layer 106 may be thicker, also thinner depletion layer can be realized in channel region, thus boost device performance reduce short-channel effect.As described below, RW130 is asymmetrical, that is, be not positioned at immediately below channel region, but deflection source region or side, drain region.This asymmetrical RW can reduce the interband Tunneling leakage current of the drain region apart from each other with it or side, source region.Such as, when RW130 is partial to side, source region, the leakage current between drain region and body can be reduced.At this, so-called amesiality, indicate for opposite side, nearer apart from this side.Such as, when being partial to side, source region, trap distance source region (distance such as, between the core of trap and the core in source region) is nearer, and distance drain region (distance such as, between the core of trap and the core in drain region district) is far away.

According to another embodiment of the present disclosure, RW130 can also extend in buried insulating layer 104 and base substrate 102 further (in figure and not shown).In this case, RW130 can form the doping of low concentration trap in soi layer 106 and buried insulating layer 104, and can form the doping of high concentration trap in base substrate 102.Such as, RW130 can form delta doping in base substrate 102.So, can the structure of falling dopant well be formed.This can reduce the device threshold voltage change caused because soi layer thickness changes further.

This SOI device 100 can also be included in the backgate 118-1 formed in base substrate 102.Usually, the doping type of backgate 118-1 can be contrary with source/drain region doping type.Such as, for p-type device, backgate 118-1 can comprise the N-shaped doped region in base substrate 102; And for N-shaped device, backgate 118-1 can comprise the p-type doped region in base substrate 102.In this example (p-type device), backgate 118-1 is depicted as N-shaped doping.Backgate 118-1 can be formed as near (such as, directly adjoining) buried insulating layer 104.Backgate 118-1 can with RW130 electric coupling.So, can backgate be passed through, affect the electromotive force of RW130, thus change the threshold voltage of device.

Such as, backgate 118-1 can form ground plane by heavy doping, and under channel region, interface is in accumulation area to reduce tagma leakage current.Such as, backgate adds a reverse bias, can threshold voltage be improved, thus reduce leakage current.By the electric coupling of back gate voltage and RW, can adjusting threshold voltage and transistor characteristic, realize effective power management and performance boost, comprise possible dynamic threshold voltage adjustment.

This SOI device 100 can also be included in the contact site 136-1 in source region and the drain region 126 and contact site 136-2 to backgate 118-1.By respectively these contact sites, can to source region, drain region and backgate apply required voltage.

In addition, this SOI device 100 can also comprise isolation part 116, such as isolation part STI between device _dand isolation part STI between backgate _b.The position of isolation part can be determined according to device layout layout.

Isolation part STI between backgate _bsOI substrate can be divided into different regions (see Fig. 6, first area and second area), backgate in each region (such as, 118-1 in first area and the 118-3 in second area) can extend continuously, thus the semiconductor device formed in this region can share identical backgate.Backgate between zones of different such as 118-1 and 118-3 can have different doping types, and can by isolation part STI between backgate _band it is electrically isolated from one.In order to strengthen the electric isolution between backgate, doped region 118-2 and 118-4 contrary with its doping type can also be set below backgate 118-1 and 118-3.Adjacent doped region 118-2 and 118-4 can between backgate isolation part STI _bbelow is adjacent to each other.Like this, reverse pn can be had between backgate 118-1 and 118-3 and tie, thus can electric isolution well between them.

Isolation part STI between device _drespective regions (such as, first area, see Fig. 6) can be divided into different device areas (see Fig. 6).One or more semiconductor device can be formed in corresponding device region, and the semiconductor device in each device area can with the semiconductor device electric isolution in other device areas.In this embodiment, isolation part STI between device _dsoi layer can be run through.

Below, with reference to Fig. 1-10, a kind of exemplary fabrication process of above-mentioned SOI device is described.In the following description, the material etc. for each layer, region, structure no longer describes in detail, can with reference to the description above in conjunction with Figure 11.

As shown in Figure 1, SOI substrate is provided.This SOI substrate comprises base substrate 102, buried insulating layer 104 and soi layer 106.

Next, according to device layout layout, isolation part can be formed.Isolation part such as can be passed through to form groove in the substrate, and to filling dielectric in groove as oxide (such as, SiO ₂) formed.This such as can carry out as follows.

Particularly, as shown in Figure 2, hard mask layer can be formed in SOI substrate (particularly, soi layer 106).Such as, can nitride (such as, the silicon nitride) layer 110 of deposition thickness to be the oxide skin(coating) 108 of about 5-20nm and thickness be about 50-150nm successively.On hard mask layer, photoresist 112 can be formed.By operations such as exposure, developments, photoresist 112 can be patterned into and expose the region corresponding with the isolation part that will be formed.

Then, as shown in Figure 3, with the photoresist 112 after composition for mask, successively selective etch is carried out, as reactive ion etching (RIE) to hard mask layer (comprising nitride layer 110 and oxide skin(coating) 108), soi layer 106.Etching can stop at buried insulating layer 104.So, obtain the groove T for isolating between device _d.Afterwards, photoresist 112 can be removed.

Subsequently, as shown in Figure 4, photoresist 114 can be formed further in the structure shown in Fig. 3, and by device layout layout, its composition is exposed the region corresponding with isolation part between the backgate that will be formed (in that region, define the groove of certain depth, as previously described in connection with figure 3).

Then, as shown in Figure 5, with the photoresist 114 after composition for mask, successively selective etch is carried out to buried insulating layer 104 and base substrate 102, as reactive ion etching (RIE).Etching can enter certain depth in base substrate 102 (such as, being deeper than the back gate region that will be formed).Due to the existence of hard mask layer, this etching is equivalent to (being exposed by the photoresist 114) groove obtained described in above composition graphs 3 to deepen further.So, obtain the groove T for isolating between backgate _b.Afterwards, photoresist 114 can be removed.

Then, as shown in Figure 6, the groove T that can obtain as mentioned above _dwith groove T _bmiddle filling dielectric material as oxide, to form device interval respectively from STI _dand isolation STI between backgate _b.They can be referred to as isolation part 116.This filling such as can pass through structure (removing photoresist 114) the upper deposit dielectric material shown in Fig. 5, to fill groove wherein completely.Then, planarization can be carried out, such as chemico-mechanical polishing (CMP).CMP can stop at soi layer 106.So hard mask layer is also removed.Isolation part 116 defines active area.

As shown in Figure 6, by isolation STI between backgate _b, SOI substrate can be divided into different regions, as illustrated in the drawing first area and second area.In each region, as described below, the backgate extended continuously can be formed.Backgate respective in adjacent area can by isolation STI between backgate _band be isolated from each other.In each region (such as, illustrated first area), by isolation STI between device _d, SOI substrate (particularly, soi layer 106) can be divided into different device areas.One or more device can be formed as FET in each device area.The device formed in variant device area in the same area can share the backgate formed for this region.

After forming isolation part as mentioned above, element manufacturing can be carried out.

Such as, as shown in Figure 7, can ion implantation be passed through, in base substrate 102, form backgate 118-1 and 118-3.In this embodiment, by controlling the energy of ion implantation, backgate can be formed as be in base substrate 102, thus directly adjoin with buried insulating layer 104.In addition, the energy of ion implantation can be controlled, make the bottom surface of backgate be not less than isolation STI between backgate _bbottom surface, to realize good isolation.Figure 7 illustrates backgate 118-1 be N-shaped doping and backgate 118-3 be p-type doping example, but the disclosure is not limited thereto.Such as, backgate 118-1 can be adulterated by p-type and backgate 118-3 can be adulterated by N-shaped, or they can be doped to identical type.

Advantageously, in order to isolate better between backgate, the contrary well region of doping type with it can also be formed below backgate.Such as, as shown in Figure 7, the well region 118-2 of p-type can be formed below the backgate 118-1 of N-shaped, the well region 118-4 of N-shaped can be formed below the backgate 118-3 of p-type.These two well regions can extend and exceed isolation STI between backgate _bbottom surface, thus between backgate isolation STI _bbelow is adjacent.So, between the backgate 118-1 and the backgate 118-3 of p-type of N-shaped, reverse pn can be had and tie, they can be isolated better.

Then, as shown in Figure 8, semiconductor device can be formed in device area.Such as, in this device area, sacrificial gate can above be formed at substrate (particularly, soi layer) stacking.Sacrificial gate is stacking can comprise sacrificial gate dielectric layer 120 and sacrificial gate conductor layer 122.Sacrificial gate dielectric layer 120 can comprise oxide, and thickness is about 0.5-5nm; Sacrificial gate conductor layer 122 can comprise polysilicon, and thickness is about 20-200nm.Sacrificial gate can be stacked as basis, in soi layer, carry out extension area injection, and can haloing injection be carried out.Then, side wall 124 can be formed on the sidewall that sacrificial gate is stacking.Side wall 124 can comprise nitride, and width is about 5-50nm.Then, can sacrificial gate heap superimposition side wall be mask, carry out source/drain injection.Can anneal, to activate the ion of injection.So, in soi layer, in the stacking relative both sides of sacrificial gate, source region and drain region 126 can be formed.Advantageously, the whole thickness of soi layer can be run through in source region and drain region 126.Channel region (not shown) can be formed between source region and drain region.

Although the foregoing describe the concrete example forming device, the disclosure is not limited thereto.There is various ways to form semiconductor device in this area.

Then, as shown in Figure 9, in the structure shown in Fig. 8, can pass through such as deposit and then carry out planarization, form zone isolation layer 128.Zone isolation layer 128 can comprise oxide.Planarization can stop at side wall 124, so, expose sacrificial gate stacking.Sacrificial gate can be removed at least partially stacking, such as sacrificial gate conductor layer 122.When sacrificial gate conductor layer 122 comprises polysilicon, it can carry out wet method by such as TMAH solution and remove.Now, sacrificial gate dielectric layer 120 can retain, to protect the surface of soi layer in the ion implantation of carrying out subsequently.Like this, inside side wall 124, groove is left.As described in the arrow in figure, angle-tilt ion injection can be carried out by this groove with the direction tilted relative to substrate surface, retreat trap (RW) 130 to be formed below channel region.RW130 can with the backgate 118-1 electric coupling of below.Like this, RW130 can be partial to source region or side, drain region and (in the example of figure 9, be partial to left side, such as side, source region; Certainly, by changing the angle of inclination of ion implantation, RW130 also can be made to be partial to right side).

In the example of figure 9, show RW130 and be only formed in example in soi layer 106.But the disclosure is not limited thereto, such as, by increasing the energy of ion implantation, RW130 can further with extend in buried insulating layer 104 and base substrate 102.In this case, RW130 can form the doping of low concentration trap in soi layer 106 and buried insulating layer 104, and can form the doping of high concentration trap in base substrate 102.Such as, RW130 can form delta doping in base substrate 102.So, can the structure of falling dopant well be formed.

Subsequently, as shown in Figure 10, sacrificial gate dielectric layer 120 can be removed, and form gate dielectric layer 132 and grid conductor layer 134 successively in groove inside side wall 124.Those skilled in the art will know that various ways is to realize this replacement gate process, does not repeat them here.

In addition, as shown in figure 11, various contact site can also be formed, such as, arrive the contact site 136-1 in source region and the drain region 126 and contact site 136-2 to backgate 118-1.This contact site such as can by forming contact hole, and then filled conductive material such as Cu or W is formed in the contact hole.By these contact sites, suitable voltage can be applied to source region and drain region 126 and backgate 118-1.Due to the electric coupling between backgate 118-1 and RW130, can apply biased to RW130 by backgate 118-1.

In the above description, the ins and outs such as composition, etching for each layer are not described in detail.But it will be appreciated by those skilled in the art that and by various technological means, the layer of required form, region etc. can be formed.In addition, in order to form same structure, those skilled in the art can also design the not identical method with method described above.In addition, although respectively describing each embodiment above, this is not also meaning that the measure in each embodiment can not advantageously be combined.

Above embodiment of the present disclosure is described.But these embodiments are only used to the object illustrated, and are not intended to limit the scope of the present disclosure.The scope of the present disclosure is by claims and equivalents thereof.Do not depart from the scope of the present disclosure, those skilled in the art can make multiple substituting and amendment, and these substitute and amendment all should fall within the scope of the present disclosure.

Claims (7)

1. there is a semiconductor-on-insulator SOI device for asymmetric retrogressing trap and backgate, comprising:

SOI substrate, comprises base substrate, buried insulating layer and soi layer;

The semiconductor device formed on soi substrates, comprises source region in soi layer and drain region and the channel region between source region and drain region;

The retrogressing trap be positioned at below channel region formed in soi layer; And

The backgate formed in base substrate,

Wherein, backgate and the electric coupling of retrogressing trap,

It is characterized in that, retreat trap deflection source region or side, drain region.

2. the SOI device with asymmetric retrogressing trap and backgate according to claim 1, is characterized in that, described retrogressing trap deflection side, source region.

3. the SOI device with asymmetric retrogressing trap and backgate according to claim 1 and 2, characterized by further comprising: to the contact site of backgate, applies voltage by this contact site to backgate and retrogressing trap.

4. the SOI device with asymmetric retrogressing trap and backgate according to claim 1 and 2, characterized by further comprising: the first isolation structure, SOI substrate is divided into different regions,

Wherein, the multiple semiconductor device sharing identical backgate are formed in each area.

5. the SOI device with asymmetric retrogressing trap and backgate according to claim 4, characterized by further comprising: the second isolation structure, described region is divided into different device areas, and wherein said multiple semiconductor device is formed in described different device area respectively.

6. the SOI device with asymmetric retrogressing trap and backgate according to claim 1, it is characterized in that, retreating trap extends in buried insulating layer and base substrate further, wherein retreat trap in soi layer and buried insulating layer, form the doping of low concentration trap, and in base substrate, form the doping of high concentration trap.

7. the SOI device with asymmetric retrogressing trap and backgate according to claim 6, is characterized in that, retreats trap in base substrate, forms delta doping.