CN105633141B - SOI device and its manufacturing method - Google Patents
SOI device and its manufacturing method Download PDFInfo
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- CN105633141B CN105633141B CN201510254364.7A CN201510254364A CN105633141B CN 105633141 B CN105633141 B CN 105633141B CN 201510254364 A CN201510254364 A CN 201510254364A CN 105633141 B CN105633141 B CN 105633141B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 17
- 239000012212 insulator Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 150000002927 oxygen compounds Chemical class 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2229/00—Indexing scheme for semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, for details of semiconductor bodies or of electrodes thereof, or for multistep manufacturing processes therefor
Abstract
Provide a kind of SOI device and its manufacturing method.One example device may include: SOI substrate, including base substrate, buried insulating layer and soi layer；The semiconductor devices formed on soi substrates, including the source region and drain region that are located in soi layer and the channel region between source region and drain region；The retrogressing trap being located at below channel region formed in soi layer, buried insulating layer and base substrate, wherein retreat trap and form the doping of low concentration trap in soi layer and buried insulating layer, and form the doping of high concentration trap in base substrate；And the backgate formed in base substrate, wherein backgate is electrically coupled with trap is retreated.
Description
Technical field
This disclosure relates to which semiconductor field, has more particularly, to one kind and retreats trap (Retrograde Well, RW)
With semiconductor-on-insulator (SOI) device and its manufacturing method of backgate.
Background technique
Completely depleted (FD) semiconductor-on-insulator (SOI) field effect transistor (FET) device has the advantages that several, example
Such as, reduce power consumption and reduce electric leakage etc..Since warpage (Kink) effect can be eliminated, so FD SOI device can press down well
Short-channel effect processed is simultaneously realized close to ideal sub-threshold slope.
But FD SOI device needs very thin soi layer, for example, about 10-20nm is allowed it to completely depleted.This
Lead to the difficulty to soi layer thickness control in process and Si is lost too sensitive.In addition, thin soi layer increases outside
Portion's resistance, and therefore reduce device performance.
Summary of the invention
The purpose of the disclosure is at least partly to provide a kind of SOI device and its system for having and retreating trap (RW) and backgate
Make method.
According to one aspect of the disclosure, a kind of SOI device is provided, comprising: SOI substrate, including base substrate, embedment
Insulating layer and soi layer；The semiconductor devices formed on soi substrates including the source region and drain region that are located in soi layer and is located at
Channel region between source region and drain region；After what is formed in soi layer, buried insulating layer and base substrate is located at below channel region
Move back trap, wherein retreat trap and form the doping of low concentration trap in soi layer and buried insulating layer, and formed in base substrate highly concentrated
Spend trap doping；And the backgate formed in base substrate, wherein backgate is electrically coupled with trap is retreated.
According to another aspect of the present disclosure, a kind of method for manufacturing SOI device is provided, comprising: for including substrate liner
Bottom, buried insulating layer and soi layer SOI substrate, backgate is formed in base substrate；Sacrificial gate is formed on soi substrates to stack,
And source region and drain region are formed in soi layer, channel region is defined between source region and drain region；Remove sacrificial gate stacks at least one
Part, and via the space as obtained from at least part of removal, in soi layer, buried insulating layer and base substrate
It is formed and retreats trap, wherein retreated trap in soi layer and buried insulating layer and form the doping of low concentration trap, and formed in base substrate
The doping of high concentration trap, and retreat trap and be electrically coupled with backgate；And it forms device gate and stacks.
In accordance with an embodiment of the present disclosure, RW can be formed in SOI substrate.Using this RW, can be formed in channel region
Relatively thin depletion layer, although soi layer may be thicker.On the other hand, by the backgate being electrically coupled with RW, it can control the threshold of device
Threshold voltage.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present disclosure, the above-mentioned and other purposes of the disclosure, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1-10 is to diagrammatically illustrate manufacture according to the sectional view of the process of the SOI device of the embodiment of the present disclosure；
Figure 11 is to diagrammatically illustrate the sectional view of the SOI device according to the embodiment of the present disclosure.
Specific embodiment
Hereinafter, will be described with reference to the accompanying drawings embodiment of the disclosure.However, it should be understood that these descriptions are only exemplary
, and it is not intended to limit the scope of the present disclosure.In addition, in the following description, descriptions of well-known structures and technologies are omitted, with
Avoid unnecessarily obscuring the concept of the disclosure.
The various structural schematic diagrams according to the embodiment of the present disclosure are shown in the attached drawings.These figures are not drawn to scale
, wherein some details are magnified for the purpose of clear expression, and some details may be omitted.It is shown in the drawings
Various regions, the shape of layer and relative size, positional relationship between them are merely exemplary, in practice may be due to system
It makes tolerance or technical restriction and is deviated, and those skilled in the art may be additionally designed as required with difference
Shape, size, the regions/layers of relative position.
In the context of the disclosure, when one layer/element is referred to as located at another layer/element "upper", which can
May exist intermediate layer/element on another layer/element or between them.In addition, if in a kind of direction
In one layer/element be located at another layer/element "upper", then when turn towards when, which can be located at another layer/member
Part "lower".
Figure 11 is to diagrammatically illustrate the sectional view of semiconductor-on-insulator (SOI) device according to the embodiment of the present disclosure.
As shown in figure 11, SOI device 100 may include SOI substrate according to this embodiment.The SOI substrate may include
Base substrate 102, buried insulating layer 104 and soi layer 106 (referring to Fig. 1).For example, base substrate 102 may include semiconductor material
Material such as Si, buried insulating layer 104 may include dielectric such as SiO2, with a thickness of about 10-50nm, soi layer 106 may include partly leading
Body material such as Si, with a thickness of about 15-150nm.In this embodiment, the thickness of soi layer 106 is thicker, thus (example under normal circumstances
Such as, in the case where no formation RW as described below) it not will form FD device.Here, being described by taking silicon systems material as an example.
It should be noted however that the present disclosure is not limited thereto.Base substrate 102 and soi layer 106 may include that other except Si are partly led
Body material, and the two may include different semiconductor material.
The SOI device 100 can also include the semiconductor devices formed on soi layer, such as FET.Specifically, the semiconductor
Device may include source region and the drain region 126 that grid stack opposite sides in the grid stacking being located on soi layer and soi layer.Grid heap
Folded may include gate dielectric layer 132 and grid conductor layer 134.For example, gate dielectric layer 132 may include high-K gate dielectric, such as HfO2
Deng with a thickness of about 1-4nm；Grid conductor layer 134 may include metal gate conductor, such as TiN, with a thickness of about 1-10nm.Gate medium
Work function regulating course (not shown) can also be set between layer 132 and grid conductor layer 134.Source region and drain region 126 can be with n-type dopings
(for n-type device) or p-type doping (for p-type device).In addition, soi layer itself can (light) be doped to p-type (for N-shaped
Device) or N-shaped (for p-type device).Channel region (not shown) extends between source region and drain region.It is stacked by grid, it can be with
Control the conduction and cut-off of channel region.
In the following embodiments, it is described for p-type device.It should be noted however that the present disclosure is not limited thereto, lead to
It crosses and suitably changes doping type, may be equally applicable for n-type device.
In SOI substrate (specifically, in soi layer 106, buried insulating layer 104 and base substrate 102) under channel region
Side's (in other words, grid stack lower section), could be formed with and retreat trap (RW) 130.RW 130 is in soi layer 106 and buried insulating layer 104
In can form low concentration trap doping (showing in the accompanying drawings with spot), and high concentration can be formed in base substrate 102
Trap adulterates (showing in the accompanying drawings with shadow region).For example, RW 130 can form delta doping in base substrate 102.In
It is that can be formed and adulterate well structure.Device threshold voltage becomes caused by this can be further decreased because of the change of soi layer thickness
Change.The doping type of RW 130 can be opposite with source/drain region doping type.Specifically, RW 130 may include soi layer, embedment
P-type doping area (for n-type device) or n-type doping area (for p-type device) in insulating layer and base substrate, doping concentration
E.g., about 5 × 1016/cm3-5×1019/cm3.It, can also be although soi layer 106 may be thicker due to the presence of RW 130
Channel region realizes relatively thin depletion layer, to promote device performance and reduce short-channel effect.As described below, RW 130 can be certainly
In alignment with channel region.
The SOI device 100 can also include the backgate 118-1 formed in base substrate 102.In general, backgate 118-1
Doping type can be opposite with source/drain region doping type.For example, backgate 118-1 may include base substrate for p-type device
N-type doping area in 102；And for n-type device, backgate 118-1 may include the p-type doping area in base substrate 102.At this
In example (p-type device), backgate 118-1 is shown as n-type doping.Backgate 118-1 can be formed adjacent to (for example, directly adjacent
Connect) buried insulating layer 104.Backgate 118-1 can be electrically coupled with RW 130.Thus it is possible to influence the electricity of RW 130 by backgate
Gesture, to change the threshold voltage of device.
For example, backgate 118-1 can form ground plane by heavy doping, interface is in accumulation area to reduce under channel region
Body area leakage current.For example, adding a reverse bias in backgate, threshold voltage can be improved, to reduce leakage current.Pass through back
Gate voltage and RW's is electrically coupled, and adjustable threshold voltage and transistor characteristic realize effective power management and performance boost,
It is adjusted including possible dynamic threshold voltage.
The SOI device 100 can also include to source region and the contact portion 136-1 in drain region 126 and connecing to backgate 118-1
Contact portion 136-2.By these contact portions respectively, voltage needed for can applying to source region, drain region and backgate.
In addition, the SOI device 100 can also include isolation part 116, such as isolation part STI between deviceDIt is isolated between backgate
Portion STIB.It the position of isolation part can be depending on device design layout.
Isolation part STI between backgateBSOI substrate can be divided into different regions (referring to Fig. 6, first area and the secondth area
Domain), backgate in each region (for example, 118-3 in 118-1 and second area in first area) can continuously prolong
It stretches, so that the semiconductor devices formed in the region can share identical backgate.Backgate such as 118-1 between different zones and
118-3 can have different doping types, and can pass through isolation part STI between backgateBAnd it is electrically isolated from one.In order to reinforce carrying on the back
The doped region 118-2 opposite with its doping type can also be arranged in electric isolution between grid below backgate 118-1 and 118-3
And 118-4.Adjacent doped region 118-2 and 118-4 can between backgate isolation part STIBLower section is adjacent to each other.In this way, backgate
It can have reverse p-n junctions between 118-1 and 118-3, to can be electrically isolated well between them.
Isolation part STI between deviceDCorresponding region (for example, first area, referring to Fig. 6) can be divided into different device regions
Domain (referring to Fig. 6).One or more semiconductor devices can be formed in corresponding device region, and partly leading in each device area
Body device can be electrically isolated with the semiconductor devices in other device areas.In this embodiment, isolation part STI between deviceDIt can
To run through soi layer.
Hereinafter, Fig. 1-10 will be referred to, a kind of exemplary fabrication process of above-mentioned SOI device is described.In the following description, for
Each layer, region, material of structure etc. are no longer described in detail, and are referred to the description of above combination Figure 11.
As shown in Figure 1, providing SOI substrate.The SOI substrate includes base substrate 102, buried insulating layer 104 and soi layer
106。
Next, isolation part can be formed according to device design layout.Isolation part for example can be by forming in the substrate
Groove, and into groove filling dielectric such as oxide (for example, SiO2) formed.This can for example be carried out as follows.
Specifically, as shown in Fig. 2, hard mask layer can be formed on SOI substrate (specifically, soi layer 106).For example, can
With oxide skin(coating) 108 that successively deposition thickness is about 5-20nm and with a thickness of the nitride (for example, silicon nitride) of about 50-150nm
Layer 110.On hard mask layer, photoresist 112 can be formed.It can be by the operation such as expose, develop, by 112 composition of photoresist
For expose with by the corresponding region in isolation part to be formed.
Then, as shown in figure 3, being mask with the photoresist 112 after composition, to hard mask layer (including 110 He of nitride layer
Oxide skin(coating) 108), soi layer 106 successively carry out selective etch, such as reactive ion etching (RIE).Etching, which can stop at, buries
Enter insulating layer 104.Then, it has obtained for the groove T being isolated between deviceD.Later, photoresist 112 can be removed.
Then, it as shown in figure 4, photoresist 114 is further formed in structure that can be shown in Fig. 3, and is designed by device
Layout is patterned exposing and (in that region, has formd with by the corresponding region in isolation part between backgate to be formed
The groove of certain depth, as previously described in connection with figure 3).
Then, as shown in figure 5, being mask with the photoresist 114 after composition, to buried insulating layer 104 and base substrate 102
Selective etch is successively carried out, such as reactive ion etching (RIE).Etching can enter certain depth (example in base substrate 102
Such as, it is deeper than back gate region to be formed).Due to the presence of hard mask layer, this etching, which is equivalent to, to be obtained in conjunction with described in Fig. 3 above
To (be photo-etched glue 114 exposing) groove further deepen.Then, it has obtained for the groove T being isolated between backgateB.Later,
Photoresist 114 can be removed.
It then, as shown in fig. 6, can be in the groove T obtained as described aboveDWith groove TBMiddle filling dielectric material such as oxygen
Compound, to be respectively formed isolation STI between deviceDThe isolation STI between backgateB.They may be collectively referred to as isolation part 116.This filling
Such as it can be by deposit dielectric material in structure (removal photoresist 114) shown in Fig. 5, to be filled up completely ditch therein
Slot.It is then possible to carry out planarization process, such as chemically mechanical polishing (CMP).CMP can stop at soi layer 106.Then,
Hard mask layer is also removed.Isolation part 116 defines active area.
As shown in fig. 6, passing through isolation STI between backgateB, SOI substrate can be divided into different regions, and as illustrated in the drawing
One region and second area.In each region, as described below, the backgate being extended continuously can be formed.It is respective in adjacent area
Backgate can pass through isolation STI between backgateBAnd it is isolated from each other.In each region (for example, first area of diagram), pass through device
Between isolation STID, SOI substrate (specifically, soi layer 106) can be divided into different device areas.It can be in each device area
Form one or more devices such as FET.The device formed in variant device area in the same area can be shared for the area
The backgate that domain is formed.
It, can be with device was fabricated after forming isolation part as described above.
For example, as shown in fig. 7, backgate 118-1 and 118-3 can be formed in base substrate 102 by ion implanting.
In this embodiment it is possible to be formed as backgate in base substrate 102 by the energy of control ion implanting, thus with
Buried insulating layer 104 abuts directly against.Furthermore, it is possible to the energy of ion implanting be controlled, so that the bottom surface of backgate is not less than between backgate
Isolation STIBBottom surface, to realize good isolation.It is shown in FIG. 7 that backgate 118-1 is n-type doping and backgate 118-3 is p-type
The example of doping, but the present disclosure is not limited thereto.For example, backgate 118-1 can be by p-type doping and backgate 118-3 can be by N-shaped
It adulterates or they can be doped to identical type.
Advantageously, in order to preferably be isolated between backgate, the opposite trap of doping type therewith can also be formed below backgate
Area.For example, as shown in fig. 7, the well region 118-2 of p-type can be formed below the backgate 118-1 of N-shaped, it can be in the backgate of p-type
The well region 118-4 of N-shaped is formed below 118-3.The two well regions can extend beyond isolation STI between backgateBBottom surface, thus
Isolation STI between backgateBLower section is adjacent.Then, it between the backgate 118-1 of N-shaped and the backgate 118-3 of p-type, can have reversed
Them are isolated preferably in pn-junction.
Then, as shown in figure 8, semiconductor devices can be formed in device area.For example, can be in the device area
In, sacrificial gate stacking is formed on substrate (specifically, soi layer).Sacrificial gate stacking may include sacrificing gate dielectric layer 120 and sacrificial
Domestic animal grid conductor layer 122.Sacrificing gate dielectric layer 120 may include oxide, with a thickness of about 0.5-5nm；Sacrificial gate conductor layer 122 can
To include polysilicon, with a thickness of about 20-200nm.Based on can stacking by sacrificial gate, extension area injection is carried out in soi layer, and
It can carry out haloing injection.It is then possible to form side wall 124 on the side wall that sacrificial gate stacks.Side wall 124 may include nitridation
Object, width are about 5-50nm.It is then possible to which sacrificial gate stacks and side wall is mask, source drain implant is carried out.It can anneal,
To activate the ion of injection.Then, in soi layer, the opposite sides that can be stacked in sacrificial gate forms source region and drain region 126.
Advantageously, source region and drain region 126 can run through the whole thickness of soi layer.Channel region (not shown) can be formed in source region and leakage
Between area.
Although but the present disclosure is not limited thereto the foregoing describe the specific example for forming device.There are a variety of sides for this field
Formula forms semiconductor devices.
Then, it as shown in figure 9, in structure that can be shown in Fig. 8, can be carried out for example, by deposit and then flat
Change, separation layer 128 between forming layer.Zone isolation layer 128 may include oxide.Planarization can stop at side wall 124, in
It is to expose sacrificial gate stacking.At least part of sacrificial gate stacking, such as sacrificial gate conductor layer 122 can be removed.It is sacrificing
In the case that grid conductor layer 122 includes polysilicon, wet process removal can be carried out for example, by TMAH solution.At this point, sacrificial gate is situated between
Matter layer 120 can retain, to protect the surface of soi layer in the ion implanting then carried out.In this way, in 124 inside of side wall
Leave groove.As described in the arrow in figure, ion implanting can be carried out by the groove, be retreated with being formed below channel region
Trap (RW) 130.RW 130 can be electrically coupled with the backgate 118-1 of lower section.Here, ion implanting can be approximately perpendicular to substrate table
The direction in face carries out.In this way, the groove that RW 130 can be self-aligned to 124 inside of side wall (then forms grid heap in the groove
It is folded, to be self-aligned to grid stacking, and therefore it is self-aligned to channel region).RW 130 is in soi layer 106 and buried insulating layer 104
The doping of low concentration trap can be formed, and the doping of high concentration trap can be formed in base substrate 102.For example, RW 130 can be
Delta doping is formed in base substrate 102.Well structure is adulterated thus it is possible to be formed.
Then, as shown in Figure 10, it can remove and sacrifice gate dielectric layer 120, and the successively shape in the groove of 124 inside of side wall
At gate dielectric layer 132 and grid conductor layer 134.Those skilled in the art will know that various ways realize this replacement gate process,
This is repeated no more.
In addition, as shown in figure 11, various contact portions, such as the contact portion 136-1 to source region and drain region 126 can also be formed
And the contact portion 136-2 to backgate 118-1.This contact portion for example can be by forming contact hole, then in the contact hole
Conductive material such as Cu or W are filled to be formed.By these contact portions, can apply to source region and drain region 126 and backgate 118-1
Voltage appropriate.Due to being electrically coupled between backgate 118-1 and RW 130, can be applied partially by backgate 118-1 to RW 130
It sets.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
Embodiment of the disclosure is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the present disclosure.The scope of the present disclosure is limited by appended claims and its equivalent.This public affairs is not departed from
The range opened, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in the disclosure
Within the scope of.
Claims (12)
1. a kind of semiconductor-on-insulator SOI device, comprising:
SOI substrate, including base substrate, buried insulating layer and soi layer；
The semiconductor devices formed on soi substrates including the source region and drain region that are located in soi layer and is located at source region and drain region
Between channel region；
The retrogressing trap being located at below channel region formed in soi layer, buried insulating layer and base substrate, wherein retreat trap and exist
The doping of low concentration trap is formed in soi layer and buried insulating layer, and the doping of high concentration trap is formed in base substrate；And
The backgate formed in base substrate,
Wherein, backgate is electrically coupled with trap is retreated.
2. SOI device according to claim 1, wherein the retrogressing trap is self-aligned to channel region.
3. SOI device according to claim 1 or 2, further includes: be connected to the contact portion of backgate, by the contact portion to
Backgate and retrogressing trap apply voltage.
4. SOI device according to claim 1 or 2, further includes: SOI substrate is divided into different areas by the first isolation structure
Domain,
Wherein, the multiple semiconductor devices for sharing identical backgate are formed in each area.
5. SOI device according to claim 4, further includes: the region is divided into different devices by the second isolation structure
Region, wherein the multiple semiconductor devices is respectively formed in the different device area.
6. SOI device according to claim 1, wherein retreat trap and form delta doping in base substrate.
7. a kind of method for manufacturing semiconductor-on-insulator SOI device, comprising:
For including base substrate, the SOI substrate of buried insulating layer and soi layer, backgate is formed in base substrate；
Sacrificial gate is formed on soi substrates to stack, and forms source region and drain region in soi layer, is limited between source region and drain region
Channel region；
At least part that sacrificial gate stacks is removed, and via the space as obtained from at least part of removal, in SOI
It is formed in layer, buried insulating layer and base substrate and retreats trap, wherein retreated trap in soi layer and buried insulating layer and form low concentration
Trap doping, and the doping of high concentration trap is formed in base substrate, and retreat trap and be electrically coupled with backgate；And
Device gate is formed to stack.
8. according to the method described in claim 7, forming retrogressing trap includes: with the direction substantially perpendicular to SOI substrate surface
Ion implanting is carried out into soi layer, buried insulating layer and base substrate, to obtain and the self aligned retrogressing trap of channel region.
9. according to the method described in claim 7, forming backgate includes: to carry out ion implanting in basad substrate.
10. the method according to any one of claim 7-9, further includes: formed enter in base substrate first every
From structure, which is divided into SOI substrate in different regions, and makes in backgate and another region in a region
Backgate be electrically isolated.
11. according to the method described in claim 10, further include: the second isolation structure for running through soi layer is formed, by the region
It is divided into different device areas.
12. according to the method described in claim 7, wherein, retreating trap and forming delta doping in base substrate.
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| US11482521B2 (en) * | 2020-02-06 | 2022-10-25 | Globalfoundries U.S. Inc. | Integrated circuit with P-N-P junction and vertically aligned field effect transistor, and method to form same |
| US11309435B2 (en) * | 2020-03-09 | 2022-04-19 | Globalfoundries U.S. Inc. | Bandgap reference circuit including vertically stacked active SOI devices |
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| US6686630B2 (en) * | 2001-02-07 | 2004-02-03 | International Business Machines Corporation | Damascene double-gate MOSFET structure and its fabrication method |
| US20090212363A1 (en) * | 2008-02-27 | 2009-08-27 | Advanced Micro Devices, Inc. | Method for forming a one-transistor memory cell and related structure |
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| CN204558469U (en) * | 2015-05-14 | 2015-08-12 | 中国科学院微电子研究所 | SOI device |
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| US20090212363A1 (en) * | 2008-02-27 | 2009-08-27 | Advanced Micro Devices, Inc. | Method for forming a one-transistor memory cell and related structure |
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