CN204904841U - Storage array and NOR flash memory memory that contains this storage array - Google Patents
Storage array and NOR flash memory memory that contains this storage array Download PDFInfo
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- CN204904841U CN204904841U CN201520429183.9U CN201520429183U CN204904841U CN 204904841 U CN204904841 U CN 204904841U CN 201520429183 U CN201520429183 U CN 201520429183U CN 204904841 U CN204904841 U CN 204904841U
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Abstract
The utility model relates to an integrated circuit field discloses a storage array and NOR flash memory memory that contains this storage array, this storage array including the memory cell array that is arranged in same trap and pseudo - cellular array and to trap provide voltage's trap driver, a serial communication port, the drain electrode of the information storage of memory cell array edge pipe with the drain electrode of managing with the dummy unit that the information storage pipe is adjacent of this edge among the pseudo - cellular array is connected, pseudo - cellular array's word line with the trap driver is connected. The interference that pseudo - cellular array received when this storage array and NOR flash memory memory that contains this storage array can reduce erasable memory cell array, and then can improve the threshold voltage vt's of memory cell array distribution uniformity to improve the precision that reads of data.
Description
Technical field
The utility model relates to integrated circuit fields, particularly, relates to a kind of storage array and the NOR flash memory storer comprising this storage array.
Background technology
In existing NOR (or non-) flash memories, the example arrangement of its storage array usually as depicted in figs. 1 and 2.Memory cell array 10 and dummy unit array 20,30 are arranged in same P trap 40, and the wordline WL of memory cell array 10 is used for the corresponding information storage tube of gating.Wordline (namely its control is deleted) floating (as shown in the storage array of Fig. 1) or the ground connection (as shown in the storage array of Fig. 2) of dummy unit array 20,30, and the source electrode of dummy unit array 20,30 is connected with the source electrode of memory cell array 10.P trap driver 60 provides voltage to P trap 40, and P trap 40 is arranged in dark N trap 50.
The shortcoming of the storage array shown in Fig. 1 and Fig. 2 is, when erasing memory unit array 10, dummy unit array 20,30 is easily interfered, and then the distribution of the threshold voltage vt of memory cell array 10 can be made inconsistent, and affects the reading accuracy of data.
Utility model content
The purpose of this utility model is to provide a kind of storage array and comprises the NOR flash memory storer of this storage array, interference when it can reduce erasing memory unit array suffered by dummy unit array, and then the distribution consistance of threshold voltage vt of memory cell array can be improved, and improve the reading accuracy of data.
To achieve these goals, the utility model provides a kind of storage array, this storage array comprises the memory cell array and dummy unit array that are arranged in same trap and the trap driver providing voltage to described trap, it is characterized in that, the drain electrode of the information storage tube of described memory cell array edge is connected with the drain electrode of dummy unit pipe adjacent with the information storage tube of this edge in described dummy unit array, and the wordline of described dummy unit array is connected with described trap driver.
Preferably, described trap is P type trap.
Preferably, described memory cell array and described dummy unit array are made up of floating-gate MOS tube.
The utility model also provides a kind of NOR flash memory storer, it is characterized in that, this NOR flash memory storer comprises above-mentioned storage array.
Pass through technique scheme, wordline due to dummy unit array is connected on the trap driver of the trap residing for it, therefore make the wordline of dummy unit array identical with the current potential of the trap residing for it, like this in the erasable process of memory cell array, potential difference (PD) between the wordline of dummy unit array and the trap residing for it remains zero, therefore the threshold voltage vt of dummy unit array can not be subject to the impact of the pressure reduction between the wordline of dummy unit array and the trap residing for it and step-down, and then leakage current can not be produced because of the reduction of the threshold voltage of dummy unit array, more can not affect the reading accuracy of data, and be connected with the drain electrode of dummy unit pipe adjacent with the information storage tube of this edge in described dummy unit array due to the drain electrode of the information storage tube of memory cell array edge, therefore, it is possible to guarantee the distribution consistance of the threshold voltage vt of memory cell array.
Other features and advantages of the utility model are described in detail in embodiment part subsequently.
Accompanying drawing explanation
Accompanying drawing is used to provide further understanding of the present utility model, and forms a part for instructions, is used from explanation the utility model, but does not form restriction of the present utility model with embodiment one below.In the accompanying drawings:
Fig. 1 is a kind of longitudinal profile schematic diagram of existing storage array;
Fig. 2 is another longitudinal profile schematic diagram of existing storage array;
Fig. 3 is the longitudinal profile schematic diagram of the storage array according to a kind of embodiment of the utility model;
Fig. 4 shows the position relationship between the wordline of the dummy unit array in same trap and the wordline of memory cell array; And
Fig. 5 is the circuit diagram of the storage array according to a kind of embodiment of the utility model.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in detail.Should be understood that, embodiment described herein, only for instruction and explanation of the utility model, is not limited to the utility model.
Fig. 3 shows the longitudinal profile schematic diagram of the storage array according to a kind of embodiment of the utility model.As shown in Figure 3, this storage array comprises the memory cell array 10 and dummy unit array 20 that are arranged in same trap 40, 30, this storage array also comprises the trap driver 60 providing voltage to described trap 40, it is characterized in that, the drain electrode of the information storage tube of the edge of described memory cell array 10 is connected (as the label 70 in Fig. 3 with the drain electrode of dummy unit pipe adjacent with the information storage tube of this edge in described dummy unit array 20 (30), shown in 80), described dummy unit array 20, the wordline (being also its control gate) of 30 is connected with described trap driver 60.
In addition, also show the wordline WL (being also grid) of described memory cell array 10 in Fig. 3, these wordline control the erasable control signal of described memory cell array 10 for receiving.
Like this, according in the technical solution of the utility model, by being in same trap 40, both sides are used as the dummy unit array 20 of dummy unit, the wordline of 30 is connected on the trap driver 60 of the trap 40 residing for it, dummy unit array 20 can be made, wordline and the trap 40 of 30 are in identical current potential, like this, in the erasable process of memory cell array 10, dummy unit array 20, potential difference (PD) between the wordline of 30 and trap 40 just remains zero, thus dummy unit array 20, the threshold voltage vt of 30 would not be subject to dummy unit array 20, the impact of the pressure reduction between the wordline of 30 and trap 40 and step-down, and then can not because of dummy unit array 20, the threshold voltage of 30 reduces and produces leakage current, more can not affect the reading accuracy of data.And, because the drain electrode of the information storage tube of the edge of memory cell array 10 is connected with the drain electrode of dummy unit pipe adjacent with the information storage tube of this edge in described dummy unit array 20 (30), therefore, it is possible to make the threshold voltage of memory cell array 10 distribute have good consistance.
Preferably, described trap 40 is P type trap.This P type trap is arranged in dark N trap 50.
Preferably, described memory cell array 10 and described dummy unit array 20,30 are made up of floating-gate MOS tube.Like this, the wordline of memory cell array 10 and described dummy unit array 20,30 is its control and deletes.
In addition, Fig. 4 schematically illustrates the position relationship between the wordline of the dummy unit array 20,30 in same trap 40 and the wordline of memory cell array 10.
Fig. 5 is the circuit diagram of the storage array according to a kind of embodiment of the utility model.As shown in Figure 5, the drain electrode that in dummy unit array 20, control gate is connected to the dummy unit pipe of DWL0 is connected with the drain electrode (i.e. its bit line) that wordline in memory cell array 10 is connected to the information storage tube of WL0, and the drain electrode that in dummy unit array 30, control gate is connected to the dummy unit pipe of DWLm is connected with the drain electrode (i.e. its bit line) that wordline in memory cell array 10 is connected to the information storage tube of WLm-1.The control gate of the dummy unit pipe in dummy unit array 20 and 30 is all connected to trap driver 60.Also schematically show the connected mode of the source S 0 ~ Sn-1 of information storage tube and dummy unit pipe in Fig. 5, wherein 16 or 32 or more source electrode can be linked together.
The utility model also provides a kind of NOR flash memory storer, it is characterized in that, this NOR flash memory storer comprises storage array recited above.
Below preferred implementation of the present utility model is described by reference to the accompanying drawings in detail; but; the utility model is not limited to the detail in above-mentioned embodiment; within the scope of technical conceive of the present utility model; can carry out multiple simple variant to the technical solution of the utility model, these simple variant all belong to protection domain of the present utility model.
In addition, also can carry out combination in any between various different embodiment of the present utility model, as long as it is without prejudice to thought of the present utility model, it should be considered as content disclosed in the utility model equally.
Claims (4)
1. a storage array, this storage array comprises the memory cell array and dummy unit array that are arranged in same trap and the trap driver providing voltage to described trap, it is characterized in that, the drain electrode of the information storage tube of described memory cell array edge is connected with the drain electrode of dummy unit pipe adjacent with the information storage tube of this edge in described dummy unit array, and the wordline of described dummy unit array is connected with described trap driver.
2. storage array according to claim 1, is characterized in that, described trap is P type trap.
3. storage array according to claim 1, is characterized in that, described memory cell array and described dummy unit array are made up of floating-gate MOS tube.
4. a NOR flash memory storer, is characterized in that, this NOR flash memory storer comprises the storage array in claims 1 to 3 described in arbitrary claim.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520429183.9U CN204904841U (en) | 2015-06-19 | 2015-06-19 | Storage array and NOR flash memory memory that contains this storage array |
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| CN201520429183.9U CN204904841U (en) | 2015-06-19 | 2015-06-19 | Storage array and NOR flash memory memory that contains this storage array |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116705086A (en) * | 2023-06-08 | 2023-09-05 | 厦门半导体工业技术研发有限公司 | Memory array |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116705086A (en) * | 2023-06-08 | 2023-09-05 | 厦门半导体工业技术研发有限公司 | Memory array |
| CN116705086B (en) * | 2023-06-08 | 2024-04-09 | 厦门半导体工业技术研发有限公司 | Memory array |
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Effective date of registration: 20230301 Address after: Room 1601-1607, 85 Xiangxue Avenue, Huangpu District, Guangzhou, Guangdong 510000 Patentee after: AoXin integrated circuit technology (Guangdong) Co.,Ltd. Address before: 621000 No. 39, North Section of Sanjiang Avenue, Economic and Technological Development Zone, Mianyang City, Sichuan Province Patentee before: SICHUAN DOUQI TECHNOLOGY CO.,LTD. |
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