CN204792780U - Integrated inductance of semiconductor - Google Patents
Integrated inductance of semiconductor Download PDFInfo
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- CN204792780U CN204792780U CN201520512656.1U CN201520512656U CN204792780U CN 204792780 U CN204792780 U CN 204792780U CN 201520512656 U CN201520512656 U CN 201520512656U CN 204792780 U CN204792780 U CN 204792780U
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Abstract
(B, ) the utility model discloses an integrated inductance of semiconductor, which comprises a substrate, a metal wiring and the 2nd metal wiring, the substrate includes first surface and second surface, a surface parallel is provided with two one at least metal wiring, the 2nd surface parallel is provided with one two at least metal wiring, a metal wiring and the 2nd metal wiring include head end and end, the head end of article one of a metal wiring is the first port of inductance, a metal wiring's last end is the second port of inductance, the substrate is provided with the wafer through -hole that runs through first surface and second surface, the intussuseption of wafer through -hole is filled with the conductive metal material, the end of (b) (b) n (b) (b) strip of a metal wiring passes through the head end that (b) (b) n (b) (b) strip of the 2nd metal wiring is connected to the wafer through -hole, the end of (b) (b) n (b) (b) strip of the 2nd metal wiring passes through the head end that (b) (b) n+1 (b) (b) strip of a metal wiring is connected to the wafer through -hole. Have height (b) (b) Q (b) (b) value, high inductance density characteristic to the performance is high, with low costs. (B, )
Description
Technical field
the utility model relates to semiconductor integrated inductor, is specifically related to a kind of three-dimensional spiral semiconductor integrated inductor based on wafer through hole and flip chip package technology.
Background technology
inductance can be the element that magnetic energy stores electric energy conversion.In integrated circuits, especially in simulation and radio frequency integrated circuit, inductance is one of passive device of often use, is generally used for as impedance matching element, resonant circuit components, filter building block, choke elements etc.Evaluating one of inductance performance most important index be Q value, and Q value is expressed as the ratio of an energy-storage travelling wave tube (as inductance, electric capacity etc.) energy stored by within the same signal period and institute's consumed energy.High Q value inductance means that inductance has lower energy loss, can promote the performance of integrated circuit, and therefore, high performance analog and radio frequency integrated circuit all require that the inductance that it uses has high q-factor.
at present, simulation and radio frequency integrated circuit great majority adopt the integrated inductor of planar spiral structures as shown in Figure 1, 2.As shown in Figure 1, planar spiral inductor 100 is made up of the first through hole 103 of metal routing 101 on metal routing on the first metal layer 102, second metal level and connection the first metal layer and the second metal level; The head end of metal routing 101 and the end of metal routing 102 form two ports of inductance 100 respectively; The end of through hole 103 connection metal cabling 101 and the head end of metal routing 102.Can see, the inductance 100 that metal routing 102, metal routing 101, through hole 103 are formed jointly is planar spiral structures.Be illustrated in figure 2 the side direction generalized section of inductance 100 along A-B tangential direction in Fig. 1, the substrate 108 that integrated circuit uses, according to the difference of the semiconductor technology selected, substrate 108 can be the materials such as Si, GaAs, InP, metal routing 102 is made in the upper surface of substrate 108, and covered encirclement by first medium layer 104, metal routing 101 is made in the upper surface of first medium layer 104, and being covered encirclement by second dielectric layer 105, the end of metal routing 101 and the head end of metal routing 102 are connected by the through hole 103 running through first medium layer 104.
this integrated inductor is as shown in Figure 1, 2 produced in the plane parallel with substrate plane, under radio frequency operation condition, can respond in substrate and form vortex current (EddyCurrent), the direction of vortex current is contrary with the sense of current in inductance coil, this must cause the magnetic flux of inductance coil to reduce, and extra energy loss is comparatively large thus make the Q value of whole inductance lower.According to existing conventional semiconductor technology level, in planar spiral inductor, the width of metal routing is generally 5um to 40um, spacing between metal routing is generally 5um to 20um, and planar spiral inductor monolateral length of area occupied on chip of a conventional inductance value (as 10nH inductance) is generally 100um to 400um; Visible plane spiral inductance occupies a large amount of chip areas, and its cost is higher.
at present, following two schemes is mainly contained with the loss the reducing substrate problem solving substrate mesoscale eddies electric current of starting with:
1, the screen be made up of additional metal levels is set below planar spiral inductor or adopts complicated hanging type planar spiral inductor to reduce vortex current in substrate to improve the Q value of inductance.But the restriction being subject to planar spiral inductor operation principle cannot tackle the problem at its root, inductive magnetic flux amount cannot be improved to reduce vortex current while increasing inductance value and to put forward high q-factor.
the chip area that the inductance value density that the mode of 2, being connected by multiple layer metal cabling improves planar spiral inductor takies to reduce planar spiral inductor, but the Q value of inductance usually can be made to reduce.
therefore, prior art means effectively cannot improve inductance Q value, reduce the cost of integrated inductor simultaneously.
Utility model content
for solving the problems of the technologies described above, the utility model object is: provide a kind of semiconductor integrated inductor, based on wafer through hole (TSV, and flip chip package technology (FC Through-SiliconVia), Flip-Chip) three-dimensional spiral inductor, can effectively reduce the vortex current in substrate and there is low DC losses thus there is very high inductance Q value, and comparing planar spiral inductor and significantly improve inductance density thus reduce manufacturing cost.
the technical solution of the utility model is:
a kind of semiconductor integrated inductor, comprise substrate, first metal routing and the second metal routing, described substrate comprises first surface and second surface, described first surface is arranged with at least two the first metal routings in parallel, described second surface is arranged with at least one the second metal routings in parallel, described first metal routing and the second metal routing comprise head end and end, the head end of the Article 1 of described first metal routing is the first port of inductance, the end of the last item of described first metal routing is the second port of inductance, described substrate is provided with the wafer through hole running through first surface and second surface, conductive metallic material is filled with in described wafer through hole, the end of n-th of described first metal routing connects the head end of n-th of the second metal routing by wafer through hole, the end of n-th of the second metal routing connects the head end of (n+1)th of the first metal routing by wafer through hole.
preferably, described substrate is High resistivity substrate, can be high resistant Si substrate, GaAs substrate, InP substrate, high resistant SOI substrate, glass substrate or ceramic substrate.
preferably, the width of described first metal routing and the second metal routing is 5um-50um, and thickness is 0.1um-20um, and the spacing of described first metal routing and the spacing of the second metal routing are 1um-20um.
preferably, the first port of described inductance and/or the second port are connected with the metal coupling for flip chip package.
preferably, the diameter of described wafer through hole is 20um-100um.
the invention also discloses a kind of resonant network comprising semiconductor integrated inductor of the present utility model, first port connection metal projection of described inductance, second port connects a pole plate of electric capacity, another pole plate connection metal projection of described electric capacity, described inductance and electric capacity are produced on the first chip, and this first chip passes through metal coupling flip chip package on the second chip.
preferably, described second chip attachment is on base plate for packaging, and described second chip is by the respective pins of bonding wire connection encapsulation substrate.
preferably, the electric capacity on described first chip is MIM capacitor, and described first chip adopts IPD technique.
preferably, described second chip is the radio frequency integrated circuit with active circuit.
preferably, described second chip is provided with multiple wafer through hole running through the second chip first surface and second surface, it to be drawn out to the second surface that outside signal port is connected to the second chip, and be connected on corresponding metal coupling by the metal routing on second surface, the again routing layer that distributes, mounted on base plate for packaging by the mode of flip chip package.
the utility model has the advantages that:
1. semiconductor integrated inductor of the present utility model is connected and composed by wafer through hole by the metal routing be distributed in High resistivity substrate upper and lower surface continuous print, non-crossing electrical metal paths constitute the spiral inductance of a stereochemical structure.There is a large portion inductance value to be contributed by multiple wafer through hole in three-dimensional spiral inductor, thus improve inductance value density, effectively can reduce the chip area shared by inductance.There is the advantage of high-performance and low cost.
2. three-dimensional spiral inductor can be produced on be integrated with the passive devices such as multiple electric capacity, resistance, inductance chip on, the first surface of substrate has made metal coupling, for by described chip flip chip package to base plate for packaging or other chip surface, install firmly, save space.
Accompanying drawing explanation
below in conjunction with drawings and Examples, the utility model is further described:
fig. 1 is the structural representation of the integrated inductor of existing planar spiral structures;
fig. 2 is the side direction generalized section of A-B tangential direction in Fig. 1;
fig. 3 is the structural representation of the utility model wafer through hole three-dimensional spiral inductor;
fig. 4 is the side direction generalized section of A-B tangential direction in Fig. 3;
fig. 5 is the resonant network resistance figure be made up of electric capacity and inductance;
fig. 6 is that the chip of resonant network realizes schematic diagram;
fig. 7 is the structural representation of chip attachment at base plate for packaging of resonant network;
fig. 8 is the vertical view of Fig. 7.
Embodiment
for making the purpose of this utility model, technical scheme and advantage clearly understand, below in conjunction with embodiment also with reference to accompanying drawing, the utility model is further described.Should be appreciated that, these describe just exemplary, and do not really want to limit scope of the present utility model.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring concept of the present utility model.
embodiment 1:
be illustrated in figure 3 the schematic diagram based on wafer through hole three-dimensional spiral inductor that the utility model proposes.As shown in Figure 3, three-dimensional spiral inductor 200 is produced among substrate 208.Preferably, in the utility model, substrate 208 has high resistant characteristic, and namely its resistivity is much larger than 50ohm-cm, is generally more than 1000ohm-cm; Substrate 208 can be the materials such as high resistant Si substrate, GaAs substrate, InP substrate, high resistant SOI substrate, glass, pottery.
substrate 208 has upper and lower two surfaces, and its upper surface has made a series of at least two strip metal cablings 201 parallel to each other, each strip metal cabling 201 has first, last two ends; Substrate lower surface has made a series of at least one metal routing 202 parallel to each other, each strip metal cabling 202 has first, last two ends.The head end of the Article 1 in metal routing 201 is as the first port of three-dimensional spiral inductor; The end of the last item in metal routing 201 is as the second port of three-dimensional spiral inductor.Made multiple wafer through hole 203 in substrate 208, wafer through hole 203 is the through-hole structures running through the upper and lower surface of substrate 208, and it is inner adopts good conductive metallic material such as plating process filling such as grade, such as the material such as aluminium, copper, tungsten.The end of n-th in metal routing 201 is connected to the head end of n-th in metal routing 202 by wafer through hole 203; The end of n-th in metal routing 202 is connected to the head end of in metal routing 201 (n+1)th by wafer through hole 203; Thus metal routing 201, wafer through hole 203, metal routing 202 are connected to become a continuous print, non-crossing electrical metal paths, constitute the spiral inductance of a stereochemical structure, namely based on the three-dimensional spiral inductor 200 of wafer through hole.
it should be noted that, the width of many strip metals cabling 201 spacing each other, many strip metals cabling 202 spacing each other and metal routing 201 and metal routing 202 and thickness, determine for the manufacture of the design rule of its semiconductor technology according to selection.The width of usual metal routing 201 and metal routing 202 is in 5um to 50um magnitude, and thickness is in 0.1um to 20um magnitude, and the spacing between metal routing is in 1um to 20um magnitude.
first port of three-dimensional spiral inductor and the second port are connected respectively to one for carrying out metal coupling 204, the metal coupling 205 of flip chip package.Usually, metal coupling 204 and metal coupling 205 adopt the mode of copper post (Cu-Pillar) or tin ball (SolderBall) to manufacture.
to be illustrated in figure 4 in Fig. 3 inductance 200 along the side direction generalized section of A-B tangential direction, the completely through upper and lower surface of substrate 208 of wafer through hole 203 can be seen, the respective end of metal routing 201 and metal routing 202 is linked together.The thickness of usual substrate 208, in 75um to 300um magnitude, therefore has a large portion inductance value to be contributed by multiple wafer through hole 203, thus improves inductance value density, effectively can reduce the chip area shared by inductance in three-dimensional spiral inductor 200.The diameter of usual wafer through hole 203 is 20um to 100um magnitude, its inner solid conducting metal for filling completely, and therefore wafer through hole 203 has very low DC losses; In addition the high resistant characteristic of substrate 208, thus make three-dimensional spiral inductor 200 have very high inductance Q value.
therefore, the three-dimensional spiral inductor based on wafer through hole that the utility model proposes, compared to planar spiral inductor of the prior art, has higher inductance Q value and higher inductance value density, has the advantage of high-performance and low cost.
embodiment 2:
be illustrated in figure 5 the Application Example of the utility model three-dimensional spiral inductor.Be illustrated in figure 5 a resonant network be made up of electric capacity 306 and inductance 307 required in a radio frequency integrated circuit, be generally used for rf filtering or impedance matching, two ports of resonant network are respectively 304 and 305.Be illustrated in figure 6 the chip of resonant network in Fig. 5 and realize schematic diagram, chip 300 has made three-dimensional spiral inductor 307 and electric capacity 306.Capacitor on chip adopts metal-insulator-metal type (MIM, Metal-Insulator-Metal) structure to manufacture.First port of three-dimensional spiral inductor 307 is connected to metal coupling 304, corresponding to the port 304 of resonant network in Fig. 5, second port of three-dimensional spiral inductor 307 is connected to a pole plate of MIM capacitor 306, the another one pole plate of MIM capacitor 306 is connected to metal coupling 305, corresponding to the port 305 of resonant network in Fig. 5.
as shown in Figure 7, the chip 300 of resonant network is manufactured with three-dimensional spiral inductor 307 and MIM capacitor 306, chip 300 flip chip package of resonant network is on an other chips 310, metal coupling 304,305 on chip 300 has been connected respectively on the corresponding pad of chip 310 upper surface, thus connects the resonant network on chip 300 in the circuit on chip 310.Chip 310 is provided with active radio frequency circuit, such as radio-frequency (RF) transceiver, radio-frequency power amplifier, radio-frequency (RF) switch etc., it adopts corresponding active semi-conductor manufacture technics, chip 300 adopts relatively more cheap IPD manufacture technics, it is integrated with high-performance, the three-dimensional spiral inductor of low cost and other passive devices.In the active circuit that chip 300 adopts the mode of flip chip package to be connected on chip 310, whole scheme has splendid performance and cost advantage.
as shown in Figure 7, chip 310 is also mounted on base plate for packaging 311, and the pad on chip 310 is connected in the respective pins of base plate for packaging 311 by bonding wire (BondingWire) 312.Base plate for packaging 311 can be LGA substrate in practical implementations, also can the form such as metal lead wire frame (Lead-Frame), and this is only for the utility model being described instead of for restriction of the present utility model.
be illustrated in figure 8 the vertical view of Fig. 7, can definitely see, it makes the chip 300 of the resonant network be made up of three-dimensional spiral inductor 307 and MIM capacitor 306, flip chip package is on the chip 310 having made active circuit, and the pad on chip 310 is connected in the respective pins of base plate for packaging 311 by bonding wire 312.
embodiment 3:
in another one embodiment of the present utility model, it makes first chip with the passive device such as three-dimensional spiral inductor and MIM capacitor, by metal coupling flip chip package on the first surface of the second chip having made active circuit, thus the passive device network that the first chip makes connection is entered in the active circuit that the second chip makes; Second chip makes multiple wafer through hole, it to be drawn out to the second surface that outside signal port is connected to the second chip, and to distribute routing layer (RDL by the metal routing on second surface, again, etc. Re-DistributedLayer) mode is connected on corresponding metal coupling, thus the chip-stacked entity that is made up of the first chip and the second chip can be mounted on the pcb board that base plate for packaging or user use by the mode of flip chip package.
should be understood that, above-mentioned embodiment of the present utility model only for exemplary illustration or explain principle of the present utility model, and is not formed restriction of the present utility model.Therefore, any amendment made when not departing from spirit and scope of the present utility model, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.In addition, the utility model claims be intended to contain fall into claims scope and border or this scope and border equivalents in whole change and modification.
Claims (10)
1.
a kind of semiconductor integrated inductor, comprise substrate, first metal routing and the second metal routing, it is characterized in that, described substrate comprises first surface and second surface, described first surface is arranged with at least two the first metal routings in parallel, described second surface is arranged with at least one the second metal routings in parallel, described first metal routing and the second metal routing comprise head end and end, the head end of the Article 1 of described first metal routing is the first port of inductance, the end of the last item of described first metal routing is the second port of inductance, described substrate is provided with the wafer through hole running through first surface and second surface, conductive metallic material is filled with in described wafer through hole, the end of n-th of described first metal routing connects the head end of n-th of the second metal routing by wafer through hole, the end of n-th of the second metal routing connects the head end of (n+1)th of the first metal routing by wafer through hole.
2.
semiconductor integrated inductor according to claim 1, is characterized in that, described substrate is High resistivity substrate, can be high resistant Si substrate, GaAs substrate, InP substrate, high resistant SOI substrate, glass substrate or ceramic substrate.
3.
semiconductor integrated inductor according to claim 1, it is characterized in that, the width of described first metal routing and the second metal routing is 5um-50um, and thickness is 0.1um-20um, and the spacing of described first metal routing and the spacing of the second metal routing are 1um-20um.
4.
semiconductor integrated inductor according to claim 1, is characterized in that, the first port of described inductance and/or the second port are connected with the metal coupling for flip chip package.
5.
semiconductor integrated inductor according to claim 1, is characterized in that, the diameter of described wafer through hole is 20um-100um.
6.
a kind of resonant network comprising the claims 1 or the semiconductor integrated inductor described in 2 or 5, it is characterized in that, first port connection metal projection of described inductance, second port connects a pole plate of electric capacity, another pole plate connection metal projection of described electric capacity, described inductance and electric capacity are produced on the first chip, and this first chip passes through metal coupling flip chip package on the second chip.
7.
resonant network according to claim 6, is characterized in that, described second chip attachment is on base plate for packaging, and described second chip is by the respective pins of bonding wire connection encapsulation substrate.
8.
resonant network according to claim 6, is characterized in that, the electric capacity on described first chip is MIM capacitor, and described first chip adopts IPD technique.
9.
resonant network according to claim 6, is characterized in that, described second chip is the radio frequency integrated circuit with active circuit.
10.
resonant network according to claim 7, it is characterized in that, described second chip is provided with multiple wafer through hole running through the second chip first surface and second surface, it to be drawn out to the second surface that outside signal port is connected to the second chip, and be connected on corresponding metal coupling by the metal routing on second surface, the again routing layer that distributes, mounted on base plate for packaging by the mode of flip chip package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520512656.1U CN204792780U (en) | 2015-07-15 | 2015-07-15 | Integrated inductance of semiconductor |
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| CN201520512656.1U CN204792780U (en) | 2015-07-15 | 2015-07-15 | Integrated inductance of semiconductor |
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| CN204792780U true CN204792780U (en) | 2015-11-18 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979333A (en) * | 2015-07-15 | 2015-10-14 | 宜确半导体（苏州）有限公司 | Semiconductor integrated inductor |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979333A (en) * | 2015-07-15 | 2015-10-14 | 宜确半导体（苏州）有限公司 | Semiconductor integrated inductor |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
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| PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
| PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of utility model: A Semiconductor Integrated Inductor Effective date of registration: 20230726 Granted publication date: 20151118 Pledgee: Bank of Communications Ltd. Suzhou branch Pledgor: ETRA SEMICONDUCTOR (SUZHOU) Co.,Ltd. Registration number: Y2023980049705 |