CN204731967U - Collecting sensor signal device - Google Patents
Collecting sensor signal device Download PDFInfo
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- CN204731967U CN204731967U CN201520482129.0U CN201520482129U CN204731967U CN 204731967 U CN204731967 U CN 204731967U CN 201520482129 U CN201520482129 U CN 201520482129U CN 204731967 U CN204731967 U CN 204731967U
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Abstract
The utility model discloses a kind of collecting sensor signal device, comprise processor, at least one data acquisition unit, charhing unit and communication unit, data acquisition unit comprises data acquisition port and analog to digital conversion circuit, charhing unit comprises charge management circuit, charging inlet and rechargeable battery, communication unit comprises radio communication circuit and antenna, processor respectively with analog to digital conversion circuit, charge management circuit is connected with radio communication circuit, analog to digital conversion circuit is connected with data acquisition port, charge management circuit is connected with charging inlet, radio communication circuit is connected with antenna.The utility model supports the connected mode of multiple and sensor, can compatible various types of sensor, adopts wireless communication transmissions data, avoids the noise of wire transmission.
Description
Technical field
The utility model relates to Signal Collection Technology field, particularly relates to a kind of collecting sensor signal device.
Background technology
Along with the development of society, signal picker is widely used in structural static test, testing fatigue and the load test stabilizations such as bridge, buildings, aircraft, boats and ships, vehicle, derrick.But, traditional signal picker support few with the connected mode of sensor, antijamming capability is weak, cannot be transmitted by wireless network.
Utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, provides a kind of collecting sensor signal device, adopts wireless communication transmissions data, avoids the noise of wire transmission.
The purpose of this utility model is achieved through the following technical solutions: collecting sensor signal device, comprise processor, at least one data acquisition unit, charhing unit and communication unit, data acquisition unit comprises data acquisition port and analog to digital conversion circuit, charhing unit comprises charge management circuit, charging inlet and rechargeable battery, communication unit comprises radio communication circuit and antenna, processor respectively with analog to digital conversion circuit, charge management circuit is connected with radio communication circuit, analog to digital conversion circuit is connected with data acquisition port, charge management circuit is connected with charging inlet, radio communication circuit is connected with antenna.
Described data acquisition port comprises the first data acquisition port, the second data acquisition port, the 3rd data acquisition port and the 4th data acquisition port, and analog-digital conversion circuit as described comprises the first analog to digital conversion circuit, the second analog to digital conversion circuit, the 3rd analog to digital conversion circuit and the 4th analog to digital conversion circuit.
Described first data acquisition port is connected with the analog input end of the first analog to digital conversion circuit, the digital input end of the processor of the digital output end of the first analog to digital conversion circuit connects, second data acquisition port is connected with the analog input end of the second analog to digital conversion circuit, the digital input end of the processor of the digital output end of the second analog to digital conversion circuit connects, 3rd data acquisition port is connected with the analog input end of the 3rd analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 3rd analog to digital conversion circuit connects, 4th data acquisition port is connected with the analog input end of the 4th analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 4th analog to digital conversion circuit connects.
Described first analog to digital conversion circuit is connected by the first switch with the second analog to digital conversion circuit, 3rd analog to digital conversion circuit is connected by second switch with four-way analog to digital conversion circuit, first analog to digital conversion circuit is connected with the first data acquisition port by the 3rd switch, second analog to digital conversion circuit is connected with the second data acquisition port by the 4th switch, 3rd analog to digital conversion circuit is connected with the 3rd data acquisition port by the 5th switch, and the 4th analog to digital conversion circuit is connected with the 4th data acquisition port by the 6th switch.
Described first switch and second switch include ADG884BRMZ chip, and the 3rd switch, the 4th switch, the 5th switch and the 6th switch include ADG812YRU chip.
Further, also comprise storer, storer is connected with processor.
Further, also comprise key-press module, be used to indicate the run indicator of power supply status and charged state and be used to indicate the connection pilot lamp of network communication status, key-press module, run indicator are all connected with processor with connection pilot lamp.
The beneficial effects of the utility model are:
(1) the utility model supports the connected mode of multiple and sensor, can compatible various types of sensor;
(2) be provided with wireless communication chips, support of wireless communication, avoid the noise of wire transmission;
(3) be provided with power management chip, can will reduce power consumption, extend the power-on time of battery.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the utility model collecting sensor signal device;
Fig. 2 is the connection diagram of the first analog to digital conversion circuit and the second analog to digital conversion circuit in the utility model;
Fig. 3 is the connection diagram of the 3rd analog to digital conversion circuit and the 4th analog to digital conversion circuit in the utility model.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection domain of the present utility model is not limited to the following stated.
As shown in Figure 1, collecting sensor signal device, comprise processor, at least one analog to digital conversion circuit, at least one data acquisition port, charge management circuit, radio communication circuit, antenna and rechargeable battery, processor is connected with one or more analog to digital conversion circuit respectively, at least one analog to digital conversion circuit and at least one data acquisition port connect one to one, processor is also connected with charging inlet by charge management circuit, and processor is also connected with antenna by radio communication circuit.
Further, also comprise storer, storer is connected with processor, and storer comprises K9K8G08U0A chip.
Further, also comprise key-press module, be used to indicate the run indicator of power supply status and charged state and be used to indicate the connection pilot lamp of network communication status, key-press module, run indicator are all connected with processor with connection pilot lamp.Power supply status comprises battery-powered state, externally fed state and off-mode, charged state comprises pre-charge state, charging quickly state, rechargeable battery full state and charging abnormality, and run indicator distinguishes each state of power supply and charging by the light that sends different colours and the flicker of carrying out different frequency; Network communication status comprises accepting state, transmission state, dormant state, malfunction and off-mode, connects pilot lamp and carrys out by the light sending different colours and the flicker carrying out different frequency each state that diffServ network communicates.
Described processor comprises STM32F103VBT6 chip, and the crystal oscillating circuit of processor comprises XO-5032 chip, and analog to digital conversion circuit comprises ADS1248IPW chip, and charging management chip comprises CN3063 chip.
Described radio communication circuit comprises radio frequency chip.
Described data acquisition port comprises the first data acquisition port, the second data acquisition port, the 3rd data acquisition port and the 4th data acquisition port, and analog-digital conversion circuit as described comprises the first analog to digital conversion circuit, the second analog to digital conversion circuit, the 3rd analog to digital conversion circuit and the 4th analog to digital conversion circuit.
Described first data acquisition port is connected with the analog input end of the first analog to digital conversion circuit, the digital input end of the processor of the digital output end of the first analog to digital conversion circuit connects, second data acquisition port is connected with the analog input end of the second analog to digital conversion circuit, the digital input end of the processor of the digital output end of the second analog to digital conversion circuit connects, 3rd data acquisition port is connected with the analog input end of the 3rd analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 3rd analog to digital conversion circuit connects, 4th data acquisition port is connected with the analog input end of the 4th analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 4th analog to digital conversion circuit connects.
Described first analog to digital conversion circuit is connected by the first switch with the second analog to digital conversion circuit, 3rd analog to digital conversion circuit is connected by second switch with four-way analog to digital conversion circuit, first analog to digital conversion circuit is connected with the first data acquisition port by the 3rd switch, second analog to digital conversion circuit is connected with the second data acquisition port by the 4th switch, 3rd analog to digital conversion circuit is connected with the 3rd data acquisition port by the 5th switch, and the 4th analog to digital conversion circuit is connected with the 4th data acquisition port by the 6th switch.
Described first switch and second switch include ADG884BRMZ chip, and the 3rd switch, the 4th switch, the 5th switch and the 6th switch include ADG812YRU chip.
Described data acquisition port is provided with and inputs anode, input negative terminal, in analog end, excitation electric pressure side and resnstance transformer end, and sensor is provided with output plus terminal, exports negative terminal, exports compensation end, output common port and bridge voltage end.End in analog and the excitation electric pressure side of each data acquisition port are separate, can not use with, otherwise can affect measurement result.
Collecting sensor signal device and the connected mode of sensor comprise that two-wire system 1/4th bridging connects, three-wire system 1/4th bridging connects, half-bridge is connected and full-bridge connects.Two-wire system 1/4th bridge is because inlead resistance, affect the size of measurements available range, advise using when line length is no more than 2 meters, three-wire system 1/4th bridge have employed line resistance compensation mode, and the measurement range of module is not affected by line resistance, and subsides method during half-bridge is many, needs according to measuring can select different subsides methods, subsides method during full-bridge is many, and the needs according to measuring can select different subsides methods, and sensor is that bridge road powers.
The bridging of described two-wire system 1/4th connects and comprises voltage drive two-wire system 1/4th bridging and connect and connect with current excitation two-wire system 1/4th bridging, three-wire system 1/4th bridging connects and comprises voltage drive three-wire system 1/4th bridging and connect and connect with current excitation three-wire system 1/4th bridging, half-bridge connection comprises the connection of voltage drive half-bridge and is connected with current excitation half-bridge, and full-bridge even comprises the connection of voltage drive full-bridge and is connected with current excitation full-bridge.Processor realizes the different connected modes of collecting sensor signal device and sensor by control first switch to the on off operating mode of the 6th switch.
The connected mode of collecting sensor signal device and sensor is when voltage drive two-wire system 1/4th bridging connects or current excitation two-wire system 1/4th bridging connects, the input anode of data acquisition port is connected with the output plus terminal of sensor, and the end in analog of data acquisition port is connected with the output negative terminal of sensor.
The connected mode of collecting sensor signal device and sensor is when voltage drive three-wire system 1/4th bridging connects or current excitation three-wire system 1/4th bridging connects, the input anode of data acquisition port is connected with the output plus terminal of sensor, the end in analog of data acquisition port is connected with the output negative terminal of sensor, and the resnstance transformer end of data acquisition port compensates to hold with the output of sensor and is connected.
Collecting sensor signal device and the connected mode of sensor are when voltage drive half-bridge is connected, current excitation half-bridge connects or current excitation full-bridge connects, the input anode of data acquisition port is connected with the output plus terminal of sensor, the input negative terminal of data acquisition port is connected with the output negative terminal of sensor, and the end in analog of data acquisition port is connected with the output common port of sensor.
Collecting sensor signal device and the connected mode of sensor are that voltage drive full-bridge is when being connected, the input anode of data acquisition port is connected with the output plus terminal of sensor, the input negative terminal of data acquisition port is connected with the output negative terminal of sensor, the end in analog of data acquisition port is connected with the output common port of sensor, and the excitation electric pressure side of data acquisition port is connected with the bridge voltage end of sensor.
When collecting sensor signal device and sensor adopt different connected mode, the each port of ADG884BRMZ chip, the state of the excitation electric pressure side of each port of ADG812YRU chip and data acquisition port is as shown in table 1, in table, ADG812.IN1 represents the IN1 port of ADG812YRU chip, ADG812.IN2 represents the IN2 port of ADG812YRU chip, ADG812.IN3 represents the IN3 port of ADG812YRU chip, ADG812.IN4 represents the IN4 port of ADG812YRU chip, ADG884.IN1 represents the IN1 port of ADG884BRMZ chip, VEXC represents the excitation electric pressure side of data acquisition port, Enable represents and enables, Disable represents forbidding:
The state of the excitation electric pressure side of each port of table 1 DG884BRMZ chip, each port of ADG812YRU chip and data acquisition port
As shown in table 1, when the connected mode of collecting sensor signal device and sensor be two-wire system 1/4th bridging connect time, the IN1 interface enabling of ADG812YRU chip, the IN2 interface enabling of ADG812YRU chip, the IN3 interface enabling of ADG812YRU chip, the IN4 interface disabling of ADG812YRU chip, the IN1 interface enabling of ADG884BRMZ chip, the excitation electric pressure side forbidding of data acquisition port; When the connected mode of collecting sensor signal device and sensor be three-wire system 1/4th bridging connect time, the IN1 interface enabling of ADG812YRU chip, the IN2 interface enabling of ADG812YRU chip, the IN3 interface disabling of ADG812YRU chip, the IN4 interface disabling of ADG812YRU chip, the IN1 interface enabling of ADG884BRMZ chip, the excitation electric pressure side forbidding of data acquisition port; When collecting sensor signal device and the connected mode of sensor be half-bridge be connected time, the IN1 interface enabling of ADG812YRU chip, the IN2 interface enabling of ADG812YRU chip, the IN3 interface disabling of ADG812YRU chip, the IN4 interface disabling of ADG812YRU chip, the IN1 interface enabling of ADG884BRMZ chip, the excitation electric pressure side forbidding of data acquisition port; When collecting sensor signal device and the connected mode of sensor be full-bridge be connected time, the IN1 interface disabling of ADG812YRU chip, the IN2 interface disabling of ADG812YRU chip, the IN3 interface disabling of ADG812YRU chip, the IN4 interface disabling of ADG812YRU chip, the IN1 interface enabling of ADG884BRMZ chip, the excitation electric pressure side of data acquisition port is enabled.
As shown in Figure 2, SIN1+ represents the input anode of the first data acquisition port, SIN1-represents the input negative terminal of the first data acquisition port, SIN1G represents the resnstance transformer end of the first data acquisition port, SIN1AGND represents the end in analog of the first data acquisition port, and SIN1VEXC represents the excitation electric pressure side of the first data acquisition port; SIN2+ represents the input anode of the second data acquisition port, SIN2-represents the input negative terminal of the second data acquisition port, SIN2G represents the resnstance transformer end of the second data acquisition port, SIN2AGND represents the end in analog of the second data acquisition port, and SIN2VEXC represents the excitation electric pressure side of the second data acquisition port, and U1 represents the first analog to digital conversion circuit, U2 represents the 3rd switch, U3 represents the second analog to digital conversion circuit, and U4 represents the 4th switch, and U5 represents the first switch.
The AIN0/IEXC end of the first analog to digital conversion circuit U1 is all connected with the input anode of the first data acquisition port with AIN4/IEXC/GPIO4 end, the AIN1/IEXC end of the first analog to digital conversion circuit U1 is all connected with the input negative terminal of the first data acquisition port with AIN5/IEXC/GPIO5, the AIN3/IEXC/GPIO3 end of the first analog to digital conversion circuit U1 holds with the IN1 of the 3rd switch U2 respectively and IN2 holds and is connected, the AIN2/IEXC/GPIO2 end of the first analog to digital conversion circuit U1 is held with the IN3 of the 3rd switch U2 respectively and is connected, the AIN7/IEXC/GPIO7 end of the first analog to digital conversion circuit U1 is held with the IN4 of the 3rd switch U2 respectively and is connected.The S1 end of the 3rd switch U2 and S2 hold all with the excitation electric press bond of the first data acquisition port, the D1 end of the 3rd switch U2 is all connected with the input anode of the first data acquisition port with S4 end, the D2 end of the 3rd switch U2 is connected with the input negative terminal of the first data acquisition port, the S3 end of the 3rd switch U2 is connected with the resnstance transformer end of the first data acquisition port, and the D3 end of the 3rd switch U2 is connected with the end in analog of the first data acquisition port.
The AIN0/IEXC end of the second analog to digital conversion circuit U3 is all connected with the input anode of the second data acquisition port with AIN4/IEXC/GPIO4 end, the AIN1/IEXC end of the second analog to digital conversion circuit U3 is all connected with the input negative terminal of the second data acquisition port with AIN5/IEXC/GPIO5, the AIN3/IEXC/GPIO3 end of the second analog to digital conversion circuit U3 holds with the IN1 of the 4th switch U4 respectively and IN2 holds and is connected, the AIN2/IEXC/GPIO2 end of the second analog to digital conversion circuit U3 is held with the IN3 of the 4th switch U4 respectively and is connected, the AIN7/IEXC/GPIO7 end of the second analog to digital conversion circuit U3 is held with the IN4 of the 4th switch U4 respectively and is connected.The S1 end of the 4th switch U4 and S2 hold all with the excitation electric press bond of the second data acquisition port, the D1 end of the 4th switch U4 is all connected with the input anode of the second data acquisition port with S4 end, the D2 end of the 4th switch U4 is connected with the input negative terminal of the second data acquisition port, the S3 end of the 4th switch U4 is connected with the resnstance transformer end of the second data acquisition port, and the D3 end of the 4th switch U4 is connected with the end in analog of the second data acquisition port.
The AIN6/IEXC/GPIO6 end of the first analog to digital conversion circuit U1 is held with the IN2 of the first switch U5 and is connected, and the AIN6/IEXC/GPIO6 end of the second analog to digital conversion circuit U3 is held with the IN1 of the first switch U5 and is connected.
As shown in Figure 3, SIN3+ represents the input anode of the 3rd data acquisition port, SIN3-represents the input negative terminal of the 3rd data acquisition port, SIN3G represents the resnstance transformer end of the 3rd data acquisition port, SIN3AGND represents the end in analog of the 3rd data acquisition port, and SIN3VEXC represents the excitation electric pressure side of the 3rd data acquisition port; SIN4+ represents the input anode of the 4th data acquisition port, SIN4-represents the input negative terminal of the 4th data acquisition port, SIN4G represents the resnstance transformer end of the 4th data acquisition port, SIN4AGND represents the end in analog of the 4th data acquisition port, and SIN4VEXC represents the excitation electric pressure side of the 4th data acquisition port, and U6 represents the 3rd analog to digital conversion circuit, U7 represents the 5th switch, U8 represents the 4th analog to digital conversion circuit, and U9 represents the 6th switch, and U10 represents second switch.
The AIN0/IEXC end of the 3rd analog to digital conversion circuit U6 is all connected with the input anode of the 3rd data acquisition port with AIN4/IEXC/GPIO4 end, the AIN1/IEXC end of the 3rd analog to digital conversion circuit U6 is all connected with the input negative terminal of the 3rd data acquisition port with AIN5/IEXC/GPIO5, the AIN3/IEXC/GPIO3 end of the 3rd analog to digital conversion circuit U6 holds with the IN1 of the 5th switch U7 respectively and IN2 holds and is connected, the AIN2/IEXC/GPIO2 end of the 3rd analog to digital conversion circuit U6 is held with the IN3 of the 5th switch U7 respectively and is connected, the AIN7/IEXC/GPIO7 end of the 3rd analog to digital conversion circuit U6 is held with the IN4 of the 5th switch U7 respectively and is connected.The S1 end of the 5th switch U7 and S2 hold all with the excitation electric press bond of the 3rd data acquisition port, the D1 end of the 5th switch U7 is all connected with the input anode of the 3rd data acquisition port with S4 end, the D2 end of the 5th switch U7 is connected with the input negative terminal of the 3rd data acquisition port, the S3 end of the 5th switch U7 is connected with the resnstance transformer end of the 3rd data acquisition port, and the D3 end of the 5th switch U7 is connected with the end in analog of the 3rd data acquisition port.
The AIN0/IEXC end of the 4th analog to digital conversion circuit U8 is all connected with the input anode of the 4th data acquisition port with AIN4/IEXC/GPIO4 end, the AIN1/IEXC end of the 4th analog to digital conversion circuit U8 is all connected with the input negative terminal of the 4th data acquisition port with AIN5/IEXC/GPIO5, the AIN3/IEXC/GPIO3 end of the 4th analog to digital conversion circuit U8 holds with the IN1 of the 6th switch U9 respectively and IN2 holds and is connected, the AIN2/IEXC/GPIO2 end of the 4th analog to digital conversion circuit U8 is held with the IN3 of the 6th switch U9 respectively and is connected, the AIN7/IEXC/GPIO7 end of the 4th analog to digital conversion circuit U8 is held with the IN4 of the 6th switch U9 respectively and is connected.The S1 end of the 6th switch U9 and S2 hold all with the excitation electric press bond of the 4th data acquisition port, the D1 end of the 6th switch U9 is all connected with the input anode of the 4th data acquisition port with S4 end, the D2 end of the 6th switch U9 is connected with the input negative terminal of the 4th data acquisition port, the S3 end of the 6th switch U9 is connected with the resnstance transformer end of the 4th data acquisition port, and the D3 end of the 6th switch U9 is connected with the end in analog of the 4th data acquisition port.
The AIN6/IEXC/GPIO6 end of the 3rd analog to digital conversion circuit U6 is held with the IN2 of second switch U10 and is connected, and the AIN6/IEXC/GPIO6 end of the 4th analog to digital conversion circuit U8 is held with the IN1 of second switch U10 and is connected.
Claims (6)
1. collecting sensor signal device, it is characterized in that: comprise processor, at least one data acquisition unit, charhing unit and communication unit, data acquisition unit comprises data acquisition port and analog to digital conversion circuit, charhing unit comprises charge management circuit, charging inlet and rechargeable battery, communication unit comprises radio communication circuit and antenna, processor respectively with analog to digital conversion circuit, charge management circuit is connected with radio communication circuit, analog to digital conversion circuit is connected with data acquisition port, charge management circuit is connected with charging inlet, radio communication circuit is connected with antenna.
2. collecting sensor signal device according to claim 1, it is characterized in that: described data acquisition port comprises the first data acquisition port, the second data acquisition port, the 3rd data acquisition port and the 4th data acquisition port, analog-digital conversion circuit as described comprises the first analog to digital conversion circuit, the second analog to digital conversion circuit, the 3rd analog to digital conversion circuit and the 4th analog to digital conversion circuit;
Described first data acquisition port is connected with the analog input end of the first analog to digital conversion circuit, the digital input end of the processor of the digital output end of the first analog to digital conversion circuit connects, second data acquisition port is connected with the analog input end of the second analog to digital conversion circuit, the digital input end of the processor of the digital output end of the second analog to digital conversion circuit connects, 3rd data acquisition port is connected with the analog input end of the 3rd analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 3rd analog to digital conversion circuit connects, 4th data acquisition port is connected with the analog input end of the 4th analog to digital conversion circuit, the digital input end of the processor of the digital output end of the 4th analog to digital conversion circuit connects.
3. collecting sensor signal device according to claim 2, it is characterized in that: described first analog to digital conversion circuit is connected by the first switch with the second analog to digital conversion circuit, 3rd analog to digital conversion circuit is connected by second switch with four-way analog to digital conversion circuit, first analog to digital conversion circuit is connected with the first data acquisition port by the 3rd switch, second analog to digital conversion circuit is connected with the second data acquisition port by the 4th switch, 3rd analog to digital conversion circuit is connected with the 3rd data acquisition port by the 5th switch, 4th analog to digital conversion circuit is connected with the 4th data acquisition port by the 6th switch.
4. collecting sensor signal device according to claim 3, is characterized in that: described first switch and second switch include ADG884BRMZ chip, and the 3rd switch, the 4th switch, the 5th switch and the 6th switch include ADG812YRU chip.
5. collecting sensor signal device according to claim 1, it is characterized in that: also comprise storer, storer is connected with processor.
6. collecting sensor signal device according to claim 1, it is characterized in that: also comprise key-press module, be used to indicate the run indicator of power supply status and charged state and be used to indicate the connection pilot lamp of network communication status, key-press module, run indicator are all connected with processor with connection pilot lamp.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520482129.0U CN204731967U (en) | 2015-07-06 | 2015-07-06 | Collecting sensor signal device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520482129.0U CN204731967U (en) | 2015-07-06 | 2015-07-06 | Collecting sensor signal device |
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| CN204731967U true CN204731967U (en) | 2015-10-28 |
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| CN201520482129.0U Expired - Fee Related CN204731967U (en) | 2015-07-06 | 2015-07-06 | Collecting sensor signal device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023412A (en) * | 2015-07-06 | 2015-11-04 | 成都科力德科技有限责任公司 | Sensor signal collection device |
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2015
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105023412A (en) * | 2015-07-06 | 2015-11-04 | 成都科力德科技有限责任公司 | Sensor signal collection device |
| CN105023412B (en) * | 2015-07-06 | 2018-06-15 | 成都科力德科技有限责任公司 | Collecting sensor signal device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20151028 Termination date: 20160706 |