CN204649959U - A kind of many frequency sweeps high-frequency radar receiver device - Google Patents
A kind of many frequency sweeps high-frequency radar receiver device Download PDFInfo
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- CN204649959U CN204649959U CN201520337733.4U CN201520337733U CN204649959U CN 204649959 U CN204649959 U CN 204649959U CN 201520337733 U CN201520337733 U CN 201520337733U CN 204649959 U CN204649959 U CN 204649959U
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Abstract
The utility model discloses a kind of many frequency sweeps high-frequency radar receiver device, comprise: for providing the Clock management module of system clock source for described receiver apparatus, for providing the power management module of power supply for each module in described receiver apparatus, for generation of, launch the upstream circuitry module of many frequency sweeps digital signal and the downstream circuitry module for receiving, processing echo digital signal; Described upstream circuitry module, comprise the digital signal synthesis device, analog-digital chip, emission switch circuit and the first filter amplification circuit that connect successively, the circuit module for echo digital signal processing in the described digital signal synthesis device in described upstream circuitry module and described downstream circuitry module is all integrated in same FPGA process chip.By adopting FPGA process chip and analog-digital chip, system architecture is simple, and volume is little, and can meet the generation of any radar signal in higher-frequency radar, comprises Multicarrier Radar Signal simultaneously, overcomes the shortcoming of existing radar.
Description
Technical field
The utility model relates to the high band radar system technical field for ocean remote sensing, particularly one many frequency sweeps high-frequency radar receiver device.
Background technology
High frequency marine radar is a kind of over-the-horizon radar, is mainly used in detection ocean surface wind, wave, flow field and low-altitude low-speed moving target.The use of linear FM signal and corresponding pulse compression technique makes radar transmission power greatly reduce, interrupt linear frequency modulation continuous wave (frequency modulated interruptedcontinuous wave, FMICW) can the powerful direct wave problem of resolution system, the normal use of bonding base system.But as a kind of long-range detection system, in deepwater application, radar transmission power is still excessive.Because radar signal frequency is in high band, high band is extremely crowded frequency range, and the frequency electromagnetic waves of vertical polarization can along ocean surface diffraction, also can be far away through ionospheric propagation.Therefore radar self is easily subject to outside outside electromagnetic interference, and powerful emissive power also can impact the electronic equipment of periphery.Pulse compression technique a kind of the signal being distributed in different frequency and time is carried out phase compensation, realizes the technology that time domain accumulates.Pulse compression technique can allow radar system launch width relative to wider and peak power is lower pulse, to obtain burst pulse, the range resolution of high-peak power radar system and detection performance.
Existing high frequency ocean radar system all adopts DDS chip to generate swept-frequency signal, cannot meet the requirement simultaneously generating multiple frequency sweep.And no matter signal generation still compresses process to current high band radar installations, does not all have up-conversion and down coversion structure.
Utility model content
The purpose of this utility model is to propose a kind of many frequency sweeps high-frequency radar receiver device, have that circuit structure is simple, volume is little, and the generation of any radar signal in higher-frequency radar can be met, comprise Multicarrier Radar Signal simultaneously, overcome the shortcoming of existing radar.
For reaching this object, the utility model by the following technical solutions:
A kind of many frequency sweeps high-frequency radar receiver device, comprise: for providing the Clock management module of system clock source for described receiver apparatus, for providing the power management module of low jitter high-isolation power supply for each module in described receiver apparatus, for generation of, launch the upstream circuitry module of many frequency sweeps digital signal and the downstream circuitry module for receiving, processing echo digital signal;
Wherein, described upstream circuitry module, comprise the digital signal synthesis device, analog-digital chip, emission switch circuit and the first filter amplification circuit that connect successively, be all integrated in same FPGA process chip for the circuit module for echo digital signal processing in the described digital signal synthesis device of many frequency sweeps digital signal generation and described downstream circuitry module in described upstream circuitry module; Described Clock management module respectively with upstream circuitry module, downstream circuitry model calling, described power management module respectively with Clock management module, upstream circuitry module, downstream circuitry model calling.
Wherein, described downstream circuitry module, comprises the receiving key circuit, the second filter amplification circuit, modulus conversion chip and the digital signal processor that connect successively.
Wherein, also comprise the sequential control circuit module for providing system sequence to control to described receiver apparatus, described sequential control circuit module, digital signal synthesis device and digital signal processor are all integrated in same FPGA process chip.
Wherein, described downstream circuitry module, also comprises receiving antenna; Wherein, described receiving antenna is connected with receiving key circuit.
Wherein, described upstream circuitry module, also comprises emitting antenna; Wherein, described emitting antenna is connected with described first filter amplification circuit.
Wherein, described Clock management module is the relevant clock source of the overall situation, and comprise the clock synchronizer of crystal oscillator and single loop multi output, described crystal oscillator is connected with clock synchronizer.
Wherein, the low-jitter clock synchronizer of described clock synchronizer to be model be CDCE72010.
Wherein, described power management module, comprise the non-isolated digital power transmission module of two-way that digital PWM system controller that model is UCD9248PFC and model are PTD08D210W, described digital PWM system controller is connected with digital power transmission module.
Wherein, described emission switch circuit and receiving key circuit, all employing two-stage model is the switch chip realization of SA630D.
Wherein, described FPGA process chip, adopts the kintex-7 series of Xilinx company.
Beneficial effect:
One many frequency sweeps high-frequency radar receiver device described in the utility model, comprise: for providing the Clock management module of system clock source for described receiver apparatus, for providing the power management module of low jitter high-isolation power supply for each module in described receiver apparatus, for generation of, launch the upstream circuitry module of many frequency sweeps digital signal and the downstream circuitry module for receiving, processing echo digital signal; Wherein, described upstream circuitry module, comprise the digital signal synthesis device, analog-digital chip, emission switch circuit and the first filter amplification circuit that connect successively, be all integrated in same FPGA process chip for the circuit module for echo digital signal processing in the described digital signal synthesis device of many frequency sweeps digital signal generation and described downstream circuitry module in described upstream circuitry module; Described Clock management module respectively with upstream circuitry module, downstream circuitry model calling, described power management module respectively with Clock management module, upstream circuitry module, downstream circuitry model calling.Technical scheme described in the utility model is by adopting digital to analog converter and the digital signal synthesis device be integrated in FPGA process chip, Direct Digital Synthesis.Digital signal produces in FPGA process chip inside, and then use digital to analog converter, this is the structure that high band radar installations does not have; In addition, no matter signal produces still is compressed process, and current high band radar installations does not all have up-conversion and down coversion structure.This programme not only system architecture realizes simple, and volume is little, and can meet the generation of any radar signal in higher-frequency radar, comprises Multicarrier Radar Signal simultaneously, overcomes the shortcoming of existing radar.
Accompanying drawing explanation
Fig. 1 is the structural representation of a kind of many frequency sweeps high-frequency radar receiver device that the utility model specific embodiment provides.
Fig. 2 is many swept-frequency signals time-frequency figure of a kind of many frequency sweeps high-frequency radar receiver device that the utility model specific embodiment provides.
Fig. 3 is many swept-frequency signals process of pulse-compression process flow diagram of a kind of many frequency sweeps high-frequency radar receiver device that the utility model specific embodiment provides.
In figure:
1-Clock management module; 2-power management module; 3-upstream circuitry module; 4-downstream circuitry module; 5-sequential control circuit module; 310-digital signal synthesis device; 320-analog-digital chip; 330-emission switch circuit; 340-first filter amplification circuit; 350-emitting antenna; 410-receiving key circuit; 420-second filter amplification circuit; 430-modulus conversion chip; 440-digital signal processor; 450-receiving antenna.
Embodiment
The technical solution of the utility model is further illustrated by embodiment below in conjunction with accompanying drawing.
Fig. 1 is the structural representation of a kind of many frequency sweeps high-frequency radar receiver device that the utility model specific embodiment provides.As shown in Figure 1, one many frequency sweeps high-frequency radar receiver device described in the utility model, comprise: for providing the Clock management module 1 of system clock source for described receiver apparatus, for providing the power management module 2 of low jitter high-isolation power supply for each module in described receiver apparatus, for generation of, launch the upstream circuitry module 3 of many frequency sweeps digital signal and the downstream circuitry module 4 for receiving, processing echo digital signal;
Wherein, described upstream circuitry module 3, comprise the digital signal synthesis device 310, analog-digital chip 320, emission switch circuit 330 and the first filter amplification circuit 340 that connect successively, be all integrated in same FPGA process chip for the circuit module for echo digital signal processing in the described digital signal synthesis device 310 of many frequency sweeps digital signal generation and described downstream circuitry module 4 in described upstream circuitry module 3; Described Clock management module 1 is connected with upstream circuitry module 3, downstream circuitry module 4 respectively, and described power management module 2 is connected with Clock management module 1, upstream circuitry module 3, downstream circuitry module 4 respectively.
Technical scheme described in the utility model is by adopting digital to analog converter and the digital signal synthesis device 310 be integrated in FPGA process chip, Direct Digital Synthesis.Digital signal produces in FPGA process chip inside, and then use digital to analog converter, this is the structure that high band radar installations does not have; In addition, no matter signal produces still is compressed process, and current high band radar installations does not all have up-conversion and down coversion structure.This programme not only system architecture realizes simple, and volume is little, and can meet the generation of any radar signal in higher-frequency radar, comprises Multicarrier Radar Signal simultaneously, overcomes the shortcoming of existing radar.
Visible, in existing high-frequency radar receiver, DDS chip is utilized cannot directly to produce many swept-frequency signals, and this programme adopts the mode of digital-to-analog conversion, multiple swept-frequency signal can be produced by FPGA process chip simultaneously, and carry out numeral and add up, then by the digital data transmission after cumulative to digital to analog converter chip, finally carry out amplification filtering output.Therefore, by adopting the receiver apparatus structure described in this programme, can the parameter of flexible configuration different frequency signals, realize multiple frequency signal and produce simultaneously.Described upstream circuitry module 3, also comprises emitting antenna 350; Wherein, described emitting antenna 350 is connected with described first filter amplification circuit 340.By emitting antenna 350, the many swept-frequency signals after amplification filtering are launched.
In this programme, described downstream circuitry module 4, comprises receiving key circuit 410, second filter amplification circuit 420, modulus conversion chip 430 and the digital signal processor 440 that connect successively.Described downstream circuitry module 4, also comprises receiving antenna 450; Wherein, described receiving antenna 450 is connected with receiving key circuit 410.In echoed signal after receiving antenna 450 enters into receiver, AFE (analog front end) part carries out amplification filtering to signal, then signal enters modulus conversion chip 430 and directly carries out radio frequency sampling, sampled echo signals is divided into multichannel by the digital signal processor 440 in FPGA process chip, mixing is carried out respectively with the single swept-frequency signal of launching, low-pass filtering, time-frequency conversion, realizes the pulse compression of signal.The data after pulse compression are sent to host computer, so that carry out follow-up process finally by USB.
Described receiver apparatus, also comprise the sequential control circuit module 5 for providing system sequence to control to described receiver apparatus, described sequential control circuit module 5, digital signal synthesis device 310 and digital signal processor 440 are all integrated in same FPGA process chip.Launch the generation of digital signal, the sequential control of echo digital signal processing and system all completes in same FPGA process chip, simplifies system.
The course of work of a kind of many frequency sweeps high-frequency radar receiver device described in this programme as follows:
Fig. 2 is many swept-frequency signals time-frequency figure of a kind of many frequency sweeps high-frequency radar receiver device that the utility model specific embodiment provides.As shown in Figure 2, digital signal synthesis device 310 circulates to produce and has multiple swept-frequency signals of a fixed response time, and it is cumulative to realize numeral, then constantly by digital data transmission to the analog-digital chip 320 be attached thereto, realize digital-to-analog conversion.The corresponding harmonic component of filtering circuit filtering and out-of-band noise, feeble signal is amplified to specific size by amplifying circuit, finally gives transmitter and emitting antenna 350.In echoed signal after receiving antenna 450 enters into receiver apparatus, AFE (analog front end) part carries out amplification filtering to signal, then signal enters modulus conversion chip 430 and directly carries out radio frequency sampling, sampled echo signals is divided into multichannel by digital signal processor 440, mixing is carried out respectively with the single swept-frequency signal of launching, low-pass filtering, time-frequency conversion, realizes the pulse compression of signal.The data after pulse compression are sent to host computer, so that carry out follow-up process finally by USB.Finally, the generation of many swept-frequency signals, transmitting and echo signal processing is realized by this receiver apparatus.
In this programme, described Clock management module 1 is the relevant clock source of the overall situation, for whole receiver system provides system clock, for other circuit provide unified relevant clock signal, comprise the clock synchronizer of crystal oscillator and single loop multi output, described crystal oscillator is connected with clock synchronizer.Upstream circuitry module 3 in this programme and downstream circuitry module 4 adopt the relevant clock source of the overall situation, and all modules, device adopt same Clock management.In addition for modulus conversion chip 430 and analog-digital chip 320 provide the differential clocks of 40MHz, uplink and downlink circuit all adopts same clock source, ensures the good coherence of system.Preferably, the low-jitter clock synchronizer of described clock synchronizer to be model be CDCE72010.
In this programme, described power management module 2, comprise the non-isolated digital power transmission module of two-way that digital PWM system controller that model is UCD9248PFC and model are PTD08D210W, described digital PWM system controller is connected with digital power transmission module.Mainly be divided into two large classes, a class provides low jitter Switching Power Supply for FPGA process chip, and an other class provides linear power supply for other circuit, ensures the performance of receiver apparatus.
In this programme, described emission switch circuit 330 and receiving key circuit 410, all employing two-stage model is the switch chip realization of SA630D.Amplifying circuit gain in described first filter amplification circuit 340 and the second filter amplification circuit 420 is 40dB, and data acquisition uses 16 modulus conversion chips 430, described FPGA process chip, adopts the kintex-7 series of Xilinx company.
In sum, many frequency sweeps high-frequency radar receiver device described in the utility model, whole system adopts a slice FPGA process chip as control module, realize signal to produce and signal transacting, reduce extra hardware spending, and transmit and can realize with Received signal strength easily synchronous, there is system architecture composition simple.The utility model configuration parameter is flexible, owing to adopting the mode of digital-to-analog conversion, FPGA process chip can be used to produce arbitrary digital signal, then send analog-digital chip 320 to.Arbitrarily can not only produce phase-modulated signal, FM signal, interrupts FM signal, and can realize the many swept-frequency signals in certain peak-to-average power ratio, radar signal is produced and performance comparison more convenient, realization arbitrarily signal generating device truly and data processor.This device can realize a kind of generation and compression of many frequency-scan radars signal, thus reaches reduction radar emission peak power but the effect of guarantee detection performance.
Below that the process adopting the apparatus structure described in this programme to produce many swept-frequency signals is described in detail:
The many swept-frequency signals time frequency distribution map adopted in the present embodiment as shown in Figure 2, in a frequency sweep cycle, there are 4 swept-frequency signal timesharing produce and launch, go round and begin again, and covers the whole time period by 4 swept-frequency signals.The numerical portion transmitted is completed by the digital signal synthesis device 310 in FPGA process chip, because needs timesharing produces multiple swept-frequency signal, and the time has overlapped, therefore individually produce swept-frequency signal by 4 tunnels, then carrying out adding up obtains final numeral output.Single frequency sweep numerical expression is as follows:
Wherein, frequency sweep slope is k (when carrying out lower frequency sweep, k is negative value), and the frequency sweep time is T, N is single frequency sweep cycle sampling number N=T/T
s.For the time signal of 4 frequency sweeps, the time interval between adjacent two frequency sweeps is T/4, then for the time-multiplexed signal digital expression formula of 4 frequency sweep be
s[n]＝s
1[mod(n,N)]+s
1[mod(n-N/4,N)]+
s
1[mod(n-N/2,N)]+s
1[mod(n-3N/4,N)]
n＝0,1,..∞ (2)
Wherein mod is complementation operating function.
According to Fig. 1, for upstream circuitry, digital signal synthesis device 310 chip in FPGA process chip calculates the numerical portion of many swept-frequency signals according to above formula, single swept-frequency signal uses CORDIC operation core to produce, then use 4 tunnel operation core to calculate simultaneously, the frequency sweep start trigger signal on every road is controlled by FPGA process chip, trigger pip time phase difference T/4.Every road swept-frequency signal is carried out numeral to add up, then send analog-digital chip 320 to by digital signal synthesis device 310, adopt 14 figure place weighted-voltage D/A converters here, larger dynamic range can be realized and meet quantizing noise requirements.Analog-digital chip 320 outputting analog signal, by emission switch circuit 330, switch is controlled by FPGA process chip, interrupting controlling, realizing good transceiver insulation for transmitting.Carry out filter and amplification to by the signal after emission switch circuit 330, adopt the corresponding harmonic component of bandpass filter filtering and out-of-band noise, in the present embodiment, passband width is 2MHz, and attenuation outside a channel is 40dB, and in passband, fluctuation range is 3dB.The Low phase noise amplifier gain be connected with wave filter is 23dB, guarantees analogue signal amplitude to be adjusted to 0dBm.This signal is extended to high-power signal by last transmitter, is then radiate by emitting antenna 350.
Below that the process of the apparatus structure process many frequency sweeps echoed signal adopted described in this programme is described in detail:
For the downstream circuitry of the receiver apparatus described in this programme, be made up of receiving key circuit 410, second filter amplification circuit 420, modulus conversion chip 430 and the digital signal processor 440 connected successively.Receiving key circuit 410 is just in time contrary with emission switch circuit 330, does not launch during reception, does not receive during transmitting, for increasing transceiver insulation, ensures that system is unsaturated by the interference of direct wave.Owing to being radio frequency Direct Sampling, so need front end band pass filters for anti-aliasing, amplifying circuit is used for being amplified in the sample range of modulus conversion chip 430 by feeble signal, to improve Dynamic Range and sensitivity.Then, the signal after amplification enters digital signal processor 440 through modulus conversion chip 430.Many swept-frequency signals pulse compression principle in the utility model as shown in Figure 3.The signal of echoed signal after modulus sampling enters digital signal processor 440, and digital echo signal is the delay transmitted, because include multiple frequency sweep information equally.Suppose that the digital echo signal expression formula of single target is
s
r[n]＝s[n-n
0],n＝0,1,...,∞ (3)
Wherein n
0for the sampling number that echo delay time is corresponding.Echoed signal is sent into multiply digital signals processor 440, identical with single swept-frequency signal pulse compression principle, carry out mixing+discrete Fourier transformation (Discrete Fourier Transform, DFT) computing respectively, realize the pulse compression of corresponding swept-frequency signal.Specific implementation is:
y
1[n]＝DFT{s
1[mod(n,N)]×s
r[n]}
y
2[n]＝DFT{s
1[mod(n-N/4,N)]×s
r[n]}
y
3[n]＝DFT{s
1[mod(n-N/2),N]×s
r[n]}
y
4[n]＝DFT{s
1[mod(n-3N/4),N]×s
r[n]}
n＝0,1,...∞ (4)
From formula (4), echoed signal is many swept-frequency signals, adopts single swept-frequency signal as local oscillator respectively, carry out pulse compression, due to the otherness in frequency, they obtain the pulse compression result of its own transmission signal respectively, finally multiple signals are carried out parallel-serial conversion, obtain { y
1, y
2, y
3, y
4.Here can using they as cycle T/4 that shake multiframe pulse pressure after result, by USB, they are transferred to host computer, finally carry out coherent accumulation and obtain corresponding velocity information.
The above; be only the utility model preferably embodiment; but protection domain of the present utility model is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; be equal to according to the technical solution of the utility model and utility model design thereof and replace or change, all should be encompassed within protection domain of the present utility model.
Claims (10)
1. the device of frequency sweep high-frequency radar receiver more than a kind, it is characterized in that, comprise: for providing the Clock management module of system clock source for described receiver apparatus, for providing the power management module of low jitter high-isolation power supply for each module in described receiver apparatus, for generation of, launch the upstream circuitry module of many frequency sweeps digital signal and the downstream circuitry module for receiving, processing echo digital signal;
Wherein, described upstream circuitry module, comprise the digital signal synthesis device, analog-digital chip, emission switch circuit and the first filter amplification circuit that connect successively, be all integrated in same FPGA process chip for the circuit module for echo digital signal processing in the described digital signal synthesis device of many frequency sweeps digital signal generation and described downstream circuitry module in described upstream circuitry module; Described Clock management module respectively with upstream circuitry module, downstream circuitry model calling, described power management module respectively with Clock management module, upstream circuitry module, downstream circuitry model calling.
2. one many frequency sweeps high-frequency radar receiver device according to claim 1, is characterized in that, described downstream circuitry module, comprises the receiving key circuit, the second filter amplification circuit, modulus conversion chip and the digital signal processor that connect successively.
3. one many frequency sweeps high-frequency radar receiver device according to claim 2, it is characterized in that, also comprise the sequential control circuit module for providing system sequence to control to described receiver apparatus, described sequential control circuit module, digital signal synthesis device and digital signal processor are all integrated in same FPGA process chip.
4. one many frequency sweeps high-frequency radar receiver device according to claim 2, it is characterized in that, described downstream circuitry module, also comprises receiving antenna; Wherein, described receiving antenna is connected with receiving key circuit.
5. one many frequency sweeps high-frequency radar receiver device according to claim 1, it is characterized in that, described upstream circuitry module, also comprises emitting antenna; Wherein, described emitting antenna is connected with described first filter amplification circuit.
6. one many frequency sweeps high-frequency radar receiver device according to claim 1, it is characterized in that, described Clock management module is the relevant clock source of the overall situation, and comprise the clock synchronizer of crystal oscillator and single loop multi output, described crystal oscillator is connected with clock synchronizer.
7. one many frequency sweeps high-frequency radar receiver device according to claim 6, is characterized in that, the low-jitter clock synchronizer of described clock synchronizer to be model be CDCE72010.
8. one many frequency sweeps high-frequency radar receiver device according to claim 1, it is characterized in that, described power management module, comprise the non-isolated digital power transmission module of two-way that digital PWM system controller that model is UCD9248PFC and model are PTD08D210W, described digital PWM system controller is connected with digital power transmission module.
9. one many frequency sweeps high-frequency radar receiver device according to claim 2, is characterized in that, described emission switch circuit and receiving key circuit, and all employing two-stage model is the switch chip realization of SA630D.
10. one many frequency sweeps high-frequency radar receiver device according to claim 1, is characterized in that, described FPGA process chip, adopts the kintex-7 series of Xilinx company.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597447A (en) * | 2016-12-23 | 2017-04-26 | 成都西科微波通讯有限公司 | Airport surface detection radar |
| CN109814104A (en) * | 2019-01-31 | 2019-05-28 | 厦门精益远达智能科技有限公司 | A kind of obstacle detection method based on radar, device, equipment and storage medium |
-
2015
- 2015-05-22 CN CN201520337733.4U patent/CN204649959U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106597447A (en) * | 2016-12-23 | 2017-04-26 | 成都西科微波通讯有限公司 | Airport surface detection radar |
| CN109814104A (en) * | 2019-01-31 | 2019-05-28 | 厦门精益远达智能科技有限公司 | A kind of obstacle detection method based on radar, device, equipment and storage medium |
| CN109814104B (en) * | 2019-01-31 | 2021-01-22 | 厦门精益远达智能科技有限公司 | Obstacle detection method, device and equipment based on radar and storage medium |
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