CN204631211U - A kind of general FPGA test macro - Google Patents
A kind of general FPGA test macro Download PDFInfo
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- CN204631211U CN204631211U CN201520362859.7U CN201520362859U CN204631211U CN 204631211 U CN204631211 U CN 204631211U CN 201520362859 U CN201520362859 U CN 201520362859U CN 204631211 U CN204631211 U CN 204631211U
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Abstract
The utility model relates to a kind of general FPGA test macro, belongs to electronic technology field.This system comprises test board and host computer.Wherein test board comprises test chip, general processor and plug connector.Test chip is in order to run FPGA test procedure, statistics program generate test data; General processor in order to run application, and control described in test chip and described host computer between data interaction; Test procedure and application program then in order to show described test data, and are loaded into described test chip and described general processor according to operation by host computer respectively.By this system, tester can utilize host computer easily, and for different FPGA to be measured, specific test procedure, statistics program and application program are loaded into test board, and then the actual working state of FPGA to be measured can be reflected more accurately, promote test data accuracy, ensure testing efficiency.
Description
Technical field
The utility model relates to electronic technology field, particularly FPGA applied technical field, specifically refers to a kind of general FPGA test macro.
Background technology
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, be electronic equipment conventional at present, it has able to programme, applies easy, feature applied widely.
In the practical application of FPGA, need a kind of evaluating system carrying out testing and analysis for FPGA code function and efficiency, the team being applicable to carry out based on FGPA system development carries out testing and checking to the FPGA code that it designs comprehensively and really.
And in existing FPGA test macro, often there is bigger difference with the application scenarios of reality in the constraint condition of tested code and placement-and-routing, test result truly cannot reflect the duty of actual FPGA program, thus increases the workload of FPGA testing authentication further.
Therefore, how to provide one can more accurately reflect FPGA actual working state, thus improve test data accuracy, ensure that the general FPGA test macro of testing efficiency becomes this area problem demanding prompt solution.
Utility model content
The purpose of this utility model overcomes above-mentioned shortcoming of the prior art, there is provided a kind of to be connected with test board by host computer, facilitate tester that specific test procedure is loaded into test board, thus corresponding test procedure can be provided for different FPGA, and then FPGA actual working state can be reflected more accurately, promote test data accuracy, ensure testing efficiency, and application mode is easy, realize the general FPGA test macro that cost is comparatively cheap.
In order to realize above-mentioned object, general FPGA test macro of the present utility model has following formation:
This general FPGA test macro comprises test board and host computer.
Wherein, described test board comprises: test chip, general processor and plug connector.Described test chip is in order to run FPGA test procedure, statistics program generate test data; Described general processor in order to run application, the test chip described in control and the data interaction between described host computer; Described plug connector is in order to realize the data interaction between described test chip and FPGA Target Board to be measured.
Test procedure and application program in order to show described test data, and are loaded into described test chip and described general processor according to operation by described host computer respectively.
In this general FPGA test macro, described test board also comprises Clock management chip and power management chip, described Clock management chip and power management chip are respectively in order to provide clock source and power supply to described test chip, and described test chip provides described clock source and power supply by described plug connector to described FPGA Target Board to be measured.
In this general FPGA test macro, described general processor is Power PC microprocessor.
In this general FPGA test macro, the test chip described in described Power PC microprocessor high-speed serial bus connects.
In this general FPGA test macro, described test board also comprises network chip and gigabit Ethernet mouth, described Power PC microprocessor sequentially pass through described network chip be connected with gigabit Ethernet mouth described in host computer.
In this general FPGA test macro, described test board also comprises ddr interface and test board jtag interface, and described ddr interface is all connected described test chip with test board jtag interface, and described ddr interface also connects described general processor.
In this general FPGA test macro, described FPGA Target Board to be measured comprises fpga chip and test board interface.
Wherein, described fpga chip is in order to the controlling run of the FPGA test procedure run according to described test chip FPGA program to be measured; Described test board interface in order to connect the plug connector of described test board, the test chip described in realization and the data interaction between described fpga chip.
In this general FPGA test macro, described FPGA Target Board to be measured also comprises Target Board jtag interface, the fpga chip described in described Target Board jtag interface connects.
Have employed the general FPGA test macro of this utility model, it comprises test board and host computer.Wherein test board comprises test chip, general processor and plug connector.Described test chip is in order to run FPGA test procedure, statistics program generate test data; Described general processor in order to run application, and control described in test chip and described host computer between data interaction; Test procedure and application program then in order to show described test data, and are loaded into described test chip and described general processor according to operation by host computer respectively.Thus, tester can utilize host computer easily, and for different FPGA to be measured, specific test procedure, statistics program and application program are loaded into test board, and then the actual working state of FPGA to be measured can be reflected more accurately, promote test data accuracy, ensure testing efficiency, and general FPGA test macro application mode of the present utility model is easy, realizes cost also comparatively cheap.
Accompanying drawing explanation
Fig. 1 is the system chart of general FPGA test macro of the present utility model.
Embodiment
In order to more clearly understand technology contents of the present utility model, describe in detail especially exemplified by following examples.
Referring to shown in Fig. 1, is the system chart of general FPGA test macro of the present utility model.
In one embodiment, this general FPGA test macro specifically comprises test board and host computer.
Wherein, described test board comprises: test chip, general processor and plug connector.Described test chip is in order to run FPGA test procedure, statistics program generate test data; Described general processor in order to run application, the test chip described in control and the data interaction between described host computer; Described plug connector is in order to realize the data interaction between described test chip and FPGA Target Board to be measured.
Test procedure and application program in order to show described test data, and are loaded into described test chip and described general processor according to operation by described host computer respectively.
In one more preferably embodiment, described test board also comprises Clock management chip and power management chip, described Clock management chip and power management chip are respectively in order to provide clock source and power supply to described test chip, and described test chip provides described clock source and power supply by described plug connector to described FPGA Target Board to be measured.
In another kind more preferably embodiment, described general processor is Power PC microprocessor.Test chip described in this Power PC microprocessor high-speed serial bus connects.And described test board also comprises network chip and gigabit Ethernet mouth, described Power PC microprocessor sequentially pass through described network chip be connected with gigabit Ethernet mouth described in host computer.
In further preferred embodiment, described test board also comprises ddr interface and test board jtag interface, and described ddr interface is all connected described test chip with test board jtag interface, and described ddr interface also connects described general processor.
In preferred embodiment, described FPGA Target Board to be measured comprises fpga chip, test board interface and Target Board jtag interface.Wherein, described fpga chip is in order to the controlling run of the FPGA test procedure run according to described test chip FPGA program to be measured; Described test board interface in order to connect the plug connector of described test board, the test chip described in realization and the data interaction between described fpga chip.Fpga chip described in described Target Board jtag interface connects.
In actual applications, general FPGA test macro of the present utility model is mainly in order to carry out function and the performance test of plate level for the code based on FPGA.Its function is achieved in the following manner.
Whole general FPGA test macro is made up of, by loading different test procedures and the corresponding test function of software simulating parts such as Target Board, test board, host computer, testing software and man-machine interfaces.
Target Board is the carrying board of tested FPGA software, mainly according to the core board that the fpga chip adopted in actual items customizes.Test board is the carrying board of test procedure, statistics program and host computer interface software, major function is testing results program, test data is sent to test board, the output data of tested software are received from test board clamping, and carry out corresponding statistical study, as required output data or analysis data are sent to host computer.Host computer is mainly used in showing the output data of tested application program and the statistics of application program operation conditions, and test procedure can pass through host computer on-line loaded in addition.
Test macro specifically comprises following part:
Target Board, mainly comprises tested fpga chip, jtag interface and the interface with test board.Tested fpga chip clock and power supply are provided by test board, control by test board FPGA.Connector between Target Board and test board, provides the data interaction path between tested FPGA and test FPGA.
Test board: comprise the compositions such as Clock management, power management, test fpga chip, POWER PC chip, network interface chip, DDR and jtag interface.Clock management provides clock source for whole system; Power management provides corresponding power supply for whole system; The clock of test fpga chip testing results program, statistics program, control objectives plate and power management, with tested fpga chip interactive testing data and operation result data; GPP is general processor, and this programme is intended adopting POWER PC, and be responsible for utilizing Rapid IO high-speed serial bus and gigabit Ethernet mouth to carry out data transmission between test chip and host computer, the application of GPP makes whole system have good extendability.
Host computer: man-machine interface is provided, the information such as the data that display gathers and statistics.In addition, the various test procedure on test fpga chip and the application program on GPP can pass through host computer on-line loaded.The test interface that host computer can provide for tester, all test datas, detecting information, control information all will be presented to tester by man-machine interface.
Have employed the general FPGA test macro of this utility model, it comprises test board and host computer.Wherein test board comprises test chip, general processor and plug connector.Described test chip is in order to run FPGA test procedure, statistics program generate test data; Described general processor in order to run application, and control described in test chip and described host computer between data interaction; Test procedure and application program then in order to show described test data, and are loaded into described test chip and described general processor according to operation by host computer respectively.Thus, tester can utilize host computer easily, and for different FPGA to be measured, specific test procedure, statistics program and application program are loaded into test board, and then the actual working state of FPGA to be measured can be reflected more accurately, promote test data accuracy, ensure testing efficiency, and general FPGA test macro application mode of the present utility model is easy, realizes cost also comparatively cheap.
In this description, the utility model is described with reference to its specific embodiment.But, still can make various amendment and conversion obviously and not deviate from spirit and scope of the present utility model.Therefore, instructions and accompanying drawing are regarded in an illustrative, rather than a restrictive.
Claims (8)
1. a general FPGA test macro, is characterized in that, comprises test board and host computer, and wherein, described test board comprises:
Test chip, in order to run FPGA test procedure, statistics program generate test data;
General processor, in order to run application, the test chip described in control and the data interaction between described host computer; And
Plug connector, in order to realize the data interaction between described test chip and FPGA Target Board to be measured;
Described host computer, in order to show described test data, and is loaded into described test chip and described general processor according to operation by test procedure and application program respectively.
2. general FPGA test macro according to claim 1, it is characterized in that, described test board also comprises Clock management chip and power management chip, described Clock management chip and power management chip are respectively in order to provide clock source and power supply to described test chip, and described test chip provides described clock source and power supply by described plug connector to described FPGA Target Board to be measured.
3. general FPGA test macro according to claim 1, is characterized in that, described general processor is Power PC microprocessor.
4. general FPGA test macro according to claim 3, is characterized in that, the test chip described in described PowerPC high-speed serial bus connects.
5. general FPGA test macro according to claim 3, it is characterized in that, described test board also comprises network chip and gigabit Ethernet mouth, described Power PC microprocessor sequentially pass through described network chip be connected with gigabit Ethernet mouth described in host computer.
6. general FPGA test macro according to claim 1, it is characterized in that, described test board also comprises ddr interface and test board jtag interface, and described ddr interface is all connected described test chip with test board jtag interface, and described ddr interface also connects described general processor.
7. general FPGA test macro according to any one of claim 1 to 6, is characterized in that, described FPGA Target Board to be measured comprises:
Fpga chip, the FPGA program that the controlling run in order to the FPGA test procedure run according to described test chip is to be measured;
Test board interface, in order to connect the plug connector of described test board, the test chip described in realization and the data interaction between described fpga chip.
8. general FPGA test macro according to claim 7, is characterized in that, described FPGA Target Board to be measured also comprises Target Board jtag interface, the fpga chip described in described Target Board jtag interface connects.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520362859.7U CN204631211U (en) | 2015-05-29 | 2015-05-29 | A kind of general FPGA test macro |
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| CN201520362859.7U CN204631211U (en) | 2015-05-29 | 2015-05-29 | A kind of general FPGA test macro |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108107352A (en) * | 2017-12-06 | 2018-06-01 | 中国电子产品可靠性与环境试验研究所 | FPGA device tests system and method |
| CN109541440A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of chip detecting method based on FPGA/MCU |
| WO2019109284A1 (en) * | 2017-12-07 | 2019-06-13 | 深圳市汇顶科技股份有限公司 | Debugger and chip debugging method |
| CN111090039A (en) * | 2019-11-07 | 2020-05-01 | 上海精密计量测试研究所 | FPGA function test method and device |
| CN112416676A (en) * | 2020-11-18 | 2021-02-26 | 上海磐启微电子有限公司 | Testing tool applied to testing chip |
-
2015
- 2015-05-29 CN CN201520362859.7U patent/CN204631211U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108107352A (en) * | 2017-12-06 | 2018-06-01 | 中国电子产品可靠性与环境试验研究所 | FPGA device tests system and method |
| WO2019109284A1 (en) * | 2017-12-07 | 2019-06-13 | 深圳市汇顶科技股份有限公司 | Debugger and chip debugging method |
| CN109541440A (en) * | 2018-12-29 | 2019-03-29 | 西安智多晶微电子有限公司 | A kind of chip detecting method based on FPGA/MCU |
| CN111090039A (en) * | 2019-11-07 | 2020-05-01 | 上海精密计量测试研究所 | FPGA function test method and device |
| CN112416676A (en) * | 2020-11-18 | 2021-02-26 | 上海磐启微电子有限公司 | Testing tool applied to testing chip |
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Address after: 200063 Shanghai, Putuo District, home to talk about Road No. 28 10H Patentee after: SHANGHAI XINHUANG INDUSTRIAL CO., LTD. Address before: 200063 Shanghai city Putuo District Tan Hydropower Road No. 28 10H Patentee before: SHANGHAI XINHUANG INDUSTRIAL CO., LTD. |
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