CN204630636U - The circuit of drainage pipeline networks liquid level detection device - Google Patents
The circuit of drainage pipeline networks liquid level detection device Download PDFInfo
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- CN204630636U CN204630636U CN201520165638.0U CN201520165638U CN204630636U CN 204630636 U CN204630636 U CN 204630636U CN 201520165638 U CN201520165638 U CN 201520165638U CN 204630636 U CN204630636 U CN 204630636U
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Abstract
The circuit that the utility model discloses a kind of drainage pipeline networks liquid level detection device comprises single chip machine controlling circuit, signal generating circuit and output circuit.Single chip machine controlling circuit basic circuit comprises CPU, power module of voltage regulation circuit, voltage filter modular circuit, voltage transformation module circuit, serial ports download modular circuit, clock module circuit, debugging module circuit, start modular circuit and CAN transceiver module circuit; Signal generating circuit mainly comprises voltage-stabilized power supply circuit, square wave circuit for generating, sine wave generating circuit, filtering circuit and amplifying circuit.Output circuit comprises Resonance detector circuit, capacitive detection circuit and voltage comparator circuit.Components and parts mature and reliable, with low cost, abundance that the utility model adopts.
Description
Technical field
The utility model belongs to technical field of industrial control, relates to a kind of circuit, is specifically related to a kind of circuit of drainage pipeline networks liquid level detection device.
Background technology
Along with the develop rapidly in city, municipal drainage has become one of bottleneck of restriction rapid urban.Municipal drainage is mainly for the existing pumping equipment in city, and by unwatering system pipe net leakage rate and Real-time Monitoring Data, global optimization unwatering system runs, and improves the comprehensive operation efficiency of pumping plant network, saves energy and reduce the cost, improve pre-flood, the flood control capacity in city.Therefore, the pick-up unit of drainage pipeline networks is very important.
In the detection of drainage pipeline networks, level sensing is a very important aspect.Because the generation of most urban waterlogging is all because the liquid level can not monitoring drainage pipeline networks well produces.The reliability of level sensing, promptness also become most important.
Summary of the invention
The purpose of this utility model is exactly imperfect for draining field correlation technique, provides a kind of circuit of drainage pipeline networks condensate tank of dehumidifier that is reliable, stable, that can communicate.
The circuit of a kind of drainage pipeline networks liquid level detection device of the utility model comprises single chip machine controlling circuit, signal generating circuit and output circuit.
Single chip machine controlling circuit basic circuit comprises CPU, power module of voltage regulation circuit, voltage filter modular circuit, voltage transformation module circuit, serial ports download modular circuit, clock module circuit, debugging module circuit, start modular circuit and CAN transceiver module circuit; Described CPU adopts STM32F103Rc chip;
Described power module of voltage regulation circuit comprises five electric capacity.Wherein one end of the first filter capacitor C7, one end of the second filter capacitor C8, one end of the 3rd filter capacitor C9, one end of the 4th filter capacitor C10, one end of the 5th filter capacitor C11 are all held with power supply VCC and are connected, other one end all ground connection of five filter capacitors.
Described voltage filter module is by two electric capacity.Wherein one end of the 6th filter capacitor C14, one end of the 7th filter capacitor C13 are all connected with one end of analog power AVCC and connect 13 pin of CPU, other one end all ground connection AGND in analog of two filter capacitors.
Described voltage transformation module comprises two electric capacity.Wherein one end of the 8th filter capacitor C15 is connected with 47 pin of CPU, other end ground connection.One end of 9th filter capacitor C16 is connected with 31 pin of CPU, other end ground connection.
The described serial ports module that downloads comprises three resistance and an electric capacity.One end of first divider resistance R5 is connected with one end of the second divider resistance R7, the 3rd divider resistance R8.Another termination power VCC of the first divider resistance R5, the other end of the second divider resistance R7 is connected with the pin 60 of CPU.One end of first storage capacitor C12 is connected with the NRST interface of CPU, and the other end is connected with the other end of the 3rd divider resistance R8 and ground connection.
Described clock module comprises a crystal oscillator and two electric capacity; One end of first crystal oscillator Y1 is connected with one end of the second storage capacitor C1, and is connected with the pin 6 of CPU; The other end of the first crystal oscillator Y1 is connected with one end of the 3rd storage capacitor C2, and is connected with the pin 5 of CPU.The other end of the first storage capacitor C1, the other end ground connection of the second storage capacitor C2.
Described debugging module comprises a light emitting diode and a resistance.One end of 4th divider resistance R6 is connected with the PA15/JTDI pin of CPU, and the other end is connected with the positive pole of light emitting diode DS1, the minus earth of light emitting diode DS1.
Described startup module comprises a resistance.One end of first pull-up resistor R9 is connected with the pin two 8 of CPU, other end ground connection.
Described CAN transceiver module comprises four resistance, three electric capacity, four Transient Suppression Diodes and CAN Interface integration chip U1; The model of CAN Interface integration chip U1 is SN65HVD1050; The anode of the first Transient Suppression Diode TVS1, the anode of the second Transient Suppression Diode TVS2, the anode of the 3rd Transient Suppression Diode TVS3, the anode of the 4th Transient Suppression Diode TVS1 are connected with the positive pole of cross thermopair.The negative electrode of the first Transient Suppression Diode TVS1, the negative electrode of the second Transient Suppression Diode TVS2 are connected with 7 pin of CAN Interface integration chip U1.The negative electrode of the 3rd Transient Suppression Diode TVS3, the negative electrode of the 4th Transient Suppression Diode TVS4 are connected with 6 pin of CAN Interface integration chip U1.4 pin of CAN Interface integration chip U1 are connected with one end of the second pull-up resistor R1,1 pin of CAN Interface integration chip U1 is connected with one end of the 3rd pull-up resistor R2, and the other end of the second pull-up resistor R1 is connected with one end of the other end of the 3rd pull-up resistor R2, the 9th filter capacitor C5 one end, the tenth filter capacitor C6 and the pin 3 of CAN Interface integration chip U1 and connects+5V power supply.The other end of the 9th filter capacitor C5 other end, the tenth filter capacitor C6 and the pin two of CAN Interface integration chip U1 connect and ground connection, the pin 5 of CAN Interface integration chip U1 is connected with one end of the 11 filter capacitor C4, the other end ground connection of the 11 filter capacitor C4, the pin 8 of CAN Interface integration chip U1 is unsettled;
12 pin of described CPU connect digitally, and 18 pin, 67 pin connect digitally, and 19 pin, 64 pin, 48 pin, 32 pin meet VCC; The pin that CPU does not mention in this article is all built on stilts;
4 pin of connector RJ1,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 4 pin of connector RJ2,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 1 pin of connector P_CANH1 is connected with 7 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 4th pull-up resistor R3,1 pin of connector P_CANL1 is connected with 6 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 5th pull-up resistor R4, the other end of the 4th pull-up resistor R3 is connected with the other end of the 5th pull-up resistor R4, one end of the 28 filter capacitor C3, the other end ground connection of the 28 filter capacitor C3;
In addition also have externally fed interface JP1, pin one meets power supply VCC, and pin two meets analog power AVCC, and pin 3 meets VEE, pin 4 ground connection.Power supply interface JP2, pin one meets power supply VCC, and pin two connects the pin 46 of CPU, and pin 3 connects the pin 49 of CPU, pin 4 ground connection.
Signal generating circuit comprises voltage-stabilized power supply circuit, square wave circuit for generating, sine wave generating circuit, filtering circuit and amplifying circuit.
Described voltage-stabilized power supply circuit comprises two electric capacity.One end of 12 filter capacitor C27 is connected with one end of the 13 filter capacitor C28 and meets power supply VCC, and the 12 filter capacitor C27 is connected with the other end of the 13 filter capacitor C28 and ground connection.
Described square wave circuit for generating comprises a passive crystal oscillator and an electric capacity.One end of 14 filter capacitor C36 is connected with 4 pin of passive crystal oscillator X17 and meets power supply VCC, and the other end of the 14 filter capacitor C36 is connected with the pin two of passive crystal oscillator X17 and ground connection, and the pin one of passive crystal oscillator X17 is maked somebody a mere figurehead.
Described sine wave generating circuit comprises 9833 chip U19, two electric capacity.One end of 15 filter capacitor C26 is connected with the pin one of 9833 chip U19, and the other end of the 15 filter capacitor C26, the pin two of 9833 chip U19 are connected and meet power supply VCC.One end of 14 filter capacitor C33 is connected with the pin 3 of 9833 chip U19, and the other end of the 14 filter capacitor C33, the pin 4 of 9833 chip U19 are connected and ground connection.The pin 5 of 9833 chip U19 is connected with the pin 3 of passive crystal oscillator X17.The 9 pin ground connection of 9833 chip U19.The pin 6 of 9833 chip U19, pin 7, pin 8 respectively with CPU pin 36, pin 35, pin 34 be connected.
Described filtering circuit comprises two resistance, five electric capacity and two inductance.The pin one 0 of one end of the first filter resistance R33, one end of the 17 filter capacitor C35 and 9833 chip U19 is connected.The other end of the first filter resistance R33 and the other end ground connection of the 17 filter capacitor C35.One end of one end of 18 filter capacitor C30 and one end of the 19 filter capacitor C31, the 20 filter capacitor C34, one end of the first filter inductance L18, one end of the second filter inductance L19 are connected, and the other end of the 18 filter capacitor C30 is connected with the pin one 0 of the other end of the first filter inductance L18,9833 chip U19.The other end of the second filter inductance L19 is connected with the other end of the 19 filter capacitor C31, one end of the 21 filter capacitor C32, one end of the second filter resistance R32, one end of the first coupling capacitance C29.The other end ground connection of the other end of the 20 filter capacitor C34, the other end of the 21 filter capacitor C32 and the second filter resistance R32.
Described amplifying circuit comprises two resistance, electric capacity, an operational amplifier; The model of described operational amplifier P18 is EL5100W;
One end of 27 filter capacitor C25 is connected with one end of one end of the 3rd filter resistance R30, the 4th filter resistance R31, the reverse input end IN-pin of operational amplifier P18, and the other end of the 27 filter capacitor C25 is connected with output terminal 0 pin of the other end of the 3rd filter resistance R30, operational amplifier P18.4th filter resistance R31 is connected with the EN pin of operational amplifier P18 and ground connection.The IN+ of end in the same way of operational amplifier P18 is connected with the first coupling capacitance C29.The V+ pin of operational amplifier P18 meets power supply VCC, and the V-pin of operational amplifier P18 meets power supply VEE,
Output circuit comprises Resonance detector circuit, capacitive detection circuit and voltage comparator circuit.
Described Resonance detector circuit comprises eight resistance, three electric capacity, two comparator module, an XOR gate module and inductance, wherein the model of comparer U17A and comparer U17B is LM2903DR2, XOR gate U18A, the model of XOR gate U18B and XOR gate U18C is MC74AC86D;
One end of the 4th described divider resistance R26 is connected with the output terminal O pin of one end of the 3rd inductance L 17, operational amplifier P18, the other end of the 4th divider resistance R26 is connected with the pin 5 of comparer U17B, one end of 5th divider resistance R29 is connected with the pin 6 of comparer U17B, the other end ground connection of the 5th divider resistance R29, the other end of the 3rd filter inductance L17 is connected with the pin two of measured capacitance P17.The pin 7 of comparer U17B is connected with the 6th divider resistance R28, and the other end of the 6th divider resistance R28 is connected with the pin 4 of XOR gate U18B.Pin 4 and the pin 8 of comparer U17B are maked somebody a mere figurehead.
The pin two ground connection of comparer U17A, one end of the 7th divider resistance R22 is connected with the pin one of the pin 3 of comparer U17A, measured capacitance P17, and the 7th divider resistance R22 other end is connected with the pin 4 of comparer U17A and ground connection; The pin 8 of comparer U17A meets power supply VCC.The pin one of comparer U17A is connected with one end of the 8th divider resistance R20, and the other end of the 8th divider resistance R20 is connected with the pin 5 of XOR gate U18B.
One end of 28 filter capacitor C21, one end of the 9th divider resistance R23 and the pin one 4 of CPU are connected, the other end of the 9th resistance R23 is connected with one end of one end of the 29 filter capacitor C22, the tenth point of piezoresistance R24, the other end of the tenth point of piezoresistance R24 is connected with one end of the 30 filter capacitor C23, one end of the 11 divider resistance R25, and the other end of the 11 divider resistance R25 is connected with the pin 6 of XOR gate U18B.The other end of the 28 filter capacitor C21, the other end of the 29 filter capacitor C22 and the other end of the 30 filter capacitor C23 are connected and ground connection.
Described capacitive detection circuit comprises three resistance and three electric capacity.One end of 31 filter capacitor C17 is connected with one end of the 12 divider resistance R17, the pin one 5 of CPU, the other end of the 12 divider resistance R17 is connected with one end of the 32 filter capacitor C18, one end of the 13 divider resistance R18, the other end of the 13 divider resistance R18 is connected with one end of the 33 filter capacitor C19, one end of the 14 divider resistance R19, and the other end of the 14 divider resistance R19 is connected with the pin one of comparer U17A.
Described voltage comparator circuit comprises two XOR gate, two resistance and two electric capacity.The pin one ground connection of XOR gate U18A, the pin two of XOR gate U18A meets power supply VCC.One end of 15 divider resistance R21 is connected with one end of the 34 filter capacitor C20, the pin one 6 of CPU.The other end ground connection of the 34 filter capacitor C20, the other end of the 15 divider resistance R21 is connected with the pin 3 of XOR gate U18A.The pin 9 of XOR gate U18C, pin one 0 are connected and ground connection.One end of 16 divider resistance R27 is connected with one end of the 35 filter capacitor C24, the pin one 7 of CPU.The other end ground connection of the 35 filter capacitor C24, the other end of the 16 divider resistance R27 is connected with the pin 8 of XOR gate U18C.
The testing circuit of the utility model design, adopts contactless method to detect the water level of drainage pipeline networks, eliminates pipe network environment inner complicated and changeable to the interference of Monitoring Data, more reliably.Install the method for capacitor plate additional in pipe network outside simple to operation, by potential method and the capacitance recorded after making finer filter accurately can detect pipe network water level, reach desirable effect.Components and parts mature and reliable, with low cost, abundance that the utility model adopts.
Accompanying drawing explanation
Modular circuit that Fig. 1 is CPU in RAM plate basic circuit part of the present utility model, power module of voltage regulation circuit, voltage filter modular circuit, voltage transformation module circuit, serial ports download, clock module circuit, debugging module circuit and start modular circuit part;
Fig. 2 is the CAN transceiver module circuit part in the RAM plate basic circuit part of utility model;
Fig. 3 is that power supply interface JP1 schemes;
Fig. 4 is that power supply interface JP2 schemes;
Fig. 5 signal generating circuit figure;
Fig. 6 output circuit figure.
Embodiment
Implement below in conjunction with schematic diagram and concrete operations that the utility model is described in further detail, have a more deep understanding to help the researcher of association area to thought of the present utility model.
As shown in Figure 1, a kind of circuit of drainage pipeline networks liquid level detection device comprises single chip machine controlling circuit, signal generating circuit and output circuit.
Single chip machine controlling circuit basic circuit comprises CPU, power module of voltage regulation circuit, voltage filter modular circuit, voltage transformation module circuit, serial ports download modular circuit, clock module circuit, debugging module circuit, start modular circuit and CAN transceiver module circuit; Described CPU adopts STM32F103Rc chip;
Described power module of voltage regulation circuit comprises five electric capacity.Wherein one end of the first filter capacitor C7, one end of the second filter capacitor C8, one end of the 3rd filter capacitor C9, one end of the 4th filter capacitor C10, one end of the 5th filter capacitor C11 are all held with power supply VCC and are connected, other one end all ground connection of five filter capacitors.
Described voltage filter module is by two electric capacity.Wherein one end of the 6th filter capacitor C14, one end of the 7th filter capacitor C13 are all connected with one end of analog power AVCC and connect 13 pin of CPU, other one end all ground connection AGND in analog of two filter capacitors.
Described voltage transformation module comprises two electric capacity.Wherein one end of the 8th filter capacitor C15 is connected with 47 pin of CPU, other end ground connection.One end of 9th filter capacitor C16 is connected with 31 pin of CPU, other end ground connection.
The described serial ports module that downloads comprises three resistance and an electric capacity.One end of first divider resistance R5 is connected with one end of the second divider resistance R7, the 3rd divider resistance R8.Another termination power VCC of the first divider resistance R5, the other end of the second divider resistance R7 is connected with the pin 60 of CPU.One end of first storage capacitor C12 is connected with the NRST interface of CPU, and the other end is connected with the other end of the 3rd divider resistance R8 and ground connection.
Described clock module comprises a crystal oscillator and two electric capacity; One end of first crystal oscillator Y1 is connected with one end of the second storage capacitor C1, and is connected with the pin 6 of CPU; The other end of the first crystal oscillator Y1 is connected with one end of the 3rd storage capacitor C2, and is connected with the pin 5 of CPU.The other end of the first storage capacitor C1, the other end ground connection of the second storage capacitor C2.
Described debugging module comprises a light emitting diode and a resistance.One end of 4th divider resistance R6 is connected with the PA15/JTDI pin of CPU, and the other end is connected with the positive pole of light emitting diode DS1, the minus earth of light emitting diode DS1.
Described startup module comprises a resistance.One end of first pull-up resistor R9 is connected with the pin two 8 of CPU, other end ground connection.
As shown in Figure 2, described CAN transceiver module comprises four resistance, three electric capacity, four Transient Suppression Diodes and CAN Interface integration chip U1; The model of CAN Interface integration chip U1 is SN65HVD1050; The anode of the first Transient Suppression Diode TVS1, the anode of the second Transient Suppression Diode TVS2, the anode of the 3rd Transient Suppression Diode TVS3, the anode of the 4th Transient Suppression Diode TVS1 are connected with the positive pole of cross thermopair.The negative electrode of the first Transient Suppression Diode TVS1, the negative electrode of the second Transient Suppression Diode TVS2 are connected with 7 pin of CAN Interface integration chip U1.The negative electrode of the 3rd Transient Suppression Diode TVS3, the negative electrode of the 4th Transient Suppression Diode TVS4 are connected with 6 pin of CAN Interface integration chip U1.4 pin of CAN Interface integration chip U1 are connected with one end of the second pull-up resistor R1,1 pin of CAN Interface integration chip U1 is connected with one end of the 3rd pull-up resistor R2, and the other end of the second pull-up resistor R1 is connected with one end of the other end of the 3rd pull-up resistor R2, the 9th filter capacitor C5 one end, the tenth filter capacitor C6 and the pin 3 of CAN Interface integration chip U1 and connects+5V power supply.The other end of the 9th filter capacitor C5 other end, the tenth filter capacitor C6 and the pin two of CAN Interface integration chip U1 connect and ground connection, the pin 5 of CAN Interface integration chip U1 is connected with one end of the 11 filter capacitor C4, the other end ground connection of the 11 filter capacitor C4, the pin 8 of CAN Interface integration chip U1 is unsettled;
12 pin of described CPU connect digitally, and 18 pin, 67 pin connect digitally, and 19 pin, 64 pin, 48 pin, 32 pin meet VCC; The pin that CPU does not mention in this article is all built on stilts;
As shown in Figure 3,4 pin of RJ1,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 4 pin of connector RJ2,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 1 pin of connector P_CANH1 is connected with 7 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 4th pull-up resistor R3,1 pin of connector P_CANL1 is connected with 6 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 5th pull-up resistor R4, the other end of the 4th pull-up resistor R3 is connected with the other end of the 5th pull-up resistor R4, one end of the 28 filter capacitor C3, the other end ground connection of the 28 filter capacitor C3;
As shown in Figure 4, also have externally fed interface JP1 in addition, pin one meets power supply VCC, and pin two meets analog power AVCC, and pin 3 meets VEE, pin 4 ground connection.Power supply interface JP2, pin one meets power supply VCC, and pin two connects the pin 46 of CPU, and pin 3 connects the pin 49 of CPU, pin 4 ground connection.
As shown in Figure 5, signal generating circuit comprises voltage-stabilized power supply circuit, square wave circuit for generating, sine wave generating circuit, filtering circuit and amplifying circuit.
Described voltage-stabilized power supply circuit comprises two electric capacity.One end of 12 filter capacitor C27 is connected with one end of the 13 filter capacitor C28 and meets power supply VCC, and the 12 filter capacitor C27 is connected with the other end of the 13 filter capacitor C28 and ground connection.
Described square wave circuit for generating comprises a passive crystal oscillator and an electric capacity.One end of 14 filter capacitor C36 is connected with 4 pin of passive crystal oscillator X17 and meets power supply VCC, and the other end of the 14 filter capacitor C36 is connected with the pin two of passive crystal oscillator X17 and ground connection, and the pin one of passive crystal oscillator X17 is maked somebody a mere figurehead.
Described sine wave generating circuit comprises 9833 chip U19, two electric capacity.One end of 15 filter capacitor C26 is connected with the pin one of 9833 chip U19, and the other end of the 15 filter capacitor C26, the pin two of 9833 chip U19 are connected and meet power supply VCC.One end of 14 filter capacitor C33 is connected with the pin 3 of 9833 chip U19, and the other end of the 14 filter capacitor C33, the pin 4 of 9833 chip U19 are connected and ground connection.The pin 5 of 9833 chip U19 is connected with the pin 3 of passive crystal oscillator X17.The 9 pin ground connection of 9833 chip U19.The pin 6 of 9833 chip U19, pin 7, pin 8 respectively with CPU pin 36, pin 35, pin 34 be connected.
Described filtering circuit comprises two resistance, five electric capacity and two inductance.The pin one 0 of one end of the first filter resistance R33, one end of the 17 filter capacitor C35 and 9833 chip U19 is connected.The other end of the first filter resistance R33 and the other end ground connection of the 17 filter capacitor C35.One end of one end of 18 filter capacitor C30 and one end of the 19 filter capacitor C31, the 20 filter capacitor C34, one end of the first filter inductance L18, one end of the second filter inductance L19 are connected, and the other end of the 18 filter capacitor C30 is connected with the pin one 0 of the other end of the first filter inductance L18,9833 chip U19.The other end of the second filter inductance L19 is connected with the other end of the 19 filter capacitor C31, one end of the 21 filter capacitor C32, one end of the second filter resistance R32, one end of the first coupling capacitance C29.The other end ground connection of the other end of the 20 filter capacitor C34, the other end of the 21 filter capacitor C32 and the second filter resistance R32.
Described amplifying circuit comprises two resistance, electric capacity, an operational amplifier; The model of described operational amplifier P18 is EL5100W;
One end of 27 filter capacitor C25 is connected with one end of one end of the 3rd filter resistance R30, the 4th filter resistance R31, the reverse input end IN-pin of operational amplifier P18, and the other end of the 27 filter capacitor C25 is connected with output terminal 0 pin of the other end of the 3rd filter resistance R30, operational amplifier P18.4th filter resistance R31 is connected with the EN pin of operational amplifier P18 and ground connection.The IN+ of end in the same way of operational amplifier P18 is connected with the first coupling capacitance C29.The V+ pin of operational amplifier P18 meets power supply VCC, and the V-pin of operational amplifier P18 meets power supply VEE,
As shown in Figure 6, output circuit comprises Resonance detector circuit, capacitive detection circuit and voltage comparator circuit.
Described Resonance detector circuit comprises eight resistance, three electric capacity, two comparator module, an XOR gate module and inductance, wherein the model of comparer U17A and comparer U17B is LM2903DR2, XOR gate U18A, the model of XOR gate U18B and XOR gate U18C is MC74AC86D;
One end of the 4th described divider resistance R26 is connected with the output terminal O pin of one end of the 3rd inductance L 17, operational amplifier P18, the other end of the 4th divider resistance R26 is connected with the pin 5 of comparer U17B, one end of 5th divider resistance R29 is connected with the pin 6 of comparer U17B, the other end ground connection of the 5th divider resistance R29, the other end of the 3rd filter inductance L17 is connected with the pin two of measured capacitance P17.The pin 7 of comparer U17B is connected with the 6th divider resistance R28, and the other end of the 6th divider resistance R28 is connected with the pin 4 of XOR gate U18B.Pin 4 and the pin 8 of comparer U17B are maked somebody a mere figurehead.
The pin two ground connection of comparer U17A, one end of the 7th divider resistance R22 is connected with the pin one of the pin 3 of comparer U17A, measured capacitance P17, and the 7th divider resistance R22 other end is connected with the pin 4 of comparer U17A and ground connection; The pin 8 of comparer U17A meets power supply VCC.The pin one of comparer U17A is connected with one end of the 8th divider resistance R20, and the other end of the 8th divider resistance R20 is connected with the pin 5 of XOR gate U18B.
One end of 28 filter capacitor C21, one end of the 9th divider resistance R23 and the pin one 4 of CPU are connected, the other end of the 9th resistance R23 is connected with one end of one end of the 29 filter capacitor C22, the tenth point of piezoresistance R24, the other end of the tenth point of piezoresistance R24 is connected with one end of the 30 filter capacitor C23, one end of the 11 divider resistance R25, and the other end of the 11 divider resistance R25 is connected with the pin 6 of XOR gate U18B.The other end of the 28 filter capacitor C21, the other end of the 29 filter capacitor C22 and the other end of the 30 filter capacitor C23 are connected and ground connection.
Described capacitive detection circuit comprises three resistance and three electric capacity.One end of 31 filter capacitor C17 is connected with one end of the 12 divider resistance R17, the pin one 5 of CPU, the other end of the 12 divider resistance R17 is connected with one end of the 32 filter capacitor C18, one end of the 13 divider resistance R18, the other end of the 13 divider resistance R18 is connected with one end of the 33 filter capacitor C19, one end of the 14 divider resistance R19, and the other end of the 14 divider resistance R19 is connected with the pin one of comparer U17A.
Described voltage comparator circuit comprises two XOR gate, two resistance and two electric capacity.The pin one ground connection of XOR gate U18A, the pin two of XOR gate U18A meets power supply VCC.One end of 15 divider resistance R21 is connected with one end of the 34 filter capacitor C20, the pin one 6 of CPU.The other end ground connection of the 34 filter capacitor C20, the other end of the 15 divider resistance R21 is connected with the pin 3 of XOR gate U18A.The pin 9 of XOR gate U18C, pin one 0 are connected and ground connection.One end of 16 divider resistance R27 is connected with one end of the 35 filter capacitor C24, the pin one 7 of CPU.The other end ground connection of the 35 filter capacitor C24, the other end of the 16 divider resistance R27 is connected with the pin 8 of XOR gate U18C.
The course of work:
The circuit groundwork flow process of drainage pipeline networks liquid level detection device is as follows, after circuit powers on, pull-up resistor R9 is to singlechip control chip U2 Injection Current, the right filter capacitor of voltage-stabilized power supply circuit carries out filtering to supply voltage, to singlechip control chip U2 injecting voltage, crystal oscillating circuit provides operation clock to singlechip control chip U2, the serial ports module that downloads starts to download, singlechip control chip U2 comes into operation, light emitting diode DS1 is bright, and CAN transmission circuit is by CAN agreement transceiving data.The pin 3 of passive crystal oscillator X17 exports a square-wave signal to the pin 5 of signal generator U10, single-chip microcomputer produces control signal and waveform parameter, by serial line interface, data are sent to 9833 chip U10, the sine wave signal that the pin one 0 through U10 exports exports after being low-pass filtered.Because 9833 do not possess amplitude modulation function, therefore add rear class operational amplifier in circuit and necessary regulation and control is carried out to the amplitude of signal.Sinusoidal signal after filtering circuit filtering export, through the in-phase input end IN+ of coupling capacitance C29 input operational amplifier.The output terminal O of operational amplifier P18 and inverting input IN-are connected by the filter capacitor C25 that is connected in parallel and feedback resistance R30, form a kind of negative feedback.Output terminal O exports the sine wave signal after amplifying, sine wave signal is through the in-phase input end pin 5 of divider resistance R26 input comparator U17B, sine wave signal is transformed into square-wave signal by comparer U17B, is input to the port 4 of XOR gate U18 through the time delay of divider resistance R28; The sine wave signal exported on the other hand is after the effect of inductance L 17 and measured capacitance P17, and be input to the in-phase input end pin 3 of comparer U17A, sine wave signal is transformed into square-wave signal by comparer U17A.When feedback resistance R22, inductance L 17, measured capacitance P17 and effect sine wave signal frequency thereon arrive resonance requirement, feedback resistance R22, inductance L 17 and measured capacitance P17 and a formation RLC series resonant circuit.From the in-phase input end 3 of the sine wave signal input comparator U17A that RLC series resonant circuit exports, sine wave signal is transformed into square-wave signal by comparer U17A, and square-wave signal is input to the pin 5 of XOR gate U18B through divider resistance R20 time delay.Both square-wave signals above compare by XOR gate U18A, then the signal after filtering needed for circuit output, if this signal is low level, then and RLC series circuit generation resonance; If this signal is square-wave signal or high level, then there is not resonance in RLC series circuit.Due to after inductance L 17, measured capacitance P17 effect, square-wave signal may be advanced or delayed, so can adjust frequency, makes inductance L 17, measured capacitance P17 resonance, can calculate the value of measured capacitance P17.
The pin one of XOR gate U18A, pin two ground connection, power supply VCC respectively, according to the principle of work of XOR gate, output terminal pin 3 exports high level all the time, filtering output is carried out through divider resistance R21 and filter capacitor C20, the pin 9 of XOR gate U18C and pin one 0 ground connection, according to the principle of work of XOR gate, output terminal pin 8 output low level all the time, carries out filtering output through divider resistance R27 and filter capacitor C24.The low level more than exported, square-wave signal or high level are all between high level herein and low level.Can judge that whether the measured value of gained is effective.
From the square-wave signal circuit filtering output after filtering that comparer U17A exports, decision circuitry whether normally work can be started.
Claims (1)
1. the circuit of drainage pipeline networks liquid level detection device, comprises single chip machine controlling circuit, signal generating circuit and output circuit;
It is characterized in that: single chip machine controlling circuit basic circuit comprises CPU, power module of voltage regulation circuit, voltage filter modular circuit, voltage transformation module circuit, serial ports download modular circuit, clock module circuit, debugging module circuit, start modular circuit and CAN transceiver module circuit; Described CPU adopts STM32F103Rc chip;
Described power module of voltage regulation circuit comprises five electric capacity; Wherein one end of the first filter capacitor C7, one end of the second filter capacitor C8, one end of the 3rd filter capacitor C9, one end of the 4th filter capacitor C10, one end of the 5th filter capacitor C11 are all held with power supply VCC and are connected, other one end all ground connection of five filter capacitors;
Described voltage filter module comprises two electric capacity; Wherein one end of the 6th filter capacitor C14, one end of the 7th filter capacitor C13 are all connected with one end of analog power AVCC and connect 13 pin of CPU, other one end all ground connection AGND in analog of two filter capacitors;
Described voltage transformation module comprises two electric capacity; Wherein one end of the 8th filter capacitor C15 is connected with 47 pin of CPU, other end ground connection; One end of 9th filter capacitor C16 is connected with 31 pin of CPU, other end ground connection;
The described serial ports module that downloads comprises three resistance and an electric capacity; One end of first divider resistance R5 is connected with one end of the second divider resistance R7, the 3rd divider resistance R8; Another termination power VCC of the first divider resistance R5, the other end of the second divider resistance R7 is connected with the pin 60 of CPU; One end of first storage capacitor C12 is connected with the NRST interface of CPU, and the other end is connected with the other end of the 3rd divider resistance R8 and ground connection;
Described clock module comprises a crystal oscillator and two electric capacity; One end of first crystal oscillator Y1 is connected with one end of the second storage capacitor C1, and is connected with the pin 6 of CPU; The other end of the first crystal oscillator Y1 is connected with one end of the 3rd storage capacitor C2, and is connected with the pin 5 of CPU; The other end of the first storage capacitor C1, the other end ground connection of the second storage capacitor C2;
Described debugging module comprises a light emitting diode and a resistance; One end of 4th divider resistance R6 is connected with the PA15/JTDI pin of CPU, and the other end is connected with the positive pole of light emitting diode DS1, the minus earth of light emitting diode DS1;
Described startup module comprises a resistance; One end of first pull-up resistor R9 is connected with the pin two 8 of CPU, other end ground connection;
Described CAN transceiver module comprises four resistance, three electric capacity, four Transient Suppression Diodes and CAN Interface integration chip U1; The model of CAN Interface integration chip U1 is SN65HVD1050; The anode of the first Transient Suppression Diode TVS1, the anode of the second Transient Suppression Diode TVS2, the anode of the 3rd Transient Suppression Diode TVS3, the anode of the 4th Transient Suppression Diode TVS1 are connected with the positive pole of cross thermopair; The negative electrode of the first Transient Suppression Diode TVS1, the negative electrode of the second Transient Suppression Diode TVS2 are connected with 7 pin of CAN Interface integration chip U1; The negative electrode of the 3rd Transient Suppression Diode TVS3, the negative electrode of the 4th Transient Suppression Diode TVS4 are connected with 6 pin of CAN Interface integration chip U1; 4 pin of CAN Interface integration chip U1 are connected with one end of the second pull-up resistor R1,1 pin of CAN Interface integration chip U1 is connected with one end of the 3rd pull-up resistor R2, and the other end of the second pull-up resistor R1 is connected with one end of the other end of the 3rd pull-up resistor R2, the 9th filter capacitor C5 one end, the tenth filter capacitor C6 and the pin 3 of CAN Interface integration chip U1 and connects+5V power supply; The other end of the 9th filter capacitor C5 other end, the tenth filter capacitor C6 and the pin two of CAN Interface integration chip U1 connect and ground connection, the pin 5 of CAN Interface integration chip U1 is connected with one end of the 11 filter capacitor C4, the other end ground connection of the 11 filter capacitor C4, the pin 8 of CAN Interface integration chip U1 is unsettled;
12 pin of described CPU connect digitally, and 18 pin, 67 pin connect digitally, and 19 pin, 64 pin, 48 pin, 32 pin meet VCC; All the other pins of CPU are all built on stilts;
4 pin of connector RJ1,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 4 pin of connector RJ2,5 pin are connected with 7 pin of CAN Interface integration chip U1,6 pin successively, 1 pin, 2 pin, 3 pin, 6 pin, 7 pin, 8 pin ground connection; 1 pin of connector P_CANH1 is connected with 7 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 4th pull-up resistor R3,1 pin of connector P_CANL1 is connected with 6 pin of CAN Interface integration chip U1,2 pin are connected with one end of the 5th pull-up resistor R4, the other end of the 4th pull-up resistor R3 is connected with the other end of the 5th pull-up resistor R4, one end of the 28 filter capacitor C3, the other end ground connection of the 28 filter capacitor C3;
In addition also have externally fed interface JP1, pin one meets power supply VCC, and pin two meets analog power AVCC, and pin 3 meets VEE, pin 4 ground connection; Power supply interface JP2, pin one meets power supply VCC, and pin two connects the pin 46 of CPU, and pin 3 connects the pin 49 of CPU, pin 4 ground connection;
Signal generating circuit comprises voltage-stabilized power supply circuit, square wave circuit for generating, sine wave generating circuit, filtering circuit and amplifying circuit;
Described voltage-stabilized power supply circuit comprises two electric capacity; One end of 12 filter capacitor C27 is connected with one end of the 13 filter capacitor C28 and meets power supply VCC, and the 12 filter capacitor C27 is connected with the other end of the 13 filter capacitor C28 and ground connection;
Described square wave circuit for generating comprises a passive crystal oscillator and an electric capacity; One end of 14 filter capacitor C36 is connected with 4 pin of passive crystal oscillator X17 and meets power supply VCC, and the other end of the 14 filter capacitor C36 is connected with the pin two of passive crystal oscillator X17 and ground connection, and the pin one of passive crystal oscillator X17 is maked somebody a mere figurehead;
Described sine wave generating circuit comprises 9833 chip U19, two electric capacity; One end of 15 filter capacitor C26 is connected with the pin one of 9833 chip U19, and the other end of the 15 filter capacitor C26, the pin two of 9833 chip U19 are connected and meet power supply VCC; One end of 14 filter capacitor C33 is connected with the pin 3 of 9833 chip U19, and the other end of the 14 filter capacitor C33, the pin 4 of 9833 chip U19 are connected and ground connection; The pin 5 of 9833 chip U19 is connected with the pin 3 of passive crystal oscillator X17; The 9 pin ground connection of 9833 chip U19; The pin 6 of 9833 chip U19, pin 7, pin 8 respectively with CPU pin 36, pin 35, pin 34 be connected;
Described filtering circuit comprises two resistance, five electric capacity and two inductance; The pin one 0 of one end of the first filter resistance R33, one end of the 17 filter capacitor C35 and 9833 chip U19 is connected; The other end of the first filter resistance R33 and the other end ground connection of the 17 filter capacitor C35; One end of one end of 18 filter capacitor C30 and one end of the 19 filter capacitor C31, the 20 filter capacitor C34, one end of the first filter inductance L18, one end of the second filter inductance L19 are connected, and the other end of the 18 filter capacitor C30 is connected with the pin one 0 of the other end of the first filter inductance L18,9833 chip U19; The other end of the second filter inductance L19 is connected with the other end of the 19 filter capacitor C31, one end of the 21 filter capacitor C32, one end of the second filter resistance R32, one end of the first coupling capacitance C29; The other end ground connection of the other end of the 20 filter capacitor C34, the other end of the 21 filter capacitor C32 and the second filter resistance R32;
Described amplifying circuit comprises two resistance, electric capacity, an operational amplifier; The model of described operational amplifier P18 is EL5100W;
One end of 27 filter capacitor C25 is connected with one end of one end of the 3rd filter resistance R30, the 4th filter resistance R31, the reverse input end IN-pin of operational amplifier P18, and the other end of the 27 filter capacitor C25 is connected with output terminal 0 pin of the other end of the 3rd filter resistance R30, operational amplifier P18; 4th filter resistance R31 is connected with the EN pin of operational amplifier P18 and ground connection; The IN+ of end in the same way of operational amplifier P18 is connected with the first coupling capacitance C29; The V+ pin of operational amplifier P18 meets power supply VCC, and the V-pin of operational amplifier P18 meets power supply VEE,
Output circuit comprises Resonance detector circuit, capacitive detection circuit and voltage comparator circuit;
Described Resonance detector circuit comprises eight resistance, three electric capacity, two comparator module, an XOR gate module and inductance, wherein the model of comparer U17A and comparer U17B is LM2903DR2, XOR gate U18A, the model of XOR gate U18B and XOR gate U18C is MC74AC86D;
One end of the 4th described divider resistance R26 is connected with the output terminal O pin of one end of the 3rd inductance L 17, operational amplifier P18, the other end of the 4th divider resistance R26 is connected with the pin 5 of comparer U17B, one end of 5th divider resistance R29 is connected with the pin 6 of comparer U17B, the other end ground connection of the 5th divider resistance R29, the other end of the 3rd filter inductance L17 is connected with the pin two of measured capacitance P17; The pin 7 of comparer U17B is connected with the 6th divider resistance R28, and the other end of the 6th divider resistance R28 is connected with the pin 4 of XOR gate U18B; Pin 4 and the pin 8 of comparer U17B are maked somebody a mere figurehead;
The pin two ground connection of comparer U17A, one end of the 7th divider resistance R22 is connected with the pin one of the pin 3 of comparer U17A, measured capacitance P17, and the 7th divider resistance R22 other end is connected with the pin 4 of comparer U17A and ground connection; The pin 8 of comparer U17A meets power supply VCC; The pin one of comparer U17A is connected with one end of the 8th divider resistance R20, and the other end of the 8th divider resistance R20 is connected with the pin 5 of XOR gate U18B;
One end of 28 filter capacitor C21, one end of the 9th divider resistance R23 and the pin one 4 of CPU are connected, the other end of the 9th resistance R23 is connected with one end of one end of the 29 filter capacitor C22, the tenth point of piezoresistance R24, the other end of the tenth point of piezoresistance R24 is connected with one end of the 30 filter capacitor C23, one end of the 11 divider resistance R25, and the other end of the 11 divider resistance R25 is connected with the pin 6 of XOR gate U18B; The other end of the 28 filter capacitor C21, the other end of the 29 filter capacitor C22 and the other end of the 30 filter capacitor C23 are connected and ground connection;
Described capacitive detection circuit comprises three resistance and three electric capacity; One end of 31 filter capacitor C17 is connected with one end of the 12 divider resistance R17, the pin one 5 of CPU, the other end of the 12 divider resistance R17 is connected with one end of the 32 filter capacitor C18, one end of the 13 divider resistance R18, the other end of the 13 divider resistance R18 is connected with one end of the 33 filter capacitor C19, one end of the 14 divider resistance R19, and the other end of the 14 divider resistance R19 is connected with the pin one of comparer U17A;
Described voltage comparator circuit comprises two XOR gate, two resistance and two electric capacity; The pin one ground connection of XOR gate U18A, the pin two of XOR gate U18A meets power supply VCC; One end of 15 divider resistance R21 is connected with one end of the 34 filter capacitor C20, the pin one 6 of CPU; The other end ground connection of the 34 filter capacitor C20, the other end of the 15 divider resistance R21 is connected with the pin 3 of XOR gate U18A; The pin 9 of XOR gate U18C, pin one 0 are connected and ground connection; One end of 16 divider resistance R27 is connected with one end of the 35 filter capacitor C24, the pin one 7 of CPU; The other end ground connection of the 35 filter capacitor C24, the other end of the 16 divider resistance R27 is connected with the pin 8 of XOR gate U18C.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201520165638.0U CN204630636U (en) | 2015-03-23 | 2015-03-23 | The circuit of drainage pipeline networks liquid level detection device |
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| CN201520165638.0U CN204630636U (en) | 2015-03-23 | 2015-03-23 | The circuit of drainage pipeline networks liquid level detection device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104713615A (en) * | 2015-03-23 | 2015-06-17 | 杭州电子科技大学 | Circuit of drainage pipe network liquid level measurement device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104713615A (en) * | 2015-03-23 | 2015-06-17 | 杭州电子科技大学 | Circuit of drainage pipe network liquid level measurement device |
| CN104713615B (en) * | 2015-03-23 | 2017-12-26 | 杭州电子科技大学 | A kind of circuit of drainage pipeline networks liquid level detection device |
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