CN201724989U - Circuit for adjustment of phase sequence and voltage of three-phase alternating current - Google Patents
Circuit for adjustment of phase sequence and voltage of three-phase alternating current Download PDFInfo
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- CN201724989U CN201724989U CN2010202165114U CN201020216511U CN201724989U CN 201724989 U CN201724989 U CN 201724989U CN 2010202165114 U CN2010202165114 U CN 2010202165114U CN 201020216511 U CN201020216511 U CN 201020216511U CN 201724989 U CN201724989 U CN 201724989U
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Abstract
The utility model provides a circuit for adjustment of phase sequence and voltage of three-phase alternating current, comprising power circuit, zero cross detection circuit, data processing circuit, wherein the power circuit is respectively connected with the zero cross detection circuit, the data processing circuit and the zero cross detection circuit is connected with the data processing circuit. The power circuit provides working voltage for the zero cross detection circuit and the data processing circuit. The zero cross detection circuit takes sample for sine wave signal of two groups of line voltages U A B and U A C in power grid to convert into the square signal, and inputs the square signal into data processing circuit. A judgement that the voltage with the phase sequence of positive sequence, inverted sequence or three phase is not balanced can be made after comparing zero cross time of two line voltage signals U A B and U A C by the data processing circuit, and a corresponding driving signal is output to a phase sequence converting executive mechanism or a warning device.
Description
Technical field:
The utility model relates to the testing circuit technical field, refers in particular to a kind of circuit of adjusting phase order of 3-phase AC and voltage.
Background technology:
At present, many equipment phase sequence to three-phase alternating current when the work operation has certain requirement, promptly only allows folk prescription to running, may cause damage as reverse running.And the phase sequence of three-phase alternating current is normally unknown, even equipment press the normal phase sort run, is keeping in repair or during power line construction, the situation of phase sequence commutation might occur, thereby cause the damage of equipment.Therefore, be badly in need of a kind of circuit that can detect and revise, thereby avoid the harm that brings because of phase sequence dislocation the phase sequence of three-phase alternating current.
Summary of the invention:
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of circuit of adjusting phase order of 3-phase AC and voltage is provided.
For achieving the above object, technical scheme provided by the utility model is: a kind of circuit of adjusting phase order of 3-phase AC and voltage, it includes power circuit, zero cross detection circuit, data processing circuit, wherein, power circuit respectively with zero cross detection circuit, data processing circuit is connected, zero cross detection circuit is connected with data processing circuit, described zero cross detection circuit includes first resistance, second resistance, the 3rd resistance, the 4th resistance, the 5th resistance, the 6th resistance, the 7th resistance, the 8th resistance, the 9th resistance, the tenth resistance, the 11 resistance, the 12 resistance, first transformer, second transformer, first diode, second diode, the 3rd diode, the 4th diode, first electric capacity, second electric capacity, wherein, one termination power A phase of first resistance, one end of another termination first primary, another termination second resistance of first transformer, another termination power of second resistance B phase, the first transformer secondary output two ends connect the 3rd resistance respectively, one end of the 4th resistance, the 3rd resistance, the 4th resistance other end connects the input end of first voltage comparator respectively, first diode, be connected across the input end of first voltage comparator after the second diode reverse parallel connection again, the first voltage comparator output terminal and the 9th resistance, the tenth resistance one end is connected with data processing circuit after linking to each other, another termination power circuit of the 9th resistance, the other end ground connection of the tenth resistance, first electric capacity and the tenth resistance are connected in parallel on the first voltage comparator output terminal, one termination power A phase of the 5th resistance, one end of another termination second primary, another termination the 6th resistance of second transformer, another termination power of the 6th resistance C phase, the second transformer secondary output two ends connect the 7th resistance respectively, the 8th resistance one end, the 7th resistance, the 8th resistance other end connects the input end of second voltage comparator respectively, the 3rd diode, be connected across the input end of second voltage comparator after the 4th diode reverse parallel connection again, second voltage comparator output terminal and the 11 resistance, one end of the 12 resistance is connected with data processing circuit after linking to each other again, another termination power circuit of the 11 resistance, the other end ground connection of the 12 resistance, second electric capacity and the 12 resistance are connected in parallel on the second voltage comparator output terminal.
Described power circuit includes voltage dependent resistor (VDR), the 3rd transformer, bridge rectifier filtering, three terminal regulator, wherein, the voltage dependent resistor (VDR) two ends respectively with an end that is connected to the 3rd primary after power supply is connected again, the 3rd transformer secondary output two ends are connected with the input end of bridge rectifier filtering, the output terminal of bridge rectifier filtering is connected with the input end of three terminal regulator, the 3rd electric capacity, the 5th electric capacity is connected in parallel on the input end of three terminal regulator, the output terminal of three terminal regulator with in parallel after the 4th electric capacity, after the 6th electric capacity connects respectively with zero cross detection circuit, data processing circuit is connected.
Described data processing circuit includes chip, the 8th electric capacity, triode, the 14 resistance, the 15 resistance, the 16 resistance, the 17 resistance, wherein, the crus secunda of chip, tripod respectively with first voltage comparator, the output terminal of second voltage comparator is connected, the 20 pin of chip respectively with the 6th electric capacity, the 14 resistance one end is connected, the 14 resistance other end is connected with the 15 resistance one end, the 15 resistance other end and the 16 resistance, the 7th electric capacity, crystal oscillator, after being connected, polar capacitor one end is connected to an end of the 8th electric capacity again, the other end of the 8th electric capacity is connected on the 20 pin of chip, the wherein bipod of triode is connected the 14 resistance two ends, tripod and the 16 resistance, the 17 resistance one end is connected, the 17 resistance other end be connected to again on the 16 pin of chip after the 7th electric capacity one end is connected, crystal oscillator wherein bipod respectively with the 17 pin of chip, the tenth octal is connected, and the polar capacitor other end is connected with the 19 pin of chip.
The utility model after having adopted such scheme, power circuit with civil power 220V step-down rectifier after output 5V direct current zero cross detection circuit and data processing circuit operating voltage is provided.Wherein, the voltage dependent resistor (VDR) in the power circuit can prevent thunderbolt and power network overvoltage intrusion.The 220V alternating current obtains the 10.5V alternating voltage after the 3rd transformer step-down, then output 12V DC voltage after bridge rectifier filtering.12V voltage is output 5V DC voltage behind three terminal regulator voltage stabilizing and the 3rd electric capacity, the 5th capacitor filtering, and this voltage is as the operating voltage of zero cross detection circuit and data processing circuit; Zero cross detection circuit is with electrical network 380V line voltage U
ABAfter first resistance, the second resistance step-down current limliting, obtain the 10V alternating voltage, output 10V alternating voltage after first transformer isolation, first transformer is 1: 1 isolating transformer, this voltage is delivered to the input end of chip.Wherein the 3rd resistance, the 4th resistance play the step-down metering function, and first diode, second diode play the limited amplitude protection effect, and the input signal amplitude limit at 0.7V, is prevented that the overvoltage of chip input port from damaging.Chip uses as voltage comparator, and when the positive half cycle of signal at sine wave, inverting input voltage is higher than in-phase input end voltage, this moment the voltage comparator output low level; When the negative half period of signal at sine wave, inverting input voltage is lower than in-phase input end voltage, voltage comparator output this moment high level, after being the each zero passage of alternating current, the upset of voltage comparator output signal once, export one and the synchronous square-wave signal of sinusoidal wave zero crossing, this square-wave signal is directly sent into single-chip microcomputer and is carried out data processing; Meanwhile, line voltage U
ACThe zero passage detection signal also send into data processing circuit.Data processing circuit is with two line voltage signal U
AB, U
ACThe zero crossing time just can make the judgement that phase sequence is positive sequence, inverted sequence or imbalance of three-phase voltage after comparing, and output corresponding driving signal is given phase sequence conversion topworks or warning device.
Description of drawings:
Fig. 1 is the utility model one-piece construction frame principle figure.
Fig. 2 is the utility model circuit theory diagrams.
Phase waveform structural representation when Fig. 3 is the utility model positive phase sequence.
Phase waveform structural representation when Fig. 4 is the utility model negative-phase sequence.
Fig. 5 is the phase waveform structural representation of the utility model three-phase voltage when asymmetric.
Embodiment:
The utility model is described in further detail below in conjunction with accompanying drawing 1 and accompanying drawing 5, preferred embodiment of the present utility model is: the described circuit of present embodiment includes power circuit 1, zero cross detection circuit 2, data processing circuit 3, wherein, power circuit 1 is connected with zero cross detection circuit 2, data processing circuit 3 respectively, zero cross detection circuit 2 is connected with data processing circuit 3, power circuit 1 with 220V civil power step-down rectifier after output 5V DC voltage provide operating voltage for zero cross detection circuit 2, data processing circuit 3, zero cross detection circuit 2 is by gathering the line voltage U
ABWith the line voltage U
ACPhase waveform, and after the conversion process with in the data input data processing circuit 3, the data after data processing circuit 3 will receive are analyzed, and two cycle signal zero-cross point relatively, if the line voltage U
ABLeading line voltage U
AC60 °, show that phase sequence is a positive phase sequence, if the line voltage U
ACLeading line voltage U
AB60 ° then is negative-phase sequence, when the line voltage U
ABAnd U
ACBetween angle during less than 60 °, imbalance of three-phase voltage then.
Described power circuit 1 includes voltage dependent resistor (VDR) ZNR, the 3rd transformer T3, bridge rectifier filtering D0, three terminal regulator VR1, wherein, voltage dependent resistor (VDR) ZNR two ends are connected to the elementary end of the 3rd transformer T3 respectively with after power supply is connected again, T3 level of the 3rd transformer two ends are connected with the input end of bridge rectifier filtering D0, the output terminal of bridge rectifier filtering D0 is connected with the input end of three terminal regulator VR1, the 3rd capacitor C 3, the 5th capacitor C 5 is connected in parallel on the input end of three terminal regulator VR1, the output terminal of three terminal regulator VR1 with in parallel after the 4th capacitor C 4, after the 6th capacitor C 6 connects respectively with zero cross detection circuit 2, data processing circuit 3 is connected.
Described zero cross detection circuit 2 includes first resistance R 1, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 12 resistance R 12, the first transformer T1, the second transformer T2, the first diode D1, the second diode D2, the 3rd diode D3, the 4th diode D4, voltage comparator U1, first capacitor C 1, second capacitor C 2, wherein, one termination power A phase of first resistance R 1, the elementary end of another termination first transformer T1, another termination second resistance R 2 of the first transformer T1, second resistance R, 2 another termination power B phases, T1 level of first transformer two ends connect the 3rd resistance R 3 respectively, one end of the 4th resistance R 4, the 3rd resistance R 3, the 4th resistance R 4 other ends connect the input end of the first voltage comparator U1C respectively, the first diode D1, be connected across the input end of the first voltage comparator U1C behind the second diode D2 reverse parallel connection again, the first voltage comparator U1C output terminal and the 9th resistance R 9, the tenth resistance R 10 1 ends are connected with data processing circuit 3 after linking to each other, another termination power circuit 1 of the 9th resistance R 9, the other end ground connection of the tenth resistance R 10, first capacitor C 1 and the tenth resistance R 10 are connected in parallel on the first voltage comparator U1C output terminal, one termination power A phase of the 5th resistance R 5, the elementary end of another termination second transformer T2, another termination the 6th resistance R 6 of the second transformer T2, the 6th resistance R 6 another termination power C phases, T2 level of second transformer two ends connect the 7th resistance R 7 respectively, the 8th resistance R 8 one ends, the 7th resistance R 7, the 8th resistance R 8 other ends connect the input end of the second voltage comparator U1D respectively, the 3rd diode D3, be connected across the input end of the second voltage comparator U1D behind the 4th diode D4 reverse parallel connection again, the second voltage comparator U1D output terminal and the 11 resistance R 11, one end of the 12 resistance R 12 is connected with data processing circuit 3 after linking to each other again, another termination power circuit 1 of the 11 resistance R 11, the other end ground connection of the 12 resistance R 12, second capacitor C 2 and the 12 resistance R 12 are connected in parallel on the second voltage comparator U1D output terminal.
Described data processing circuit 3 includes chip IC 1, the 8th capacitor C 8, triode Q1, the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17, wherein, the crus secunda 2 of chip IC 1, tripod 3 respectively with the first voltage comparator U1C, the output terminal of the second voltage comparator U1D is connected, the 20 pin 20 of chip IC 1 respectively with the 6th capacitor C 6, the 14 resistance R 14 1 ends are connected, the 14 resistance R 14 other ends are connected with the 15 resistance R 15 1 ends, the 15 resistance R 15 other ends and the 16 resistance R 16, the 7th capacitor C 7, crystal oscillator XL1, after being connected, polar capacitor E1 one end is connected to an end of the 8th capacitor C 8 again, the other end of the 8th capacitor C 8 is connected on the 20 pin 20 of chip IC 1, the wherein bipod of triode Q1 is connected the 14 resistance R 14 two ends, tripod and the 16 resistance R 16, the 17 resistance R 17 1 ends are connected, the 17 resistance R 17 other ends be connected to again on the 16 pin 16 of chip IC 1 after the 7th capacitor C 7 one ends are connected, crystal oscillator XL1 wherein bipod respectively with the 17 pin 17 of chip IC 1, the tenth octal 18 is connected, and the polar capacitor E1 other end is connected with the 19 pin 19 of chip IC 1.The utility model after having adopted such scheme, power circuit with civil power 220V step-down rectifier after output 5V direct current zero cross detection circuit and data processing circuit operating voltage is provided.Wherein, the voltage dependent resistor (VDR) ZNR in the power circuit 1 can prevent thunderbolt and power network overvoltage intrusion.The 220V alternating current obtains the 10.5V alternating voltage after the 3rd transformer T3 step-down, then output 12V DC voltage behind bridge rectifier filtering D0.12V voltage is output 5V DC voltage after three terminal regulator VR1 voltage stabilizing and the 3rd capacitor C 3,5 filtering of the 5th capacitor C, and this voltage is as the operating voltage of zero cross detection circuit 2 and data processing circuit 3; Zero cross detection circuit 2 is with electrical network 380V line voltage U
ABAfter first resistance R 1, second resistance R, 2 step-down current limlitings, obtain the 10V alternating voltage, output 10V alternating voltage after the first transformer T1 isolates, the first transformer T1 is 1: 1 isolating transformer, this voltage is delivered to the input end of chip IC 1.Wherein the 3rd resistance R 3,4 step-down metering functions of the 4th resistance R, the first diode D1, the second diode D2 play the limited amplitude protection effect, and the input signal amplitude limit at 0.7V, is prevented that chip IC 1 input port overvoltage from damaging.Chip IC 1 is used as voltage comparator, and when the positive half cycle of signal at sine wave, inverting input voltage is higher than in-phase input end voltage, this moment the voltage comparator output low level; When the negative half period of signal at sine wave, inverting input voltage is lower than in-phase input end voltage, voltage comparator output this moment high level, after being the each zero passage of alternating current, the upset of voltage comparator output signal once, export one and the synchronous square-wave signal of sinusoidal wave zero crossing, this square-wave signal is directly sent into single-chip microcomputer and is carried out data processing; Meanwhile, line voltage U
ACThe zero passage detection signal also send into data processing circuit.Data processing circuit is with two line voltage signal U
AB, U
ACThe zero crossing time just can make the judgement that phase sequence is positive sequence, inverted sequence or imbalance of three-phase voltage after comparing, and output corresponding driving signal is given phase sequence conversion topworks or warning device.
The embodiment of the above is the preferred embodiment of the utility model only, is not to limit practical range of the present utility model with this, so the variation that all shapes according to the utility model, principle are done all should be encompassed in the protection domain of the present utility model.
Claims (3)
1. circuit of adjusting phase order of 3-phase AC and voltage, it is characterized in that: it includes power circuit (1), zero cross detection circuit (2), data processing circuit (3), wherein, power circuit (1) respectively with zero cross detection circuit (2), data processing circuit (3) is connected, zero cross detection circuit (2) is connected with data processing circuit (3), described zero cross detection circuit (2) includes first resistance (R1), second resistance (R2), the 3rd resistance (R3), the 4th resistance (R4), the 5th resistance (R5), the 6th resistance (R6), the 7th resistance (R7), the 8th resistance (R8), the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 12 resistance (R12), first transformer (T1), second transformer (T2), first diode (D1), second diode (D2), the 3rd diode (D3), the 4th diode (D4), first electric capacity (C1), second electric capacity (C2), wherein, one termination power A phase of first resistance (R1), the end that another termination first transformer (T1) is elementary, another termination second resistance (R2) of first transformer (T1), another termination power of second resistance (R2) B phase, the secondary two ends of first transformer (T1) connect the 3rd resistance (R3) respectively, one end of the 4th resistance (R4), the 3rd resistance (R3), the 4th resistance (R4) other end connects the input end of first voltage comparator (U1C) respectively, first diode (D1), be connected across the input end of first voltage comparator (U1C) behind second diode (D2) reverse parallel connection again, first voltage comparator (U1C) output terminal and the 9th resistance (R9), the tenth resistance (R10) end is connected with data processing circuit (3) after linking to each other, another termination power circuit (1) of the 9th resistance (R9), the other end ground connection of the tenth resistance (R10), first electric capacity (C1) is connected in parallel on first voltage comparator (U1C) output terminal with the tenth resistance (R10), one termination power A phase of the 5th resistance (R5), the end that another termination second transformer (T2) is elementary, another termination the 6th resistance (R6) of second transformer (T2), another termination power of the 6th resistance (R6) C phase, the secondary two ends of second transformer (T2) connect the 7th resistance (R7) respectively, the 8th resistance (R8) end, the 7th resistance (R7), the 8th resistance (R8) other end connects the input end of second voltage comparator (U1D) respectively, the 3rd diode (D3), be connected across the input end of second voltage comparator (U1D) behind the 4th diode (D4) reverse parallel connection again, second voltage comparator (U1D) output terminal and the 11 resistance (R11), one end of the 12 resistance (R12) is connected with data processing circuit (3) after linking to each other again, another termination power circuit (1) of the 11 resistance (R11), the other end ground connection of the 12 resistance (R12), second electric capacity (C2) and the 12 resistance (R12) are connected in parallel on second voltage comparator (U1D) output terminal.
2. a kind of circuit of adjusting phase order of 3-phase AC and voltage according to claim 2, it is characterized in that: described power circuit (1) includes voltage dependent resistor (VDR) (ZNR), the 3rd transformer (T3), bridge rectifier filtering (D0), three terminal regulator (VR1), wherein, voltage dependent resistor (VDR) (ZNR) two ends are connected to the elementary end of the 3rd transformer (T3) respectively with after power supply is connected again, the secondary two ends of the 3rd transformer (T3) are connected with the input end of bridge rectifier filtering (D0), the output terminal of bridge rectifier filtering (D0) is connected with the input end of three terminal regulator (VR1), the 3rd electric capacity (C3), the 5th electric capacity (C5) is connected in parallel on the input end of three terminal regulator (VR1), the output terminal of three terminal regulator (VR1) with in parallel after the 4th electric capacity (C4), after the 6th electric capacity (C6) connects respectively with zero cross detection circuit (2), data processing circuit (3) is connected.
3. a kind of circuit of adjusting phase order of 3-phase AC and voltage according to claim 2, it is characterized in that: described data processing circuit (3) includes chip (IC1), the 8th electric capacity (C8), triode (Q1), the 14 resistance (R14), the 15 resistance (R15), the 16 resistance (R16), the 17 resistance (R17), wherein, the crus secunda (2) of chip (IC1), tripod (3) respectively with first voltage comparator (U1C), the output terminal of second voltage comparator (U1D) is connected, the 20 pin (20) of chip (IC1) respectively with the 6th electric capacity (C6), the 14 resistance (R14) end is connected, the 14 resistance (R14) other end is connected with the 15 resistance (R15) end, the 15 resistance (R15) other end and the 16 resistance (R16), the 7th electric capacity (C7), crystal oscillator (XL1), after being connected, polar capacitor (E1) end is connected to an end of the 8th electric capacity (C8) again, the other end of the 8th electric capacity (C8) is connected on the 20 pin (20) of chip (IC1), the wherein bipod of triode (Q1) is connected the 14 resistance (R14) two ends, tripod and the 16 resistance (R16), the 17 resistance (R17) end is connected, the 17 resistance (R17) other end be connected to again on the 16 pin (16) of chip (IC1) after the 7th electric capacity (C7) end is connected, crystal oscillator (XL1) wherein bipod respectively with the 17 pin (17) of chip (IC1), the tenth octal (18) is connected, and polar capacitor (E1) other end is connected with the 19 pin (19) of chip (IC1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202165114U CN201724989U (en) | 2010-06-01 | 2010-06-01 | Circuit for adjustment of phase sequence and voltage of three-phase alternating current |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010202165114U CN201724989U (en) | 2010-06-01 | 2010-06-01 | Circuit for adjustment of phase sequence and voltage of three-phase alternating current |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201724989U true CN201724989U (en) | 2011-01-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010202165114U Expired - Lifetime CN201724989U (en) | 2010-06-01 | 2010-06-01 | Circuit for adjustment of phase sequence and voltage of three-phase alternating current |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201724989U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101871982A (en) * | 2010-06-01 | 2010-10-27 | 佛山市中格威电子有限公司 | Method and circuit for detecting phase sequence and asymmetrical voltage of three phase current |
| CN107402331A (en) * | 2017-09-08 | 2017-11-28 | 国家电网公司 | Low pressure is wireless phase checking device and its method |
-
2010
- 2010-06-01 CN CN2010202165114U patent/CN201724989U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101871982A (en) * | 2010-06-01 | 2010-10-27 | 佛山市中格威电子有限公司 | Method and circuit for detecting phase sequence and asymmetrical voltage of three phase current |
| CN107402331A (en) * | 2017-09-08 | 2017-11-28 | 国家电网公司 | Low pressure is wireless phase checking device and its method |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20110126 Effective date of abandoning: 20120704 |