CN204615761U - A kind of binary channels I/Q modulator and DAC interface arrangement - Google Patents
A kind of binary channels I/Q modulator and DAC interface arrangement Download PDFInfo
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- CN204615761U CN204615761U CN201520264617.4U CN201520264617U CN204615761U CN 204615761 U CN204615761 U CN 204615761U CN 201520264617 U CN201520264617 U CN 201520264617U CN 204615761 U CN204615761 U CN 204615761U
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- modulator
- dac
- out2
- out1
- binary channels
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- Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
Abstract
The utility model discloses a kind of binary channels I/Q modulator and DAC interface arrangement, comprise high-speed DAC module, I/Q modulator module, earth resistance, biasing resistor, described high-speed DAC module pin comprises: OUT1_P, OUT1_N, OUT2_P, OUT2_N, and described I/Q modulator module pin comprises: IBBP, IBBN, QBBP, QBBN.A kind of binary channels I/Q modulator that the utility model provides and DAC interface arrangement, adopt the identical bias level of ADL5372 and AD9779 and similar high s/n ratio, realize matched well; Earth resistance is adopted to adjust the DAC amplitude of oscillation; Biasing resistor is adopted to carry out the control voltage amplitude of oscillation; Adopt shunt capacitance to the decoupling of large area ground plane.Being applicable to zero intermediate frequency application, inputting as provided LVDS interface, high-resolution composite intermediate frequency.
Description
Technical field
The utility model relates to a kind of binary channels I/Q modulator and DAC interface arrangement, belongs to circuit engineering field.
Background technology
At present, I/Q modulator is docked with DAC, often because bias level is different, signal to noise ratio is different, and cannot realize matched well.How to utilize minimum element to realize docking of binary channels I/Q modulator and DAC, and reduce voltage swing, and not affect resolution be the problem that will solve.
Utility model content
Object: in order to overcome the deficiencies in the prior art, the utility model provides a kind of binary channels I/Q modulator and DAC interface arrangement.
Technical scheme: for solving the problems of the technologies described above, the technical solution adopted in the utility model is:
A kind of binary channels I/Q modulator and DAC interface arrangement, comprise high-speed DAC module, I/Q modulator module, earth resistance, biasing resistor, described high-speed DAC module pin comprises: OUT1_P, OUT1_N, OUT2_P, OUT2_N, described I/Q modulator module pin comprises: IBBP, IBBN, QBBP, QBBN, described OUT1_P and IBBP is connected, OUT1_N and IBBN is connected, and OUT2_P and QBBP is connected, and OUT2_N and QBBN is connected; Between described OUT1_P and IBBP, between OUT1_N and IBBN, between OUT2_P and QBBP, between OUT2_N and QBBN, be all parallel with earth resistance; Be in series with biasing resistor between described IBBP and IBBN, between described QBBP and QBBN, be in series with biasing resistor.
Also comprise electric capacity, between described IBBP and IBBN, be in series with electric capacity, between described QBBP and QBBN, be in series with electric capacity.
Preferably, described earth resistance is set to 50 Europe.
Preferably, described biasing resistor is set to 100 Europe.
Preferably, described high-speed DAC module adopts AD9779.
Preferably, described I/Q modulator module adopts ADL5375.
Beneficial effect: a kind of binary channels I/Q modulator that the utility model provides and DAC interface arrangement, adopts the identical bias level of ADL5372 and AD9779 and similar high s/n ratio, realizes matched well; Earth resistance is adopted to adjust the DAC amplitude of oscillation; Biasing resistor is adopted to carry out the control voltage amplitude of oscillation; Adopt shunt capacitance to the decoupling of large area ground plane.Being applicable to zero intermediate frequency application, inputting as provided LVDS interface, high-resolution composite intermediate frequency.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
As shown in Figure 1, a kind of binary channels I/Q modulator and DAC interface arrangement, comprise high-speed DAC module 1, I/Q modulator module 2, earth resistance 3, biasing resistor 4, described high-speed DAC module 1 pin comprises: OUT1_P, OUT1_N, OUT2_P, OUT2_N, described I/Q modulator mould 2 pieces of pins comprise: IBBP, IBBN, QBBP, QBBN, and described OUT1_P and IBBP is connected, and OUT1_N and IBBN is connected, OUT2_P and QBBP is connected, and OUT2_N and QBBN is connected; Earth resistance 3 is all parallel with between described OUT1_P and IBBP, between OUT1_N and IBBN, between OUT2_P and QBBP, between OUT2_N and QBBN; Be in series with biasing resistor 4 between described IBBP and IBBN, between described QBBP and QBBN, be in series with biasing resistor 4.
Also comprise electric capacity 5, between described IBBP and IBBN, be in series with electric capacity 5, between described QBBP and QBBN, be in series with electric capacity 5.
Preferably, described earth resistance 3 is set to 50 Europe.
Preferably, described biasing resistor 4 is set to 100 Europe.
Preferably, described high-speed DAC module 1 adopts AD9779.
Preferably, described I/Q modulator module 2 adopts ADL5375.
The above is only preferred implementation of the present utility model; be noted that for those skilled in the art; under the prerequisite not departing from the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (6)
1. a binary channels I/Q modulator and DAC interface arrangement, comprise high-speed DAC module, I/Q modulator module, it is characterized in that: also comprise earth resistance, biasing resistor, described high-speed DAC module pin comprises: OUT1_P, OUT1_N, OUT2_P, OUT2_N, described I/Q modulator module pin comprises: IBBP, IBBN, QBBP, QBBN, and described OUT1_P and IBBP is connected, and OUT1_N and IBBN is connected, OUT2_P and QBBP is connected, and OUT2_N and QBBN is connected; Between described OUT1_P and IBBP, between OUT1_N and IBBN, between OUT2_P and QBBP, between OUT2_N and QBBN, be all parallel with earth resistance; Be in series with biasing resistor between described IBBP and IBBN, between described QBBP and QBBN, be in series with biasing resistor.
2. a kind of binary channels I/Q modulator according to claim 1 and DAC interface arrangement, is characterized in that: also comprise electric capacity, be in series with electric capacity between described IBBP and IBBN, be in series with electric capacity between described QBBP and QBBN.
3. a kind of binary channels I/Q modulator according to claim 1 and DAC interface arrangement, is characterized in that: described earth resistance is set to 50 Europe.
4. a kind of binary channels I/Q modulator according to claim 1 and DAC interface arrangement, is characterized in that: described biasing resistor is set to 100 Europe.
5. a kind of binary channels I/Q modulator according to claim 1 and DAC interface arrangement, is characterized in that: described high-speed DAC module adopts AD9779.
6. a kind of binary channels I/Q modulator according to claim 1 and DAC interface arrangement, is characterized in that: described I/Q modulator module adopts ADL5375.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520264617.4U CN204615761U (en) | 2015-04-29 | 2015-04-29 | A kind of binary channels I/Q modulator and DAC interface arrangement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520264617.4U CN204615761U (en) | 2015-04-29 | 2015-04-29 | A kind of binary channels I/Q modulator and DAC interface arrangement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204615761U true CN204615761U (en) | 2015-09-02 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520264617.4U Expired - Fee Related CN204615761U (en) | 2015-04-29 | 2015-04-29 | A kind of binary channels I/Q modulator and DAC interface arrangement |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204615761U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811141A (en) * | 2015-04-29 | 2015-07-29 | 苏州华徕光电仪器有限公司 | Dual-channel IQ modulator and DAC interface device |
-
2015
- 2015-04-29 CN CN201520264617.4U patent/CN204615761U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811141A (en) * | 2015-04-29 | 2015-07-29 | 苏州华徕光电仪器有限公司 | Dual-channel IQ modulator and DAC interface device |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150902 Termination date: 20160429 |