CN204578517U - A kind of pulse selectable adjustable signal generator based on FPGA - Google Patents
A kind of pulse selectable adjustable signal generator based on FPGA Download PDFInfo
- Publication number
- CN204578517U CN204578517U CN201520261458.2U CN201520261458U CN204578517U CN 204578517 U CN204578517 U CN 204578517U CN 201520261458 U CN201520261458 U CN 201520261458U CN 204578517 U CN204578517 U CN 204578517U
- Authority
- CN
- China
- Prior art keywords
- circuit
- pulse
- signal
- frequency
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
The utility model discloses a kind of pulse selectable adjustable signal generator based on FPGA, circuit unit involved by it comprises crystal oscillating circuit, PLL frequency multiplier circuit, frequency dividing circuit, FM circuit I, FM circuit II, single pulse width modulation circuit, two pulse width modulation circuit, MUX and pulse signal modulate circuit, PLL frequency multiplier circuit receives the reference clock signal from crystal oscillating circuit, the output of PLL frequency multiplier circuit is connected with frequency dividing circuit input, the output of frequency dividing circuit is connected to FM circuit I and FM circuit II simultaneously, single pulse width modulation circuit receives the output signal of FM circuit I, two pulse width modulation circuit receives the output signal of FM circuit II, single pulse width modulation circuit is all connected with MUX input with the output of two pulse width modulation circuit, the output of MUX is connected with pulse signal modulate circuit input.The utility model can produce frequency and all adjustable pulse of pulsewidth and dipulse signal simultaneously.
Description
Technical field
The utility model relates to a kind of pulse selectable adjustable signal generator based on FPGA.
Background technology
In order to improve the spatial resolution of distributed optical fiber sensing system, pulse excitation light signal as distributed optical fiber sensing system often adopts electrooptic modulator to modulate rear acquisition to the narrow linewidth continuous laser that centre wavelength is 1550nm, but, in order to obtain the pulsed optical signals that can meet instructions for use, the acquisition problem of the pulse drive signal of electrooptic modulator first must be solved.When adopting the enough fast A/D converter of conversion speed and the suitable receiving filter of bandwidth, the spatial resolution of distributed optical fiber sensing system then depends on the pulse duration of pulsed optical signals, and the pulsewidth of pulsed optical signals depends on the pulse duration of the pulse-modulated signal be loaded on modulator, and for the distributed optical fiber sensing system of different distance sensing, pulse duration and the output frequency of the driving pulse light signal required by it are also different, therefore, this just requires that the pulse duration of modulation signal and output frequency can carry out controllable type adjustment according to the actual distance sensing of sensor-based system.
In distributed optical fiber sensing system, if the pulsewidth of pulse modulation signal is wide, then the spatial resolution of distributed optical fiber sensing system can be caused to reduce; If but when the pulsewidth of pulse modulation signal is too low, then after electrooptic modulator modulation, the pulse light signal that obtains will be subject to the impact of phonon lifetime and obviously reduce the distance sensing of sensor-based system.Therefore, the utility model discloses a kind of pulse selectable adjustable signal generator based on FPGA, the utility model be on FPGA development board, produce pulse duration and output frequency simultaneously can the pulse modulation signal that regulates of keying formula and double pulse modulation signal, suitable pulse-modulated signal is selected to modulate to obtain corresponding pulsed optical signals to drive electrooptic modulator to the narrow linewidth continuous laser that centre wavelength is 1550nm more according to actual needs, can under ensureing that sensor-based system has the prerequisite of distance sensing enough far away as the pumping signal of distributed optical fiber sensing system using this pulsed optical signals, also improve the spatial resolution of sensor-based system simultaneously.
Utility model content
The purpose of this utility model is the generation link the deficiencies in the prior art overcoming the modulation signal in distributed optical fiber sensing system, a kind of pulse selectable adjustable signal generator based on FPGA is provided, adopt the utility model can produce pulse modulation signal and double pulse modulation signal simultaneously, and the pulse duration of these two kinds of pulse-modulated signals and output frequency all have can keying regulate advantage.
The purpose of this utility model is achieved through the following technical solutions: the circuit unit involved by a kind of pulse selectable adjustable signal generator based on FPGA comprises crystal oscillator element circuit, PLL frequency multiplier circuit, frequency dividing circuit, FM circuit I, FM circuit II, single pulse width modulation circuit, two pulse width modulation circuit, MUX and pulse signal modulate circuit, PLL frequency multiplier circuit receives the reference clock signal from crystal oscillating circuit and this reference clock signal is done process of frequency multiplication, the output of PLL frequency multiplier circuit is connected with the input of frequency dividing circuit, the output of frequency dividing circuit is connected with FM circuit I and FM circuit II simultaneously, single pulse width modulation circuit receives the output signal of FM circuit I, two pulse width modulation circuit receives the output signal of FM circuit II, single pulse width modulation circuit is all connected with the input of MUX with the output of two pulse width modulation circuit, the output of MUX is connected with the input of pulse signal modulate circuit.
The basic frequency of the clock signal of described crystal oscillator element circuit is 50MHz, and the clock cycle is 20ns, and the clock signal of crystal oscillator element circuit is as the input signal of PLL frequency multiplier circuit.
Described PLL frequency multiplier circuit by after adopting Verilog HDL language compilation program to design the PLL frequency multiplier circuit module of FPGA on FPGA hardware platform under QUARTUS II software development environment, the softer core of the IP calling PLL by name realizes.
Described frequency dividing circuit is realized by the modularized circuit adopting the programming of Verilog HDL language compilation to have division function under QUARTUS II software development environment on FPGA hardware platform, and this frequency dividing circuit receives the frequency multiplied clock signal exported from PLL frequency multiplier circuit.
Described frequency adjustment circuit I, frequency adjustment circuit II, single pulse width modulation circuit and two pulse width modulation circuit all on FPGA hardware platform by adopting Verilog HDL language compilation program to FPGA development board realizes the pulse duration of pulse-modulated signal and the adjustment of corresponding output frequency in keying mode after wherein 4 buttons carry out shaking the keyboard-coding of filtering and corresponding function under QUARTUS II software development environment, frequency adjustment circuit I and frequency adjustment circuit II receive the sub-frequency clock signal carrying out self frequency-dividing circuit simultaneously, the input of the output order pulse width modulation circuit of frequency adjustment circuit I, the output signal of two pulse width modulation circuit receive frequency regulating circuit II.
The input of described MUX is connected with the input of single pulse width modulation circuit and two pulse width modulation circuit simultaneously, realizes selecting a kind of pulse-modulated signal wherein to export at one time according to actual needs.
Described pulse signal modulate circuit is RC filter circuit, receives the output signal from MUX, realizes the pulse modulation signal that receives or the negative overshoot of double pulse modulation signal and the function of the noise filtering that transfinites.
Compared with prior art, the utility model can produce pulse modulation signal and double pulse modulation signal simultaneously, in the application not only can according to actual sensor-based system specifically need select satisfactory pulse modulation signal or double pulse modulation signal easily and flexibly, also can carry out the adjustment of keying formula to the output frequency of pulse modulation signal and double pulse modulation signal and pulse duration simultaneously, and the minimum step amount of pulse width modulation can reach 5ns, thus improve spatial resolution and the certainty of measurement of system.
Accompanying drawing explanation
Fig. 1 is the utility model block diagram.
Fig. 2 is output frequency is 20KHz, and pulse duration is 25ns, pulse modulation signal (single_pulse_1) simulation result figure when duty ratio is 0.05%.
Fig. 3 is output frequency is 2KHz, and pulse duration is 100ns, pulse modulation signal (single_pulse_2) simulation result figure when duty ratio is 0.02%.
Fig. 4 is output frequency is 100Hz, and pulse duration is 5us, pulse modulation signal (single_pulse_3) simulation result figure when duty ratio is 0.05%.
Fig. 5 is the output frequency of double pulse modulation signal (double_pulse_1) is 6.5KHz, simulation result figure when single pulse width is 25ns.
Fig. 6 is the output frequency of double pulse modulation signal (double_pulse_2) is 4KHz, simulation result figure when single pulse width is 50ns.
Fig. 7 is the output frequency of double pulse modulation signal (double_pulse_3) is 100Hz, simulation result figure when single pulse width is 1.5us.
In FIG, 1, FPGA development board 2, crystal oscillating circuit 3, PLL frequency multiplier circuit 4, frequency dividing circuit 5, FM circuit I 6, FM circuit II 7, single pulse width modulation circuit 8, two pulse width modulation circuit 9, MUX 10, pulse signal modulate circuit.
In Fig. 2 ~ Fig. 7, clk is the reference clock signal of the 50MHz that crystal oscillating circuit exports, its clock cycle is 20ns, c1_200 is the frequency multiplied clock signal obtained after doing quadruple to 50MHz reference clock signal, rst is reset signal, single_pulse_1 is output frequency is 20KHz, pulse duration is 25ns, pulse modulation signal when duty ratio is 0.05%, single_pulse_2 is output frequency is 2KHz, pulse duration is 100ns, pulse modulation signal when duty ratio is 0.02%, single_pulse_3 is output frequency is 100Hz, pulse duration is 5us, pulse modulation signal when duty ratio is 0.05%, double_pulse_1 is output frequency is 6.5KHz, double pulse modulation signal when single pulse width is 25ns, double_pulse_2 is output frequency is 4KHz, double pulse modulation signal when single pulse width is 50ns, double_pulse_3 is output frequency is 100Hz, double pulse modulation signal when single pulse width is 1.5us.
Embodiment
As shown in Figure 1, the clock signal that crystal oscillator element circuit 2 on FPGA development board 1 exports 50MHz is done quadruple process through PLL frequency multiplier circuit 3 and obtains the frequency multiplied clock signal of 200MHz after making temporal constraint, using the input signal of this frequency multiplied clock signal as frequency dividing circuit 4, count after frequency division through frequency dividing circuit 4 and obtain multiple output frequency single pulse signal different with pulse duration, each single pulse signal exported frequency dividing circuit 4 respectively by FM circuit I and FM circuit II again carries out selection and exports, FM circuit I exports a road single pulse signal and it can be used as the input signal of single pulse width modulation circuit 7, the output pulse width identical and two-way single pulse signal that output frequency is also identical while that each pulse modulation signal that the FM circuit II pair of frequency dividing circuit 4 exports being selected rear, and using this two-way single pulse signal simultaneously as the input signal of two pulse width modulation circuit 8, double pulse modulation signal is exported after corresponding logical operation being carried out to this two-way single pulse signal by two pulse width modulation circuit 8, the output signal of single pulse width modulation circuit 7 and two pulse width modulation circuit 8 exports a kind of pulse-modulated signal wherein after MUX 9 is selected, the pulse-modulated signal that signal conditioning circuit 10 pairs of MUX 9 export carries out the filtering process of negative overshoot and the noise that transfinites.
Described PLL frequency multiplier circuit on FPGA hardware platform by after adopting Verilog HDL language compilation program to design the PLL frequency multiplier circuit module of FPGA under QUARTUS II software development environment, the soft core of IP calling PLL by name again realizes, in the soft core of PLL, Clock Multiplier Factor is set to 4, and temporal constraint process is done to the 200MHz frequency multiplied clock signal that PLL frequency multiplier circuit exports, the clock cycle limiting this frequency multiplied clock signal is 5ns.
The output frequency of pulse modulation signal and double pulse modulation signal and the adjustment of pulse duration all regulate in keying mode on FPGA hardware platform after adopting Verilog HDL language compilation program to carry out shaking the keyboard-coding of filtering and corresponding function to wherein 4 buttons on FPGA development board under QUARTUS II software development environment, and the pulse duration of two kinds of modulation signals is all stepping-in amount with 5ns to be regulated, when pulse-width regulated button be pressed one time time, the pulse duration of respective pulses modulation signal just will increase 5ns, until when pulsewidth is increased to maximum, if when pulse-width regulated button is pressed again, the pulsewidth of pulse signal is set to minimum pulse width value again.
T
p=5*M(formula 1)
In above formula, T
pfor the pulse duration of pulse-modulated signal, M is the number of times that pulse width control button is pressed, and 5 is the minimum step amount of pulse duration, and unit is ns.
Claims (8)
1. the pulse selectable adjustable signal generator based on FPGA, it is characterized in that: the circuit unit involved by it comprises crystal oscillator element circuit, PLL frequency multiplier circuit, frequency dividing circuit, FM circuit I, FM circuit II, single pulse width modulation circuit, two pulse width modulation circuit, MUX and pulse signal modulate circuit, PLL frequency multiplier circuit receives the reference clock signal from crystal oscillating circuit and this reference clock signal is done process of frequency multiplication, the output of PLL frequency multiplier circuit is connected with the input of frequency dividing circuit, the output of frequency dividing circuit is connected with FM circuit I and FM circuit II simultaneously, single pulse width modulation circuit receives the output signal of FM circuit I, two pulse width modulation circuit receives the output signal of FM circuit II, single pulse width modulation circuit is all connected with the input of MUX with the output of two pulse width modulation circuit, the output of MUX is connected with the input of pulse signal modulate circuit.
2. a kind of pulse selectable adjustable signal generator based on FPGA according to claim 1, is characterized in that: described pulse modulation signal and the generation of double pulse modulation signal realize all simultaneously on same FPGA development board.
3. a kind of pulse selectable adjustable signal generator based on FPGA according to claim 1, it is characterized in that: the frequency of the reference clock signal that described crystal oscillator element circuit exports is 50MHz, do 4 frequencys multiplication by PLL frequency multiplier circuit and after doing temporal constraint, export the frequency multiplied clock signal of 200MHz, allowing the clock cycle of frequency-doubled signal be 5ns.
4. a kind of pulse selectable adjustable signal generator based on FPGA according to claim 1, it is characterized in that: the duty ratio of described pulse modulation signal is no more than 0.05%, pulse duration is that 25ns to 5us is adjustable, output frequency is 100Hz to 20KHz, and output frequency regulates by keying selection mode.
5. a kind of pulse selectable adjustable signal generator based on FPGA according to claim 1, it is characterized in that: the single pulse width of described double pulse modulation signal is that 25ns to 1.5us is adjustable, the output frequency of double pulse modulation signal is 100Hz to 6.5KHz, and output frequency regulates by keying selection mode.
6. according to claim 1 or a kind of pulse selectable adjustable signal generator based on FPGA according to claim 4, it is characterized in that: the pulse duration of described pulse modulation signal is that stepping-in amount regulates by keying mode with 5ns.
7., according to claim 1 or a kind of pulse selectable adjustable signal generator based on FPGA according to claim 5, it is characterized in that: two single pulse widths of described double pulse modulation signal and spacing therebetween all by same be by key control and simultaneously that stepping-in amount regulates with 5ns.
8. a kind of pulse selectable adjustable signal generator based on FPGA according to claim 1, is characterized in that: described pulse modulation signal and double pulse modulation signal are selected to export by MUX.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520261458.2U CN204578517U (en) | 2015-04-28 | 2015-04-28 | A kind of pulse selectable adjustable signal generator based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520261458.2U CN204578517U (en) | 2015-04-28 | 2015-04-28 | A kind of pulse selectable adjustable signal generator based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204578517U true CN204578517U (en) | 2015-08-19 |
Family
ID=53871105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520261458.2U Expired - Fee Related CN204578517U (en) | 2015-04-28 | 2015-04-28 | A kind of pulse selectable adjustable signal generator based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204578517U (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106549656A (en) * | 2016-11-22 | 2017-03-29 | 章策珉 | A kind of frequency expands device |
| CN107490461A (en) * | 2017-07-14 | 2017-12-19 | 中国航发沈阳发动机研究所 | Periodically adjustable frequency-doubled signal generation method |
| CN107560646A (en) * | 2017-08-29 | 2018-01-09 | 广州海洋地质调查局 | A kind of optical fiber sensing system |
| CN108195761A (en) * | 2018-03-06 | 2018-06-22 | 南京信息工程大学 | A kind of adjustable molecule collimation experimental system of multidimensional |
| CN109274357A (en) * | 2018-09-21 | 2019-01-25 | 昆明理工大学 | A kind of duty ratio pulse modulated circuit not varying with frequency and its modulator approach |
| CN109471119A (en) * | 2018-09-30 | 2019-03-15 | 维沃移动通信有限公司 | A kind of method and terminal device controlling power consumption |
| CN110455400A (en) * | 2019-08-23 | 2019-11-15 | 武汉理工大学 | Based on dim light grid array and the adjustable distributed vibration sensing system of spatial resolution |
-
2015
- 2015-04-28 CN CN201520261458.2U patent/CN204578517U/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106549656A (en) * | 2016-11-22 | 2017-03-29 | 章策珉 | A kind of frequency expands device |
| CN107490461A (en) * | 2017-07-14 | 2017-12-19 | 中国航发沈阳发动机研究所 | Periodically adjustable frequency-doubled signal generation method |
| CN107560646A (en) * | 2017-08-29 | 2018-01-09 | 广州海洋地质调查局 | A kind of optical fiber sensing system |
| CN107560646B (en) * | 2017-08-29 | 2018-08-28 | 广州海洋地质调查局 | A kind of optical fiber sensing system |
| CN108195761A (en) * | 2018-03-06 | 2018-06-22 | 南京信息工程大学 | A kind of adjustable molecule collimation experimental system of multidimensional |
| CN108195761B (en) * | 2018-03-06 | 2023-08-11 | 南京信息工程大学 | Multi-dimensional adjustable molecular collimation experimental system |
| CN109274357A (en) * | 2018-09-21 | 2019-01-25 | 昆明理工大学 | A kind of duty ratio pulse modulated circuit not varying with frequency and its modulator approach |
| CN109471119A (en) * | 2018-09-30 | 2019-03-15 | 维沃移动通信有限公司 | A kind of method and terminal device controlling power consumption |
| CN110455400A (en) * | 2019-08-23 | 2019-11-15 | 武汉理工大学 | Based on dim light grid array and the adjustable distributed vibration sensing system of spatial resolution |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN204578517U (en) | A kind of pulse selectable adjustable signal generator based on FPGA | |
| TWI395511B (en) | Led driver and power control circuit with spread spectrum frequency modulation function and display panel using the same | |
| CN103347332B (en) | Signal processing method and circuit and the LED light adjusting circuits with the circuit | |
| CN102568391B (en) | Pwm signal generation circuit and method and LED driver circuit | |
| CN104137443B (en) | The control of closed loop optical modulation amplitude | |
| US20200296813A1 (en) | Modular lighting application | |
| CN204731577U (en) | A kind of multifunctional signal generator based on FPGA | |
| CN103297046A (en) | Phase-locked loop and method and circuit for producing clock thereof | |
| US8525609B1 (en) | Pulse width modulation circuits, systems and methods | |
| CN107222189A (en) | Digital pulse width modulator | |
| CN105027406B (en) | Impulse density D/A converter with slope-compensation function | |
| CN102184709A (en) | Display control method and device | |
| CN103022895A (en) | Laser tube power control system | |
| CN103956996B (en) | Based on the high-resolution digital pulse width modulator of double frequency multiphase clock | |
| CN110191540A (en) | Light-dimming method, dimming device and the computer-readable medium of LED | |
| TW202046271A (en) | Method for transmitting data from timing controller to source driver and associated timing controller and display system | |
| US9287884B2 (en) | Enhanced numerical controlled oscillator | |
| CN109525224B (en) | Pulse width modulation signal duty ratio multiplication circuit based on clock period | |
| TW200740122A (en) | Pulse generator, optical disk writer and tuner | |
| KR20140135776A (en) | High resolution pulse width modulator | |
| CN103874270A (en) | Light-emitting diode driving method and device | |
| US9244484B2 (en) | Fractional-N spread spectrum state machine | |
| CN109309487A (en) | A kind of signal spread spectrum control method and system | |
| RU2644070C1 (en) | Digital modulator for frequency conversion | |
| CN108762372B (en) | Driving signal generation system and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150819 Termination date: 20160428 |