CN204440258U - A kind of circuit board efficiently downloading and debug - Google Patents
A kind of circuit board efficiently downloading and debug Download PDFInfo
- Publication number
- CN204440258U CN204440258U CN201520169534.7U CN201520169534U CN204440258U CN 204440258 U CN204440258 U CN 204440258U CN 201520169534 U CN201520169534 U CN 201520169534U CN 204440258 U CN204440258 U CN 204440258U
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- China
- Prior art keywords
- pin
- data
- circuit board
- reset
- interface
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- Expired - Fee Related
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Abstract
The utility model provides a kind of circuit board efficiently downloading and debug, belong to the technical scheme of circuit field, this circuit board is provided with feed circuit and control chip, this control chip has the grounding pin for ground connection, for the energization pins be connected with feed circuit, for the clock pins of receive clock signal, for transmitting the data pin of data, and the reset pin for resetting, described circuit board is also provided with mini pci-e interface, this mini pci-e interface has the earth terminal for ground connection, for the feeder ear be connected with feed circuit, for the clock end be connected with clock pins, for the data terminal be connected with data pin, and the reset terminal for being connected with reset pin.Due to the interface that mini pci-e interface is Based PC I-E bus, its popularization is wide, stability is high, the instability of the row's of avoiding pin, also without the need to opening via hole, avoid and occurred the phenomenon such as hole plug, loose contact, thus the stability of download program, debugging can be improved.
Description
Technical field
The utility model relates to a kind of circuit board, particularly a kind of circuit board efficiently downloading and debug.
Background technology
In the design of existing electronic product is produced, most of electronic product needs to download line program debugging of going forward side by side.And the burning of electronic product program at present or debugging are mode by cushion hole mostly, these needs open via hole in advance in the circuit board, or welding row pin, which not only improves cost of products, and very easily block at the via hole in process of manufacturing of wiring board, bring very big inconvenience to the debugging of download below operation, and the connection extremely unstable in pin and hole, easily cause program not download, or program debug is unsuccessful, cause design or production work progress slow.
Utility model content
In order to overcome the deficiencies in the prior art, the purpose of this utility model is to provide a kind of circuit board efficiently downloading and debug, and this circuit board can solve prior art download program, debug the phenomenon easily gone wrong.
For solving the problem, the technical scheme that the utility model adopts is as follows:
A kind of circuit board efficiently downloading and debug, this circuit board is provided with feed circuit and control chip, this control chip has the grounding pin for ground connection, for the energization pins be connected with feed circuit, for the clock pins of receive clock signal, for transmitting the data pin of data, and the reset pin for resetting, described circuit board is also provided with mini pci-e interface, this mini pci-e interface has the earth terminal for ground connection, for the feeder ear be connected with feed circuit, for the clock end be connected with clock pins, for the data terminal be connected with data pin, and the reset terminal for being connected with reset pin.
Preferably, the energization pins of described control chip is connected with the first electric capacity, the second electric capacity and the 3rd electric capacity, and this end that this first electric capacity, the second electric capacity and the 3rd electric capacity are connected with energization pins is connected with feed circuit jointly, other end common ground.
Preferably, the reset pin of described control chip is connected with the first resistance and the 4th electric capacity, and this reset pin is connected with feed circuit by the first resistance, and this reset pin is also by the 4th capacity earth.
Compared to existing technology, the beneficial effects of the utility model are:
The stability of download program, debugging can be improved; Because mini pci-e interface is the interface of Based PC I-E bus, its popularization is wide, stability is high, the instability of the row's of avoiding pin, also without the need to opening via hole, avoiding and occurring the phenomenon such as hole plug, loose contact.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the utility model control chip;
Fig. 2 is the schematic diagram of the utility model mini pci-e interface.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
As illustrated in fig. 1 and 2, the circuit board efficiently downloading and debug described in the utility model, this circuit board is provided with feed circuit and control chip U1, this control chip U1 have for ground connection grounding pin GND, for be connected with feed circuit energization pins VCC, for the clock pins P2.2 of receive clock signal, for transmitting the data pin (being respectively the first data pin P2.1, the second data pin P0.2 and the 3rd data pin P0.3) of data and the reset pin RESET for resetting; As shown in Figure 2, described circuit board is also provided with mini pci-e interface P1, this mini pci-e interface P1 have for ground connection earth terminal 13, for be connected with feed circuit feeder ear 12, for be connected with clock pins P2.2 clock end 14, for the data terminal (being respectively the first data terminal 15, second data terminal 16 and the 3rd data terminal 17) that is connected with data pin and the reset terminal 18 for being connected with reset pin RESET.And described data pin is respectively the first data pin P2.1, the second data pin P0.2 and the 3rd data pin P0.3, described data terminal is respectively the first data terminal 15, second data terminal 16 and the 3rd data terminal 17, this first data pin P2.1 is connected with the first data terminal 15, this second data pin P0.2 is connected with the second data terminal 16, and the 3rd data pin P0.3 is connected with the 3rd data terminal 17.
Wherein, the energization pins VCC of described control chip U1 is connected with the first electric capacity C17, the second electric capacity C10 and the 3rd electric capacity C11, this end that this first electric capacity C17, the second electric capacity C10 and the 3rd electric capacity C11 are connected with energization pins VCC is connected with feed circuit jointly, other end common ground.
In addition, the reset pin RESET stating control chip U1 is connected with the first resistance R4 and the 4th electric capacity C8, and this reset pin RESET is connected with feed circuit by the first resistance R4, and this reset pin RESET is also by the 4th electric capacity C8 ground connection.
On clock pins P2.2 on control chip U1 and the first data pin P2.1 and mini pci-e interface P1, clock end 14 and the first data terminal 15 are Debug Clk and Debug Date respectively, are used clock line and data lines when downloading.Wherein clock pins P2.2 and clock end 14 are used to tranmitting data register pulse, time clock just as the pulse of people, fixing transmission at set intervals pulse.First data pin P2.1 and the first data terminal 15 are used to transmission data, and whenever transmission pulse, control chip U1 attends school away a data, reaches with this object downloaded.The second data terminal 16 on the upper second data pin P0.2 of control chip U1 and the 3rd data pin P0.3 and mini pci-e interface P1 and the 3rd data terminal 17 are respectively used to data receiver and the data transmission of serial communication.As its name suggests, data receiver receives data exactly, and it is exactly send data that data send, and in this way, control chip U1 just can carry out exchanges data with other equipment outside, and is exactly the hardware debug having carried out program in this way.Reset terminal 18 on control chip U1 on reset pin RESET and mini pci-e interface P1, for resetting, when control chip U1 deadlock cisco unity malfunction or when program can not download, carrys out reset chip by this pin, makes it normally work.
Above-mentioned embodiment is only preferred implementation of the present utility model; can not limit the scope of the utility model protection with this, change and the replacement of any unsubstantiality that those skilled in the art does on basis of the present utility model all belong to the utility model scope required for protection.
Claims (3)
1. the circuit board efficiently downloading and debug, this circuit board is provided with feed circuit and control chip, this control chip has the grounding pin for ground connection, for the energization pins be connected with feed circuit, for the clock pins of receive clock signal, for transmitting the data pin of data, and the reset pin for resetting, it is characterized in that: described circuit board is also provided with mini pci-e interface, this mini pci-e interface has the earth terminal for ground connection, for the feeder ear be connected with feed circuit, for the clock end be connected with clock pins, for the data terminal be connected with data pin, and the reset terminal for being connected with reset pin.
2. circuit board according to claim 1, it is characterized in that: the energization pins of described control chip is connected with the first electric capacity, the second electric capacity and the 3rd electric capacity, this end that this first electric capacity, the second electric capacity and the 3rd electric capacity are connected with energization pins is connected with feed circuit jointly, other end common ground.
3. circuit board according to claim 1, is characterized in that: the reset pin of described control chip is connected with the first resistance and the 4th electric capacity, and this reset pin is connected with feed circuit by the first resistance, and this reset pin is also by the 4th capacity earth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520169534.7U CN204440258U (en) | 2015-03-24 | 2015-03-24 | A kind of circuit board efficiently downloading and debug |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520169534.7U CN204440258U (en) | 2015-03-24 | 2015-03-24 | A kind of circuit board efficiently downloading and debug |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN204440258U true CN204440258U (en) | 2015-07-01 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520169534.7U Expired - Fee Related CN204440258U (en) | 2015-03-24 | 2015-03-24 | A kind of circuit board efficiently downloading and debug |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN204440258U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160154764A1 (en) * | 2014-11-28 | 2016-06-02 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Electronic device and electronic device assembly |
| US20160154763A1 (en) * | 2014-11-28 | 2016-06-02 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Electronic device and electronic device assembly |
-
2015
- 2015-03-24 CN CN201520169534.7U patent/CN204440258U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160154764A1 (en) * | 2014-11-28 | 2016-06-02 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Electronic device and electronic device assembly |
| US20160154763A1 (en) * | 2014-11-28 | 2016-06-02 | Hong Fu Jin Precision Industry (Wuhan) Co., Ltd. | Electronic device and electronic device assembly |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150701 Termination date: 20200324 |