CN204424909U - A kind of chain type SVG chain link control system - Google Patents
A kind of chain type SVG chain link control system Download PDFInfo
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- CN204424909U CN204424909U CN201420870831.XU CN201420870831U CN204424909U CN 204424909 U CN204424909 U CN 204424909U CN 201420870831 U CN201420870831 U CN 201420870831U CN 204424909 U CN204424909 U CN 204424909U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/10—Flexible AC transmission systems [FACTS]
Abstract
A kind of chain type SVG chain link control system, comprises FPGA controller, chain link controller display circuit, fiber optic interface circuits, electric power management circuit, power sense circuit, overtemperature testing circuit, excess temperature testing circuit, superpressure testing circuit, over-voltage detection circuit, sampling filter circuit, pulse modulate circuit; Wherein electric power management circuit, power sense circuit, overtemperature testing circuit, excess temperature testing circuit, superpressure testing circuit, over-voltage detection circuit, the signal output part of sampling filter circuit are connected with the signal input part of FPGA controller; The signal input part of chain link controller display circuit, pulse signal modulate circuit is connected with the signal output part of FPGA controller respectively; The signal input output end of fiber optic interface circuits is connected with the signal input output end of FPGA controller, chain type SVG chain link control system of the present utility model in real time, accurately, gather the state information of link units reliably, can ensure that link units is stable, safe and reliable operation.
Description
Technical field
The utility model relates to intelligent grid field, particularly relates to a kind of chain type SVG control system controlled link units.
Background technology
From the SVG eighties in last century (static reacance generator) by since utility model, the major company of the states such as China, Japan, the U.S., Germany, France and scientific research institution, successively have developed the SVG device of various electric pressure, and actual motion in electric power system.The product structure of the device of SVG is also varied, and actual being mainly used in has the many level block of multiple inverter configuration, diode clamp and cascade connection multi-level formula structure in SVG device at present.Cascade connection multi-level formula structure as far back as the seventies in last century just oneself through being suggested, but mainly concentrate on passive aspect due to power system reactive power compensation and harmonic wave control at that time, active technique does not also have ripe application.Along with the raising of production technology and power consumer increase the requirement of the quality of power supply, occasion cascaded multilevel structure being applied to SVG is just started to the nineties, subsequently a large amount of applied analyses is carried out to cascaded multilevel structure key technology, fully excavate its advantage in mesohigh compensation, tandem type mesohigh SVG is paid close attention to widely since then.
The SVG of tandem type structure, owing to having the advantages such as high-power output, low switching frequency and low harmony wave pollution, obtains most attention and studies application widely.Particularly be applied to the occasions such as wind energy turbine set, steel industry, photovoltaic project, because it can instantaneously supplement idle, effectively can prevent Voltage Drop, administer harmonic wave, ensure the normal operation of the equipment such as blower fan, refining furnace.But one of subject matter of tandem type SVG is exactly the multiplex stability problem of chain link, chain link reliable and stable is tandem type SVG structure is that enterprise produces and debugging major part, the tandem type SVG device of a such as 10kV has 36 link units, and 35kV need 126 chain links especially, ensure stable, the safety of link units, be reliably exactly ensure that product quality and system safety.So performance test will be carried out to each chain link before chain link is applied to chain type SVG device.Link units is as the chief component of chain type SVG, and its performance directly determines the safety and stability of chain type SVG device in actual motion.It also determines production efficiency and the difficulty of test of chain type SVG manufacturer simultaneously, therefore the state information of link units how in real time, accurately, is gathered reliably, thus ensure that link units is stable, safe and reliable operation, become the technical problem needing solution badly.
Utility model content
The purpose of this utility model is to provide a kind of chain type SVG chain link control system, for solving the problems of the technologies described above.
Chain type SVG chain link control system of the present utility model, comprises FPGA controller, chain link controller display circuit, fiber optic interface circuits, electric power management circuit, power sense circuit, overtemperature testing circuit, excess temperature testing circuit, superpressure testing circuit, over-voltage detection circuit, sampling filter circuit, pulse modulate circuit; Wherein electric power management circuit, power sense circuit, overtemperature testing circuit, excess temperature testing circuit, superpressure testing circuit, over-voltage detection circuit, the signal output part of sampling filter circuit are connected with the signal input part of FPGA controller; The signal input part of chain link controller display circuit, pulse signal modulate circuit is connected with the signal output part of FPGA controller respectively; The signal input output end of fiber optic interface circuits is connected with the signal input output end of FPGA controller;
Described chain link controller display circuit is used for the state information of display link units in real time; Described fiber optic interface circuits is for realizing the communication between chain type SVG chain link control system and tandem type SVG device master control system; Electric power management circuit is for realizing the isolated controlling of strong and weak electricity; Described power sense circuit is used for real-time monitoring system forceful electric power state and feeds back to FPGA controller; Overtemperature testing circuit is connected with overtemperature temperature switch and is used for Real-Time Monitoring link unit whether overtemperature, and detection signal is fed back to FPGA controller; Excess temperature testing circuit is connected with excess temperature temperature switch and is used for Real-Time Monitoring link unit whether excess temperature, and detection signal is fed back to FPGA controller; Superpressure testing circuit is used for supervising in real time its exterior direct voltage whether superpressure by being connected with instrument transformer, and detection signal is fed back to FPGA controller; Over-voltage detection circuit is used for supervising in real time the whether overvoltage of its exterior direct voltage by being connected with instrument transformer, and detection signal is fed back to FPGA controller; The control signal that pulse signal modulate circuit is used for real-time reception FPGA controller controls link units by link units IGBT control circuit, and described link units IGBT control circuit is also connected with the signal input part of FPGA controller; Sampling filter circuit is connected by instrument transformer and is used for Real-time Collection external dc magnitude of voltage and feeds back to FPGA controller.
Described fiber optic interface circuits comprises two-way output optical fibre, four road input optical fibres, and described two-way output optical fibre is used for the information transmission of link units chain type SVG chain link control system gathered to tandem type SVG device master control system; Described four road input optical fibres are used for the control signal of tandem type SVG device master control system to be transferred to chain type SVG chain link control system, realize the control of the IGBT drive circuit of link units.
Described chain link controller display circuit comprises the first instruction to the 9th indicator light, resistance is to resistance, conversion chip, first indicator light is to one end ground connection of the 6th indicator light, the other end accesses conversion chip after series resistance to resistance respectively, 7th indicator light is to one end ground connection of the 9th indicator light, and the other end connects FPGA controller after series resistance to resistance respectively.
Described sampling filter circuit comprises resistance R10 to resistance R12, electric capacity C1 to electric capacity C3, the first diode, the second diode, the first operational amplifier, the positive pole of described first diode connects the positive pole of the first operational amplifier, and negative pole connects the negative pole of the first operational amplifier; The positive pole of described second diode connects the negative pole of the first operational amplifier, and negative pole connects the positive pole of the first operational amplifier; Electric capacity C1, resistance R10 are in parallel, one end ground connection, the positive pole of another termination first operational amplifier; Output series resistance R11, the resistance R12 successively of the first operational amplifier, electric capacity C2, electric capacity C3 series connection after be connected in parallel on resistance R12 two ends, electric capacity C2 and electric capacity C3 indirectly.
Described link units IGBT control circuit comprises resistance R20 to resistance R22, electric capacity C5 to C6, the 4th diode, two positive ment and Schmidt trigger; First pin of the two positive ment of one termination of resistance R20 and the second pin, first pin and second pin of two positive ment connect input signal, the pin of the two positive ment of resistance R21 mono-termination, another termination positive source, the 3rd of two positive ment the is serially connected between pin and the input of Schmidt trigger after resistance R22 is in parallel with diode D4, series capacitance C6 between the input of Schmidt trigger and ground, series capacitance C5 between the VDD-to-VSS of Schmidt trigger.
Described protective circuit comprises resistance R13 to resistance R19, electric capacity C4, second operational amplifier, 3rd operational amplifier, 3rd diode and photoisolator, the negative pole of one termination second operational amplifier of resistance R13, between the negative pole that resistance R14 is connected on the second operational amplifier and output, the just very input of the second operational amplifier, resistance R15 is in series with between the output of the second operational amplifier and the negative pole of the 3rd operational amplifier, one end of resistance R16 is connected with the positive pole of the 3rd operational amplifier, between the positive pole that resistance R17 is connected on the 3rd operational amplifier and output, resistance R18 is in series with between the output of the 3rd operational amplifier and the first pin of photoisolator, first pin of photoisolator connects the negative pole of the 3rd diode, be in series with between the second pin that the positive pole of the 3rd diode connects photoisolator, 4th pin ground connection of photoisolator, 3rd sequential series between pin and ground of photoisolator has resistance R19 and electric capacity C4, the indirect power supply of resistance R19 and electric capacity C4.
The beneficial effects of the utility model are, by the state parameter of the multiple link units in chain type SVG chain link control system real-time acquisition system, achieve state information that is real-time, accurate, that gather link units reliably, ensure that link units is stable, safe and reliable operation.
Below in conjunction with accompanying drawing, chain type SVG chain link control system of the present utility model is described further.
Accompanying drawing explanation
Fig. 1 is the theory diagram of chain type SVG chain link control system;
Fig. 2 is chain link controller display circuit schematic diagram;
Fig. 3 is sampling filter circuit theory diagrams;
Fig. 4 is link units IGBT control circuit schematic diagram;
Fig. 5 is protective circuit schematic diagram.
Embodiment
As shown in Figure 1, chain type SVG chain link control system of the present utility model, comprises FPGA controller 1, chain link controller display circuit 3, fiber optic interface circuits 2, electric power management circuit 4, power sense circuit 5, overtemperature testing circuit 6, excess temperature testing circuit 7, superpressure testing circuit 8, over-voltage detection circuit 9, sampling filter circuit 10, pulse modulate circuit 12; Wherein the signal output part of electric power management circuit 4, power sense circuit 5, overtemperature testing circuit 6, excess temperature testing circuit 7, superpressure testing circuit 8, over-voltage detection circuit 9, sampling filter circuit 10 is connected with the signal input part of FPGA controller 1; The signal input part of chain link controller display circuit 3, pulse signal modulate circuit 12 is connected with the signal output part of FPGA controller 1 respectively; The signal input output end of fiber optic interface circuits 2 is connected with the signal input output end of FPGA controller 1;
Described chain link controller display circuit 3 is for showing the state information of link units in real time; Described fiber optic interface circuits 2 is for realizing the communication between chain type SVG chain link control system and tandem type SVG device master control system; Electric power management circuit 4 is for realizing the isolated controlling of strong and weak electricity; Described power sense circuit 5 is for real-time monitoring system forceful electric power state and feed back to FPGA controller 1; Overtemperature testing circuit 6 is connected with overtemperature temperature switch 16 and is used for Real-Time Monitoring link unit whether overtemperature, and detection signal is fed back to FPGA controller 1; Excess temperature testing circuit 7 is connected with excess temperature temperature switch 15 and is used for Real-Time Monitoring link unit whether excess temperature, and detection signal is fed back to FPGA controller 1; Superpressure testing circuit 8 is used for supervising in real time its exterior direct voltage 14 whether superpressure by being connected with instrument transformer 11, and detection signal is fed back to FPGA controller 1; Over-voltage detection circuit 9 is used for supervising in real time its exterior direct voltage 14 whether overvoltage by being connected with instrument transformer 11, and detection signal is fed back to FPGA controller 1; Pulse signal modulate circuit 12 controls link units for the control signal of real-time reception FPGA controller 1 by link units IGBT control circuit 13, and described link units IGBT control circuit 13 is also connected with the signal input part of FPGA controller 1; Sampling filter circuit 10 is connected by instrument transformer 11 and is worth for Real-time Collection external dc voltage 14 and feeds back to FPGA controller 1.
Fiber optic interface circuits 2 comprises two-way output optical fibre, four road input optical fibres, and described two-way output optical fibre is used for the information transmission of link units chain type SVG chain link control system gathered to tandem type SVG device master control system; Described four road input optical fibres are used for the control signal of tandem type SVG device master control system to be transferred to chain type SVG chain link control system, realize the control of the IGBT drive circuit of link units.
FPGA controller 1 sends tandem type SVG device master control system to by a road output optical fibre after the link units information collected is carried out integrated treatment, adopts an independent optical fiber to carry out Signal transmissions, more fast and reliable can protect link units.
The link units voltage collected and link units state information are carried out integrated treatment coding by FPGA controller 1, give tandem type SVG device master control system by another road output optical fibre.
The information that FPGA controller 1 receives four road input optical fibres is decoded, be treated as the command signal that IGBT control circuit can identify, determine the operating state of link units, thus realize receiving information from SVG main controller system, and realize the control work of IGBT control circuit.
As shown in Figure 2, chain link controller display circuit 3 comprises the first indicator light LED1 to the 9th indicator light LED9, resistance R1 is to resistance R9, conversion chip, first indicator light LED1 is to one end ground connection of the 6th indicator light LED6, the other end respectively series resistance R1 accesses conversion chip to resistance R6,7th indicator light LED7 is to one end ground connection of the 9th indicator light LED9, and the other end respectively series resistance R7 connects FPGA controller to resistance R9.
FPGA controller 1 by all signals of link units of collecting after treatment, by the indicator light display of design on chain link controller display circuit 3, realizes the Presentation Function to link units operating state.
As shown in Figure 3, described sampling filter circuit 10 comprises resistance R10 to resistance R12, electric capacity C1 to electric capacity C3, the first diode D1, the second diode D2, the first operational amplifier Y1, the positive pole of described first diode D1 connects the positive pole of the first operational amplifier Y1, and negative pole connects the negative pole of the first operational amplifier Y1; The positive pole of described second diode D2 connects the negative pole of the first operational amplifier Y1, and negative pole connects the positive pole of the first operational amplifier Y1; Electric capacity C1, resistance R10 are in parallel, one end ground connection, the positive pole of another termination first operational amplifier Y1; Output series resistance R11, the resistance R12 successively of the first operational amplifier Y1, electric capacity C2, electric capacity C3 series connection after be connected in parallel on resistance R12 two ends, electric capacity C2 and electric capacity C3 indirectly.
Direct voltage 14, after instrument transformer 11, is nursed one's health through sampling filter circuit 10, A/D change-over circuit, exports serial line data sending and processes to FPGA controller, realize the collecting work of link units voltage.What the core devices of A/D change-over circuit adopted the is high speed serialization AD of 12, low in energy consumption, precision is high, controls is simple, the voltage compare loop of sampling filter circuit employing uniqueness, the voltage after making filtering conditioned is more accurate.
As shown in Figure 4, link units IGBT control circuit comprises resistance R20 to resistance R22, electric capacity C5 to C6, the 4th diode D4, two positive ment U2 and Schmidt trigger U3; First pin of the two positive ment U2 of one termination of resistance R20 and the second pin, first pin and second pin of two positive ment U2 connect input signal, 3rd pin of the two positive ment U2 of resistance R21 mono-termination, another termination positive source, between the 3rd pin being serially connected in two positive ment U2 after resistance R22 is in parallel with diode D4 and the input 1 of Schmidt trigger U3, series capacitance C6 between the input 1 of Schmidt trigger U3 and ground, series capacitance C5 between the VDD-to-VSS of Schmidt trigger U3.
The signal that FPGA controller 1 receives, IGBT module driving governor is sent to after being processed by link units IGBT control circuit 13, control controller works, and is accepted the feedback signal of module drive controller simultaneously, realize the controlling functions of link units IGBT by return circuit.
On the basis of above-described embodiment, chain type SVG chain link control system of the present utility model, also comprises protective circuit 18.
As shown in Figure 5, protective circuit 18 comprises resistance R13 to resistance R19, electric capacity C4, second operational amplifier Y2, 3rd operational amplifier Y3, 3rd diode D3 and photoisolator U1, the negative pole of the one termination second operational amplifier Y2 of resistance R13, between the negative pole that resistance R14 is connected on the second operational amplifier Y2 and output, the just very input of the second operational amplifier Y2, resistance R15 is in series with between the output of the second operational amplifier Y2 and the negative pole of the 3rd operational amplifier Y3, one end of resistance R16 is connected with the positive pole of the 3rd operational amplifier Y3, between the positive pole that resistance R17 is connected on the 3rd operational amplifier Y3 and output, resistance R18 is in series with between the output of the 3rd operational amplifier Y3 and first pin of photoisolator U1, first pin of photoisolator U1 connects the negative pole of the 3rd diode D3, be in series with between the second pin that the positive pole of the 3rd diode D3 meets photoisolator U1, the 4th pin ground connection of photoisolator U1, 3rd sequential series between pin and ground of photoisolator U1 has resistance R19 and electric capacity C4, the indirect power supply of resistance R19 and electric capacity C4.
Link units has 6 kinds of faults, is respectively IGBT fault, superpressure fault, overvoltage fault, overtemperature fault, excess temperature fault and power failure.
IGBT fault: IGBT drive module 19 feedback signal is by delivering to FPGA controller 1 after filter circuit process, after FPGA controller 1 detects signal, block IGBT drive module 19, IGBT is made to be in off state, fault message is also uploaded to tandem type SVG device master control system and carries out failure logging by FPGA controller 1 latch fault information, in order to carrying out fault inquiry, this fault can not be recovered automatically.
Superpressure fault: direct voltage 11 is after instrument transformer, FPGA controller 1 is sent to after filtering after circuit, comparison circuit, after FPGA controller 1 detects signal, block IGBT drive module, IGBT is made to be in off state, fault message is also uploaded to tandem type SVG device master control system and carries out failure logging by FPGA controller 1 latch fault information, and in order to carrying out fault inquiry, this fault can not be recovered automatically.
Overvoltage fault: direct voltage 11 is after instrument transformer 10, FPGA controller 1 is sent to after filtering after circuit, comparison circuit, after FPGA controller 1 detects signal, block IGBT drive module, IGBT is made to be in off state, fault message is also uploaded to tandem type SVG device master control system and carries out failure logging by FPGA controller 1 latch fault information, and in order to carrying out fault inquiry, this fault can be recovered automatically.
Overtemperature fault: overtemperature switching signal is sent to FPGA controller 1 after circuit after filtering, after FPGA controller 1 detects signal, block IGBT drive module, IGBT is made to be in off state, fault message is also uploaded to tandem type SVG device master control system and carries out failure logging by FPGA controller 1 latch fault information, in order to carrying out fault inquiry, this fault can be recovered automatically.
Excess temperature fault: excess temperature switching signal is sent to FPGA controller 1 after circuit after filtering, after FPGA controller 1 detects signal, fault message is uploaded to tandem type SVG device master control system and carries out failure logging, in order to carrying out fault inquiry, this fault can be recovered automatically.
Power failure: adopt AC220V power supply 17 to power, power to each device by electric power management circuit 4, strong and weak electricity is process separately, adds device antijamming capability; FPGA controller 1 is powered by power sense circuit 5 direct-detection AC220V, after fault-signal being detected, block IGBT drive module, IGBT is made to be in off state, fault message is also uploaded to tandem type SVG device master control system and carries out failure logging by FPGA controller 1 latch fault information, in order to carrying out fault inquiry, this fault can be recovered automatically.
Above-described embodiment is only be described preferred implementation of the present utility model; not scope of the present utility model is limited; under the prerequisite not departing from the utility model design spirit; the various distortion that those of ordinary skill in the art make the technical solution of the utility model and improvement, all should fall in protection range that the utility model claims determine.
Claims (6)
1. a chain type SVG chain link control system, comprise FPGA controller (1), it is characterized in that, also comprise chain link controller display circuit (3), fiber optic interface circuits (2), electric power management circuit (4), power sense circuit (5), overtemperature testing circuit (6), excess temperature testing circuit (7), superpressure testing circuit (8), over-voltage detection circuit (9), sampling filter circuit (10), pulse modulate circuit (12); Wherein the signal output part of electric power management circuit (4), power sense circuit (5), overtemperature testing circuit (6), excess temperature testing circuit (7), superpressure testing circuit (8), over-voltage detection circuit (9), sampling filter circuit (10) is connected with the signal input part of FPGA controller (1); The signal input part of chain link controller display circuit (3), pulse signal modulate circuit (12) is connected with the signal output part of FPGA controller (1) respectively; The signal input output end of fiber optic interface circuits (2) is connected with the signal input output end of FPGA controller (1);
Described chain link controller display circuit (3) is for showing the state information of link units in real time; Described fiber optic interface circuits (2) is for realizing the communication between chain type SVG chain link control system and tandem type SVG device master control system; Electric power management circuit (4) is for realizing the isolated controlling of strong and weak electricity; Described power sense circuit (5) is for real-time monitoring system forceful electric power state and feed back to FPGA controller (1); Overtemperature testing circuit (6) is connected with overtemperature temperature switch (16) and is used for Real-Time Monitoring link unit whether overtemperature, and detection signal is fed back to FPGA controller (1); Excess temperature testing circuit (7) is connected with excess temperature temperature switch (15) and is used for Real-Time Monitoring link unit whether excess temperature, and detection signal is fed back to FPGA controller (1); Superpressure testing circuit (8) is used for supervising in real time its exterior direct voltage (14) whether superpressure by being connected with instrument transformer (11), and detection signal is fed back to FPGA controller (1); Over-voltage detection circuit (9) is used for supervising in real time its exterior direct voltage (14) whether overvoltage by being connected with instrument transformer (11), and detection signal is fed back to FPGA controller (1); Pulse signal modulate circuit (12) controls link units for the control signal of real-time reception FPGA controller (1) by link units IGBT control circuit (13), and described link units IGBT control circuit (13) is also connected with the signal input part of FPGA controller (1); Sampling filter circuit (10) is connected by instrument transformer (11) and is used for Real-time Collection external dc voltage (14) value and feeds back to FPGA controller (1).
2. chain type SVG chain link control system according to claim 1, it is characterized in that, described fiber optic interface circuits (2) comprises two-way output optical fibre, four road input optical fibres, and described two-way output optical fibre is used for the information transmission of link units chain type SVG chain link control system gathered to tandem type SVG device master control system; Described four road input optical fibres are used for the control signal of tandem type SVG device master control system to be transferred to chain type SVG chain link control system, realize the control of the IGBT drive circuit of link units.
3. chain type SVG chain link control system according to claim 2, it is characterized in that, described chain link controller display circuit (3) comprises the first indicator light LED1 to the 9th indicator light LED9, resistance R1 is to resistance R9, conversion chip, first indicator light LED1 is to one end ground connection of the 6th indicator light LED6, the other end respectively series resistance R1 accesses conversion chip to resistance R6,7th indicator light LED7 is to one end ground connection of the 9th indicator light LED9, and the other end respectively series resistance R7 connects FPGA controller to resistance R9.
4. chain type SVG chain link control system according to claim 3, it is characterized in that, described sampling filter circuit (10) comprises resistance R10 to resistance R12, electric capacity C1 to electric capacity C3, the first diode D1, the second diode D2, the first operational amplifier Y1, the positive pole of described first diode D1 connects the positive pole of the first operational amplifier Y1, and negative pole connects the negative pole of the first operational amplifier Y1; The positive pole of described second diode D2 connects the negative pole of the first operational amplifier Y1, and negative pole connects the positive pole of the first operational amplifier Y1; Electric capacity C1, resistance R10 are in parallel, one end ground connection, the positive pole of another termination first operational amplifier Y1; Output series resistance R11, the resistance R12 successively of the first operational amplifier Y1, electric capacity C2, electric capacity C3 series connection after be connected in parallel on resistance R12 two ends, electric capacity C2 and electric capacity C3 indirectly.
5. chain type SVG chain link control system according to claim 4, it is characterized in that, described link units IGBT control circuit comprises resistance R20 to resistance R22, electric capacity C5 to C6, the 4th diode D4, two positive ment U2 and Schmidt trigger U3, first pin of the two positive ment U2 of one termination of resistance R20 and the second pin, the other end ground connection of resistance R20, first pin and second pin of two positive ment U2 connect input signal, 3rd pin of the two positive ment U2 of resistance R21 mono-termination, another termination positive source, between the 3rd pin being serially connected in two positive ment U2 after resistance R22 is in parallel with the 4th diode D4 and the input 1 of Schmidt trigger U3, series capacitance C6 between the input 1 of Schmidt trigger U3 and ground, series capacitance C5 between the VDD-to-VSS of Schmidt trigger U3.
6. according to the arbitrary described chain type SVG chain link control system of claim 1 to 5, it is characterized in that, also comprise protective circuit and comprise resistance R13 to resistance R19, electric capacity C4, second operational amplifier Y2, 3rd operational amplifier Y3, 3rd diode D3 and photoisolator U1, the negative pole of the one termination second operational amplifier Y2 of resistance R13, the other end ground connection of resistance R13, between the negative pole that resistance R14 is connected on the second operational amplifier Y2 and output, the just very input of the second operational amplifier Y2, resistance R15 is in series with between the output of the second operational amplifier Y2 and the negative pole of the 3rd operational amplifier Y3, one end of resistance R16 is connected with the positive pole of the 3rd operational amplifier Y3, another termination reference voltage of resistance R16, between the positive pole that resistance R17 is connected on the 3rd operational amplifier Y3 and output, resistance R18 is in series with between the output of the 3rd operational amplifier Y3 and first pin of photoisolator U1, first pin of photoisolator U1 connects the negative pole of the 3rd diode D3, the positive pole of the 3rd diode D3 connects second pin of photoisolator U1, the second pin ground connection of photoisolator U1, the 4th pin ground connection of photoisolator U1, 3rd sequential series between pin and ground of photoisolator U1 has resistance R19 and electric capacity C4, the indirect power supply of resistance R19 and electric capacity C4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420870831.XU CN204424909U (en) | 2014-12-31 | 2014-12-31 | A kind of chain type SVG chain link control system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420870831.XU CN204424909U (en) | 2014-12-31 | 2014-12-31 | A kind of chain type SVG chain link control system |
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| CN204424909U true CN204424909U (en) | 2015-06-24 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104466992A (en) * | 2014-12-31 | 2015-03-25 | 山东蓝天电能科技有限公司 | Chained SVG chain link control system and method |
| CN112186716A (en) * | 2020-09-07 | 2021-01-05 | 季华实验室 | IPM module fault detection and protection circuit of servo driver |
-
2014
- 2014-12-31 CN CN201420870831.XU patent/CN204424909U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104466992A (en) * | 2014-12-31 | 2015-03-25 | 山东蓝天电能科技有限公司 | Chained SVG chain link control system and method |
| CN112186716A (en) * | 2020-09-07 | 2021-01-05 | 季华实验室 | IPM module fault detection and protection circuit of servo driver |
| CN112186716B (en) * | 2020-09-07 | 2023-04-07 | 季华实验室 | IPM module fault detection and protection circuit of servo driver |
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