CN204408610U - A kind of high bandwidth from gain audio frequency processing system - Google Patents
A kind of high bandwidth from gain audio frequency processing system Download PDFInfo
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- CN204408610U CN204408610U CN201420738286.9U CN201420738286U CN204408610U CN 204408610 U CN204408610 U CN 204408610U CN 201420738286 U CN201420738286 U CN 201420738286U CN 204408610 U CN204408610 U CN 204408610U
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Abstract
The utility model discloses a kind of high bandwidth from gain audio frequency processing system, it is characterized in that: primarily of signal acquisition circuit, the signal debug circuit be connected with signal acquisition circuit, the linear drive circuit be simultaneously connected with signal debug circuit and signal acquisition circuit, be connected with signal debug circuit from gain control circuit, the signal processing circuit be connected with linear drive circuit, the audio frequency processing circuit be connected with from gain control circuit forms; Described linear drive circuit by driving chip U, triode VT5, triode VT6, triode VT7, triode VT8, the compositions such as the polar capacitor C10 that positive pole is connected with signal debug circuit, negative pole is connected with the IN1 pin of driving chip U after resistance R16.The utility model adds linear drive circuit, makes treatment system still keep very high stability when processing broadband signal.
Description
Technical field
The utility model relates to a kind of audio frequency processing system, specifically refer to a kind of high bandwidth from gain audio frequency processing system.
Background technology
Audio reception device has been indispensable instrument in daily life, study, work, but in use for some reason, as switching channels, broadcast advertisement etc., there will be the situation that volume differs when signal exports, have a strong impact on the audibility of user.Producing the larger main cause of this volume difference is that the amplitude that audio signal inputs is inconsistent, and solution carries out gain control exactly.
But current gain audio frequency control treatment system is analog circuit detection control, its Analog Circuit Design is relatively loaded down with trivial details, and the gain being difficult to realize relative broad range controls, and affects audibility.
Utility model content
The purpose of this utility model is to solve current loaded down with trivial details and be difficult to realize the defect that wide region gain controls from gain Design of Digital Audio Processing System, provide a kind of high bandwidth from gain audio frequency processing system.
The purpose of this utility model by following technical proposals reality: a kind of high bandwidth from gain audio frequency processing system, primarily of signal acquisition circuit, the signal debug circuit be connected with signal acquisition circuit, the linear drive circuit be simultaneously connected with signal debug circuit and signal acquisition circuit, be connected with signal debug circuit from gain control circuit, the signal processing circuit be connected with linear drive circuit, the audio frequency processing circuit be connected with from gain control circuit forms, described linear drive circuit is by driving chip U, triode VT5, triode VT6, triode VT7, triode VT8, positive pole is connected with signal debug circuit, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U after resistance R16, one end is connected with the collector electrode of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT7 after resistance R18, positive pole is connected with the base stage of triode VT5, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT5, the resistance R20 that the other end is connected with the base stage of triode VT6, one end is connected with the base stage of triode VT6, the resistance R19 that the other end is connected with the base stage of triode VT7, N pole is connected with the collector electrode of triode VT5, the diode D3 that P pole is connected with the collector electrode of triode VT6, positive terminal is connected with the collector electrode of triode VT5, the not gate Y that end of oppisite phase is connected with the collector electrode of triode VT8, one end is connected with triode VT8 emitter, the resistance R22 that the other end is connected with the emitter of triode VT7 after resistance R21, the end of oppisite phase of P pole NAND gate Y is connected, the diode D2 that N pole is connected with the tie point of resistance R21 with resistance R22 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT5, END pin ground connection, OUT pin are connected with the collector electrode of triode VT6, the collector electrode of triode VT6 is also connected with the base stage of triode VT8, its emitter is connected with the base stage of triode man VT7, the grounded collector of triode VT7, the N pole of diode D2 is connected with signal acquisition circuit and signal processing circuit simultaneously.
Described signal acquisition circuit comprises potentiometer R1, resistance R4, resistance R5, polar capacitor C1, polar capacitor C3, triode VT1; The collector electrode of triode VT1 is connected with signal debug circuit, its emitter is then connected with the sliding end of potentiometer R1 after polar capacitor C1 as signal input part, its base stage after potentiometer R1 through resistance R5, polar capacitor C3 and resistance R5 is in parallel, one end of resistance R4 is connected with signal debug circuit, the other end is then connected with the tie point of potentiometer R1 with resistance R5, and the tie point of described resistance R5 and potentiometer R1 is connected with the N pole of diode D2 and signal processing circuit simultaneously.
Described signal debug circuit is by triode VT2, the polar capacitor C2 that negative pole is connected with the base stage of triode VT2, positive pole is connected with resistance R4, the potentiometer R3 that one end is connected with the emitter of triode VT2, the other end is connected with the collector electrode of triode VT1, and the potentiometer R2 that one end is connected with the emitter of triode VT2, the other end is connected with the positive pole of polar capacitor C2 forms; The emitter of triode VT2 also with from gain control circuit is connected, its collector electrode is then connected with the positive pole of electric capacity C10, and potentiometer R2 is all connected with the emitter of triode VT2 with the sliding end of potentiometer R3.
Described signal processing circuit is by triode VT4, the resistance R9 that one end is connected with the collector electrode of triode VT4, the other end is connected with from gain control circuit, the resistance R8 that one end is connected with the emitter of triode VT4, the other end is connected with audio frequency processing circuit, the resistance R7 that one end is connected with the tie point of audio frequency processing circuit with resistance R8, and the resistance R6 that one end is connected with the base stage of triode VT4, the other end is then connected with the N pole of diode D2 forms.
Described from gain control circuit by operational amplifier P, triode VT3, diode D1, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C4 that positive pole is then connected with the emitter of triode VT2, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C5 that positive pole is connected with the emitter of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R10 of other end ground connection, positive pole is connected with the base stage of triode VT3, the polar capacitor C6 of minus earth, and one end is connected with the P pole of diode D1, the resistance R11 that the other end is connected with the VS+ pin of operational amplifier P forms, the end of oppisite phase of described operational amplifier P is connected with resistance R9, its VS-pin is connected with external power source, output is connected with the tie point of resistance R8 and resistance R7 and audio frequency processing circuit simultaneously, and the P pole of diode D1 is connected with external power source, its N pole is then connected with the emitter of triode VT3.
Described audio frequency processing circuit is by audio processing chip K, positive pole is connected with the GAIN2 pin of audio processing chip K after resistance R13, the polar capacitor C7 that negative pole is connected with the GAIN1 pin of audio processing chip K after polar capacitor C8, positive pole is connected with the OUT pin of audio processing chip K after resistance R14, the polar capacitor C9 that negative pole is then connected with the negative pole of polar capacitor C7, one end is connected with the BYP pin of audio processing chip K, the resistance R15 that the other end is connected with VS pin with the GAIN2 pin of audio processing chip K respectively, and one end is connected with the output of operational amplifier P, the resistance R12 that the other end is connected with the IN1 pin of audio processing chip K forms, the IN2 pin of described audio processing chip K is connected with the tie point of resistance R8 with resistance R7, GND pin ground connection, as system output while OUT pin is connected with its VS pin.
The utility model compared with prior art has the following advantages and beneficial effect:
1, audio frequency processing circuit of the present utility model, it can process for the large and small audio signal received, and the scope of audio frequency process is widened greatly.
2, be provided with audio processing chip K in audio frequency processing circuit of the present utility model, its can process small-signal while the noise of filtering out background, when avoiding small signal gain to amplify, background noise is also exaggerated, and affects audibility.
3, the utility model adds linear drive circuit, makes treatment system still keep very high stability when processing broadband signal.
Accompanying drawing explanation
Fig. 1 is overall structure schematic diagram of the present utility model.
Fig. 2 is the structural representation of the utility model linear drive circuit.
Embodiment
Below in conjunction with embodiment, the utility model is described in further detail, but execution mode of the present utility model is not limited to this.
Embodiment
As shown in Figure 1, a kind of high bandwidth of the present utility model from gain audio frequency processing system, primarily of signal acquisition circuit, the signal debug circuit be connected with signal acquisition circuit, the linear drive circuit be simultaneously connected with signal debug circuit and signal acquisition circuit, be connected with signal debug circuit from gain control circuit, the signal processing circuit be connected with linear drive circuit, the audio frequency processing circuit be connected with from gain control circuit forms.
As shown in Figure 2, described linear drive circuit is by driving chip U, triode VT5, triode VT6, triode VT7, triode VT8, positive pole is connected with signal debug circuit, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U after resistance R16, one end is connected with the collector electrode of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT7 after resistance R18, positive pole is connected with the base stage of triode VT5, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT5, the resistance R20 that the other end is connected with the base stage of triode VT6, one end is connected with the base stage of triode VT6, the resistance R19 that the other end is connected with the base stage of triode VT7, N pole is connected with the collector electrode of triode VT5, the diode D3 that P pole is connected with the collector electrode of triode VT6, positive terminal is connected with the collector electrode of triode VT5, the not gate Y that end of oppisite phase is connected with the collector electrode of triode VT8, one end is connected with triode VT8 emitter, the resistance R22 that the other end is connected with the emitter of triode VT7 after resistance R21, the end of oppisite phase of P pole NAND gate Y is connected, the diode D2 that N pole is connected with the tie point of resistance R21 with resistance R22 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT5, END pin ground connection, OUT pin are connected with the collector electrode of triode VT6, the collector electrode of triode VT6 is also connected with the base stage of triode VT8, its emitter is connected with the base stage of triode man VT7, the grounded collector of triode VT7, the N pole of diode D2 is connected with signal acquisition circuit and signal processing circuit simultaneously.Linear drive circuit, makes treatment system still keep very high stability when processing broadband signal.In order to ensure implementation result, described driving chip U is preferably LM387 integrated chip, its highly sensitive and low price.
Described signal acquisition circuit comprises potentiometer R1, resistance R4, resistance R5, polar capacitor C1, polar capacitor C3, triode VT1; The collector electrode of triode VT1 is connected with signal debug circuit, its emitter is then connected with the sliding end of potentiometer R1 after polar capacitor C1 as signal input part, its base stage after potentiometer R1 through resistance R5, polar capacitor C3 and resistance R5 is in parallel, one end of resistance R4 is connected with signal debug circuit, the other end is then connected with the tie point of potentiometer R1 with resistance R5, and the tie point of described resistance R5 and potentiometer R1 is connected with the N pole of diode D2 and signal processing circuit simultaneously.
Described signal debug circuit is by triode VT2, the polar capacitor C2 that negative pole is connected with the base stage of triode VT2, positive pole is connected with resistance R4, the potentiometer R3 that one end is connected with the emitter of triode VT2, the other end is connected with the collector electrode of triode VT1, and the potentiometer R2 that one end is connected with the emitter of triode VT2, the other end is connected with the positive pole of polar capacitor C2 forms; The emitter of triode VT2 also with from gain control circuit is connected, its collector electrode is then connected with the positive pole of electric capacity C10, and potentiometer R2 is all connected with the emitter of triode VT2 with the sliding end of potentiometer R3.
Described signal processing circuit is by triode VT4, the resistance R9 that one end is connected with the collector electrode of triode VT4, the other end is connected with from gain control circuit, the resistance R8 that one end is connected with the emitter of triode VT4, the other end is connected with audio frequency processing circuit, the resistance R7 that one end is connected with the tie point of audio frequency processing circuit with resistance R8, and the resistance R6 that one end is connected with the base stage of triode VT4, the other end is then connected with the N pole of diode D2 forms.
Described from gain control circuit by operational amplifier P, triode VT3, diode D1, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C4 that positive pole is then connected with the emitter of triode VT2, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C5 that positive pole is connected with the emitter of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R10 of other end ground connection, positive pole is connected with the base stage of triode VT3, the polar capacitor C6 of minus earth, and one end is connected with the P pole of diode D1, the resistance R11 that the other end is connected with the VS+ pin of operational amplifier P forms, the end of oppisite phase of described operational amplifier P is connected with resistance R9, its VS-pin is connected with external power source, output is connected with the tie point of resistance R8 and resistance R7 and audio frequency processing circuit simultaneously, and the P pole of diode D1 is connected with external power source, its N pole is then connected with the emitter of triode VT3.
Described audio frequency processing circuit is by audio processing chip K, positive pole is connected with the GAIN2 pin of audio processing chip K after resistance R13, the polar capacitor C7 that negative pole is connected with the GAIN1 pin of audio processing chip K after polar capacitor C8, positive pole is connected with the OUT pin of audio processing chip K after resistance R14, the polar capacitor C9 that negative pole is then connected with the negative pole of polar capacitor C7, one end is connected with the BYP pin of audio processing chip K, the resistance R15 that the other end is connected with VS pin with the GAIN2 pin of audio processing chip K respectively, and one end is connected with the output of operational amplifier P, the resistance R12 that the other end is connected with the IN1 pin of audio processing chip K forms, the IN2 pin of described audio processing chip K is connected with the tie point of resistance R8 with resistance R7, GND pin ground connection, as system output while OUT pin is connected with its VS pin.
As mentioned above, just well the utility model can be realized.
Claims (6)
1. a high bandwidth from gain audio frequency processing system, it is characterized in that: primarily of signal acquisition circuit, the signal debug circuit be connected with signal acquisition circuit, the linear drive circuit be simultaneously connected with signal debug circuit and signal acquisition circuit, be connected with signal debug circuit from gain control circuit, the signal processing circuit be connected with linear drive circuit, the audio frequency processing circuit be connected with from gain control circuit forms, described linear drive circuit is by driving chip U, triode VT5, triode VT6, triode VT7, triode VT8, positive pole is connected with signal debug circuit, the polar capacitor C10 that negative pole is connected with the IN1 pin of driving chip U after resistance R16, one end is connected with the collector electrode of triode VT5, the resistance R17 that the other end is connected with the base stage of triode VT7 after resistance R18, positive pole is connected with the base stage of triode VT5, the polar capacitor C12 that negative pole is connected with the IN1 pin of driving chip U, positive pole is connected with the IN2 pin of driving chip U, the polar capacitor C11 of minus earth, one end is connected with the emitter of triode VT5, the resistance R20 that the other end is connected with the base stage of triode VT6, one end is connected with the base stage of triode VT6, the resistance R19 that the other end is connected with the base stage of triode VT7, N pole is connected with the collector electrode of triode VT5, the diode D3 that P pole is connected with the collector electrode of triode VT6, positive terminal is connected with the collector electrode of triode VT5, the not gate Y that end of oppisite phase is connected with the collector electrode of triode VT8, one end is connected with triode VT8 emitter, the resistance R22 that the other end is connected with the emitter of triode VT7 after resistance R21, the end of oppisite phase of P pole NAND gate Y is connected, the diode D2 that N pole is connected with the tie point of resistance R21 with resistance R22 forms, the VCC pin of described driving chip U is connected with the base stage of triode VT5, END pin ground connection, OUT pin are connected with the collector electrode of triode VT6, the collector electrode of triode VT6 is also connected with the base stage of triode VT8, its emitter is connected with the base stage of triode man VT7, the grounded collector of triode VT7, the N pole of diode D2 is connected with signal acquisition circuit and signal processing circuit simultaneously.
2. a kind of high bandwidth according to claim 1 from gain audio frequency processing system, it is characterized in that: described signal acquisition circuit comprises potentiometer R1, resistance R4, resistance R5, polar capacitor C1, polar capacitor C3, triode VT1; The collector electrode of triode VT1 is connected with signal debug circuit, its emitter is then connected with the sliding end of potentiometer R1 after polar capacitor C1 as signal input part, its base stage after potentiometer R1 through resistance R5, polar capacitor C3 and resistance R5 is in parallel, one end of resistance R4 is connected with signal debug circuit, the other end is then connected with the tie point of potentiometer R1 with resistance R5, and the tie point of described resistance R5 and potentiometer R1 is connected with the N pole of diode D2 and signal processing circuit simultaneously.
3. a kind of high bandwidth according to claim 2 from gain audio frequency processing system, it is characterized in that: described signal debug circuit is by triode VT2, the polar capacitor C2 that negative pole is connected with the base stage of triode VT2, positive pole is connected with resistance R4, the potentiometer R3 that one end is connected with the emitter of triode VT2, the other end is connected with the collector electrode of triode VT1, and the potentiometer R2 that one end is connected with the emitter of triode VT2, the other end is connected with the positive pole of polar capacitor C2 forms; The emitter of triode VT2 also with from gain control circuit is connected, its collector electrode is then connected with the positive pole of electric capacity C10, and potentiometer R2 is all connected with the emitter of triode VT2 with the sliding end of potentiometer R3.
4. a kind of high bandwidth according to claim 3 from gain audio frequency processing system, it is characterized in that: described signal processing circuit is by triode VT4, one end is connected with the collector electrode of triode VT4, the resistance R9 that the other end is connected with from gain control circuit, one end is connected with the emitter of triode VT4, the resistance R8 that the other end is connected with audio frequency processing circuit, the resistance R7 that one end is connected with the tie point of audio frequency processing circuit with resistance R8, and one end is connected with the base stage of triode VT4, the resistance R6 that the other end is then connected with the N pole of diode D2 forms.
5. a kind of high bandwidth according to claim 4 from gain audio frequency processing system, it is characterized in that: described from gain control circuit by operational amplifier P, triode VT3, diode D1, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C4 that positive pole is then connected with the emitter of triode VT2, negative pole is connected with the normal phase input end of operational amplifier P, the polar capacitor C5 that positive pole is connected with the emitter of triode VT3, one end is connected with the collector electrode of triode VT3, the resistance R10 of other end ground connection, positive pole is connected with the base stage of triode VT3, the polar capacitor C6 of minus earth, and one end is connected with the P pole of diode D1, the resistance R11 that the other end is connected with the VS+ pin of operational amplifier P forms, the end of oppisite phase of described operational amplifier P is connected with resistance R9, its VS-pin is connected with external power source, output is connected with the tie point of resistance R8 and resistance R7 and audio frequency processing circuit simultaneously, and the P pole of diode D1 is connected with external power source, its N pole is then connected with the emitter of triode VT3.
6. a kind of high bandwidth according to claim 5 from gain audio frequency processing system, it is characterized in that: described audio frequency processing circuit is by audio processing chip K, positive pole is connected with the GAIN2 pin of audio processing chip K after resistance R13, the polar capacitor C7 that negative pole is connected with the GAIN1 pin of audio processing chip K after polar capacitor C8, positive pole is connected with the OUT pin of audio processing chip K after resistance R14, the polar capacitor C9 that negative pole is then connected with the negative pole of polar capacitor C7, one end is connected with the BYP pin of audio processing chip K, the resistance R15 that the other end is connected with VS pin with the GAIN2 pin of audio processing chip K respectively, and one end is connected with the output of operational amplifier P, the resistance R12 that the other end is connected with the IN1 pin of audio processing chip K forms, the IN2 pin of described audio processing chip K is connected with the tie point of resistance R8 with resistance R7, GND pin ground connection, as system output while OUT pin is connected with its VS pin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420738286.9U CN204408610U (en) | 2014-11-29 | 2014-11-29 | A kind of high bandwidth from gain audio frequency processing system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420738286.9U CN204408610U (en) | 2014-11-29 | 2014-11-29 | A kind of high bandwidth from gain audio frequency processing system |
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| Publication Number | Publication Date |
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| CN204408610U true CN204408610U (en) | 2015-06-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420738286.9U Expired - Fee Related CN204408610U (en) | 2014-11-29 | 2014-11-29 | A kind of high bandwidth from gain audio frequency processing system |
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| CN (1) | CN204408610U (en) |
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- 2014-11-29 CN CN201420738286.9U patent/CN204408610U/en not_active Expired - Fee Related
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Granted publication date: 20150617 Termination date: 20151129 |